JPH07282599A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device capable of performing a device test without depending on the address scrambling procession of a tester. CONSTITUTION:An address scrambler 20 changing selectively the logical value of an address signal in between the column address latch 13 and the column address decoder 9 of a dynamic RAM 1. When an operation is instructed by an address scrambler control signal ASC, the address scrambler 20 executes an address scrambling procession to supply an address signal in which the arrangement of the prescribed bits is changed to the address decoder 9. Since the address scrambling procession is performed in the inside of the semiconductor storage device, the device test of the semiconductor storage device is performed without being restricted by the throughput of a connected tester or the function of a soft ware mounted on the tester.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address scramble technique for a semiconductor memory device, for example, dynamic RA.
The present invention relates to a technique effective when applied to a device test such as selection / analysis of a defective bit of M (random access memory).

[0002]

2. Description of the Related Art In a device test such as a defective bit analysis of a semiconductor memory device, a tester is connected to a target semiconductor memory device to perform read / write processing in memory cell units. The tester has a fail bit map, and records test results such as fail / pass of each memory cell in corresponding bits on the fail bit map. Further, the tester is equipped with software that scrambles the supplied address value in accordance with the address mapping of the semiconductor memory device to be tested. Due to the function of the software, the test result of each memory cell is not a bit corresponding to an address value based on the address decode logic of the semiconductor memory device on the fail bit map, but a bit at a physically corresponding position. Will be recorded. Thus, by analyzing the fail bit map, the physical position of the defective bit on the memory array can be specified, and the cause of the defect such as interference between memory cells can be clarified.

[0003]

However, in the conventional technique of performing the address scrambling process on the tester side by software, the following problems exist in specifying and analyzing the position of the defective bit. Found by the inventor.

First, it is necessary to create corresponding software for each address mapping of the memory array. The address array of the memory array of the semiconductor memory device depends on the configuration unique to the semiconductor memory device, and if the semiconductor memory device to be tested has a different function or configuration, the physical arrangement order of the memory cells also depends on the decode logic. The address mapping specified in 1) is also different. Therefore, it is necessary to develop software having an address scramble logic corresponding to the semiconductor memory device for each address mapping unique to the semiconductor memory device.

Secondly, depending on the processing capacity of the tester,
There is a limit to the address scrambling process that can be realized by software. For example, when testing a semiconductor memory device having a complicated address arrangement such as a hierarchical address mapping configuration, software for performing the address scrambling process becomes complicated. Therefore, depending on the specifications of the tester, the processing capacity may be insufficient and the semiconductor memory device may not be evaluated.

An object of the present invention is to provide a semiconductor memory device capable of performing address scrambling processing without depending on a tester. More specifically, an address scrambler is incorporated in the semiconductor memory device, regardless of the address mapping of the semiconductor memory device.
The address scrambling process on the tester side is performed by selectively changing the value of the address signal so that the test result of each memory cell can be recorded in the bit corresponding to the physical position on the fail bit map provided in the tester. It is an object of the present invention to provide a semiconductor memory device capable of performing a device test such as evaluation / analysis without depending on the capability of a tester by making it unnecessary.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a plurality of memory cells are arranged in a matrix on the memory array. An address scrambler for selectively changing the input address signal and supplying it to the address decoder is provided. The address decoder decodes the supplied address signal and outputs a selection signal for the memory cell.

Further, it is possible to instruct the operation of the address scrambler by a signal having a level higher than a signal level which can take a binary logical value supplied from the outside.

Further, the address scrambler includes a gate means for changing a bit arrangement, and performs an address scramble process by converting a logical value of the input address signal by changing a predetermined bit arrangement of the input address signal. You can

[0012]

According to the above means, the address scrambler whose operation is selected by the instruction of the signal input from the external terminal or the like is provided inside the semiconductor memory device, so that the address scramble process is performed at an arbitrary timing. be able to. As a result, the logic value of the input address signal is changed so that the address of each memory cell is not the address value determined by the decode logic of the address decoder but the address value corresponding to the linear address space. Since it can be performed internally, the address scrambling process on the tester side is not necessary.

[0013]

1 shows a dynamic RAM which is an embodiment of a semiconductor memory device according to the present invention. Although not particularly limited, the dynamic RAM 1 shown in the same figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In FIG. 1, a plurality of memory cells 3 are arranged in a matrix in the memory array 2. Although not particularly limited, the memory array 2 is of a two-intersection (folded bit line) system, and a complementary bit line pair Di, Di * (this specification is shown as a single line in FIG. 1). In the figure, the symbol * means that the signal is level-inverted with respect to the signal without the symbol, and that the signal with the symbol is a low active signal. It is arranged horizontally. In addition, word lines W0 to Wm are provided in a direction intersecting the complementary bit line pair. Further, the memory cells 3 are arranged at the intersections of the complementary bit lines and the word lines, respectively. Although not particularly limited, the memory cell 3 is a so-called one-element type dynamic memory cell, and each is composed of an information storage capacitor (storage capacity) and an address selection transistor.

The drains of the address selecting transistors of the memory cells 3 arranged in the same column of the memory array 2 are
The corresponding complementary bit lines are alternately coupled to the non-inverted signal lines or the inverted signal lines with a predetermined regularity. Further, the gates of the address selecting transistors of the memory cells 3 arranged in the same row of the memory array 2 are commonly coupled to the corresponding word lines. A predetermined cell plate voltage is commonly supplied to the other electrode, that is, the cell plate of the information storage capacitor of each memory cell 3.

According to this embodiment, the memory array 2
Is divided into four memory mats 2a to 2d, and the word lines W0 to Wm are common to the memory mats 2a to 2d. The word lines W0 to Wm included in the memory array 2 are alternatively driven to a selection level by an output selection signal of the row address decoder 4.

A precharge circuit (not shown) is coupled to the complementary bit lines forming the memory array 2. By the precharge circuit, the complementary bit lines are precharged to about half the level of the high-level power supply voltage during the chip non-selection period, for example, if the high level is set to 5V, that half is 2.5V. Further, although not shown in the drawing, for example, a static latch type sense amplifier is coupled to each complementary bit line, and the minute potential difference of the complementary bit line is amplified by the sense amplifier.

When the chip of the dynamic RAM 1 is selected, a minute potential difference is generated on the complementary bit line due to the amount of charges accumulated in the memory cells coupled to the selected word line.
At the time when the minute potential difference is established in the corresponding complementary bit line, the sense amplifiers are activated all at once to be in the operating state. The sense amplifier amplifies a minute potential difference read from a memory cell coupled to a selected word line to a complementary bit line in its operating state, and outputs it as a high level or low level binary read signal. These binary read signals are rewritten to the corresponding memory cells to refresh the stored data when the dynamic RAM is in the read mode or refresh cycle.

The complementary bit lines of the memory mats 2a to 2d are commonly connected to the corresponding first complementary common data lines 7a to 7d via the column selection circuits 5a to 5d, and the first complementary common data lines 7a to 7d. Are commonly connected to the second complementary common data line pair 7e via the column selection circuit 6. Switch element Qm included in the column selection circuits 5a to 5d
Is controlled by the column selection signal output from the first column address decoder 8 and the switch elements Qa to Qd included in the column selection circuit 6 are switch-controlled by the column selection signal output from the second column address decoder 9. It The switch elements included in the column selection circuits 5a to 5d, 6 are turned on by setting the corresponding column selection signal to the high level.

The complementary common data line pair 7e is coupled to a data input / output circuit 10 such as a data input / output buffer via a main amplifier 31 for amplifying read data or a write amplifier 32 for amplifying write data, and these are connected. Interface with the outside via.

The dynamic RAM 1 receives an address signal supplied in a multiplex format in the address buffer 11 although it is not particularly limited. As for the address signal received by the address buffer 11, for example, the row address latch 12 holds the row address signals A0 to A4, and the column address latch 13 holds the column address signals A5 to A.
Hold 9 The row address signals A0 to A4 held in the row address latch 12 are supplied to the row address decoder 14, and the row address decoder 14 decodes the row address signal and selects one word line Wi corresponding thereto. To do.

The upper bits A5 to A7 of the column address signals A5 to A9 held in the column address latch 11 are supplied to the first column address decoder 8, and the first column address decoder 8 , The upper 3 bits of the column address signal are decoded, and one complementary bit line pair Di, Di * corresponding thereto is selected for each memory mat. Further, the lower 2 bits A8 and A9 of the column address signal are supplied to the second column address decoder 9 via the address scrambler 20, and the second column address decoder 9 outputs the lower 2 bits of the column address signal. A bit is decoded, and one complementary data line pair corresponding thereto is selected from the complementary data line pairs 7a to 7d. Details of the address scrambler 20 will be described later.

In addition, a row address strobe signal RAS *, a column address strobe signal CAS *, a write enable signal WE * for instructing a read / write operation, and an address scrambler control signal ASC are used as access control signals. Entered in. The row address strobe signal RAS * indicates that the address signal supplied in the multiplex format is a row address signal by its low level and also functions as a chip selection signal. The column address strobe signal CAS * indicates, by its low level, that the supplied address signal is a column address signal.

The address scrambler control signal AS
When C is set to a level higher than a signal level that can take a binary logical value, the control circuit 40 sets the address scrambler control signal φ to a significant level, for example, a high level, and the address scrambler 20 for,
Address scramble processing is instructed.

FIG. 2 shows a part of an example circuit diagram of the memory mat 2a and the column selecting circuits 5a and 6 described above.
In the figure, S1 to S12 are memory cell selection signals obtained by decoding the respective input address signals, S1 to S8 are selection signals obtained by decoding the 3 bits of the column address signals A5 to A7, S9 to S12 represent selection signals obtained by decoding the 2 bits of the column address signals A8 and A9. In this embodiment, the selection signals S1 to S8 select the complementary bit line pairs Di and Di * in each memory mat, and the selection signals S9 to S8.
A memory mat is selected by 12.

Although not shown in particular, the row address signals A0 to A4 are also decoded by the function of the row address decoder 14 to obtain respective selection signals, and the word lines Wi are selected by the selection signals.

FIG. 3 shows an example of the address mapping defined by the decode logic of the decoder of the memory array of the semiconductor memory device having a capacity of 1 KB, and FIG. 4 shows the memory cell on the memory array of the semiconductor memory device. The respective physical arrangements of are shown. In FIG. 3, A8 and A9
Indicates the least significant 2 bits of the column address signal, and 2
Reference numerals a, 2b, 2c and 2d denote memory mats specified by selection signals obtained by decoding 2 bits of A8 and A9, respectively. Further, in FIGS. 3 and 4, $ 1 to $ 1
Reference numeral 024 indicates an individual memory cell on the memory array. The above $ 1 to $ 1024 in FIG. 3 can be regarded as addresses on the memory array defined by the address decoder. Also, the above $ 1 to $ 1 in FIG.
024 can also be regarded as an address obtained as a result of the address scrambling process or an address corresponding to the address of the fail bit map of the tester. As described above, the logical address arrangement order shown in FIG. 3 and the physical memory cell arrangement order shown in FIG. 4 are different as shown by the positional relationship between the memory mats 2b and 2c. Do not match.

In the case of the semiconductor memory device having the structure of the memory mat shown in FIG. 3, if the address arrangements of the memory mats 2b and 2c are exchanged, the physical memory cell arrangement of the memory array shown in FIG. The address arrangement order is the same as. This is because when the logical values of the least significant bits A8 and A9 of the column address signal do not match, in other words, when A8 = 1 and A9 = 0, and when A8 = 0 and A.
When 9 = 1, if the bit arrangement of A8 and A9 is changed, the same arrangement as in FIG. 4 can be obtained. In the present embodiment, when the logical values of A8 and A9 are judged to be inconsistent with each other and the address scrambler control signal φ indicates the operation of the address scrambler, the A
The bit arrangement of 8 and A9 may be changed. The above series of processes is called address scrambling process.

FIG. 5 shows an example circuit diagram of the address scrambler 20. In the figure, the address scrambler 20 has input terminals IN1, IN2, IN3,
It is composed of an exclusive OR gate 201, a NAND gate 203, switching circuits TG1 to TG4 and the like. The switching circuits TG1 to TG4 are, for example, CMOS transfer gates, although not particularly limited thereto.

In FIG. 5, the input signals of the least significant 2 bits A8 and A9 of the column address signal are input terminals I respectively.
The signals are supplied to the exclusive OR gate 201 from N1 and IN2, and output a low level signal when both inputs match and a high level signal when they do not match. This output and the address scrambler control signal φ are connected to the NAND gate 203.
Is supplied to. By the output Vc of the NAND gate 203 and its inverted signal Vc *, the switching circuit T
G1 to TG4 are controlled.

In the above, when φ is high level,
The output Vc of the NAND gate 203 is the inverted output of the exclusive OR gate 201, and
When the logical values of 8 and A9 match, a high level is output. When φ is low level, the above NAN
As the output Vc of the D gate 203, a high level is output regardless of the output value of the exclusive OR gate 201.

When the output Vc of the NAND gate 203 is at the high level, the TG of the transfer gates is selected.
1 and TG4 are turned on, and TG2 and TG3 are turned off. At this time, A8 input from IN1 is output from OUT1, and similarly A9 input from IN2 is output from OUT2. In this case, the bit arrangement of A8 and A9 is not changed. Similarly, when the output Vc of the NAND gate 203 is at a low level, TG1 and TG4 are turned off and TG2 and TG3 are turned on. At this time, A8 input from IN1 is output from OUT2, and A9 input from IN2 is output from OUT1. In this case, the bit arrangement of the column address signals A8 and A9 is changed.

According to the above address scrambler 20,
When the address scrambler control signal φ is high level,
Moreover, the bit arrangement of the column address signal is changed only when the logical values of the column address signals A8 and A9 are different. Therefore, due to the arrangement change, the address mapping by the decode logic of the address array and the physical memory cell arrangement order of the address array are made equal.

According to this embodiment, there are the following effects.
By incorporating the address scrambler 20 inside the semiconductor memory device and controlling its activation by a signal supplied from an external terminal, address scrambling can be performed at an arbitrary timing. Address scrambler 20
Thus, the value of the input address signal is changed to a value indicating the physical arrangement order of the memory cells on the memory array, in other words, the position corresponding to the linear address space of the fail bit map of the tester. Therefore, it is not necessary to perform the address scramble process on the tester side, and the device test can be performed without being restricted by the processing capability of the connected tester.

Further, it becomes unnecessary to develop software having an address scramble function for each address mapping of the semiconductor memory device to be tested.

Further, if the address scrambling process is performed by changing the arrangement of the predetermined bits of the input address signal, the structure of the address scrambler can be simplified, and the address scrambler is added to realize the above function. The circuit used is also small.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

For example, the semiconductor memory device according to the present invention is not limited to the dynamic RAM, but can be applied to various semiconductor memory devices such as a static RAM which is conditioned to enable read / write operation.

The configuration of the address scrambler is not limited to the above example. It is also possible to adopt a configuration in which the level of the input address signal is inverted by using, for example, an arithmetic circuit.

Furthermore, the capacity of the semiconductor memory device according to the present invention is not limited to 1 KB, and the address mapping and address signal formats are not limited to this example.

In the above description, the invention made by the present inventor was mainly applied to the address scrambling technique of a single semiconductor memory device which is the background field of use, but the present invention is not limited thereto. Instead, it is a technology that is effective when applied to the on-chip memory of a microcomputer.

[0042]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by providing the address scrambler inside the semiconductor memory device, the address scramble processing can be performed without using the function of the connected tester. As a result, the device test of the semiconductor memory device can be performed without being limited by the processing capability of the tester or the function of software installed in the tester.

By controlling the address scrambler by a signal supplied from an external terminal or the like, the address scramble processing can be performed at an arbitrary timing.

Furthermore, if the address scrambler is of a type in which the address scrambling process is performed by changing the arrangement of predetermined bits of the input address signal, a simple structure having an arrangement changing gate can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor memory device that is an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of the memory array and column selection circuit shown in FIG.

FIG. 3 is an explanatory diagram showing an example of a logical address arrangement of the semiconductor memory device according to the present invention.

FIG. 4 is an explanatory diagram showing an example of the memory array of the semiconductor memory device shown in FIG. 3 when address scrambling is performed.

5 is a circuit diagram of an example of the address scrambler shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 dynamic RAM 2 memory array 2a-2d memory mat 3 memory cells 5a-5d 1st column selection circuit 6 2nd column selection circuit 8 1st column address decoder 9 2nd column address decoder 11 address buffer 12 row address Latch 13 Column address latch 14 Row address decoder 20 Address scrambler Di, Di * Complementary bit line pair W0 to Wm Word line IN1, IN2, IN3 Address scrambler input terminal OUT1, OUT2 Address scrambler output terminal TG1, TG2 TG3, TG4 Transfer gate 201 Exclusive OR gate 203 NAND gate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeo Kizaki 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Hiratsuru ELS Engineering Co., Ltd. (72) Inventor Kazuo Yoshikawa Kodaira, Tokyo 5-20-1, Josui Honmachi, Ichi, Japan

Claims (3)

[Claims] 1. A memory array in which a plurality of memory cells are arranged in a matrix, an address decoder for decoding an address signal supplied from the outside to form a memory cell selection signal, and a memory cell selected by the selection signal. In a semiconductor memory device having means for enabling read / write, the logical address arrangement order of the memory cells defined by the selection signal obtained by decoding the address signal is set on the memory array. A semiconductor memory device, comprising: an address scrambler for selectively changing a logical value of a predetermined bit of the input address signal so as to be equal to a physical arrangement order of memory cells. 2. An external terminal for receiving a signal of a level higher than a signal level capable of taking a binary logical value supplied from the outside in order to instruct the logical value of the input address signal to be changed by the address scrambler. The semiconductor memory device according to claim 1, further comprising: 3. The address scrambler has a gate means for selectively changing the arrangement of predetermined bits of the input address signal, and the logic of the input address signal is changed by changing the bit arrangement by the gate means. 3. The semiconductor memory device according to claim 1, wherein the value is changed.