JPS62121997A - Dynamic ram - Google Patents

Abstract

PURPOSE:To quickly clear stored information by making a sense amplifier operable after a write signal is transmitted to plural data lines simultaneously selected. CONSTITUTION:Transistors Q3, Q4-Q5 and Q6 are controlled through a column address buffer C-ADB corresponding to an address and through a column decoder C-DCR, and plural pairs of data lines DL and their inversion DL are selected. Then a write signal from a data input terminal Din is transmitted to the selected data line DL and its inversion DL, and transistors Q1 and Q2 mutually connected to the sense amplifier SA are controlled. Then the sense amplifier SA is made operable, and data is speedily written in plural dynamic RAM cells. If the buffer C-ADB, etc., are controlled to divide the group made of pairs of data lines into blocks and any of them are selected, stored information can be cleared at every block, and clearing of stored information can be made at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a dynamic RAM, and relates to a technique effective for use in, for example, a RAM for graph ink.

[Background technology]

A semiconductor memory device such as a dynamic RAM is accessed in relatively small bit units such as 1 bit, 4 bits, or 8 bits. Therefore, as the storage capacity of RAM increases with the progress of semiconductor technology, an enormous number of cycles are required to write test patterns and initial information for testing. In particular, graphics RAM that stores image data for drawing images on a CRT (cathode ray tube) display.
, screen clearing operations often occur, so speeding up the screen clearing operation is desired.

Regarding the dynamic RAM, see, for example, Japanese Patent Laid-Open No. 82282/1982.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic RAM with an added function that allows stored information to be cleared at high speed.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, according to a control signal supplied from an external terminal or a combination of a plurality of control signals, a plurality of data lines are simultaneously selected and write No. 16 is transmitted to the plurality of simultaneously selected data lines, and then the sense amplifier is activated. This is to put it into operation.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a dynamic RAM according to the present invention. Each circuit element or circuit block in the figure is formed on a single semiconductor substrate, such as single crystal silicon, using known semiconductor integrated circuit manufacturing techniques, although this is not particularly limited.

A 1-bit memory cell MC, as shown as a representative, has an information storage capacitor Cs and an address selection M
The information of logic "1" and "θ" is stored in the form of whether the capacitor C8 has a charge or not. To read information, turn on the MO5FETQm, connect the capacitor Ca to the common data line DL, and sense how the potential of the data line DL changes depending on the amount of charge accumulated in the capacitor Cs. It is done by °ζ. Since the memory cells MC are formed small and many memory cells are connected to a common data line DL to form a memory matrix with a high M product and a large capacity, the stray capacitance of the capacitor Cs and the common data line DL increases! co
(not shown), the ratio of Cs/G o becomes a very small value.

Therefore, the change in the potential of the data line DL due to the amount of charge accumulated in the capacitor Cs is a very small signal.

Although not particularly limited, a dummy cell DC is provided as a reference for detecting such a minute signal.

This dummy cell DC is manufactured under the same manufacturing conditions and the same design constants as the memory cell MC, except that the capacitance value of the capacitor Cd is half that of the capacitor Cs of the memory cell MC. Prior to addressing, capacitor Cd receives timing signal φd (O3F
Charged to ground potential by ETQd'. In this way, since the capacitance value of capacitor Cd is set to approximately half that of capacitor Cs, memory cell MC
This will form a reference voltage equal to half the read signal from the source.

In the same figure, SA uses a timing signal (sense amplifier control signal) φPal+φpa to compensate for the difference in potential change caused by the above-mentioned addressing in the normal operation mode.
It is a sense amplifier that expands to the sense period determined by 2 (
Its operation will be described later), and its output node is coupled to a pair of complementary data lines DL, DL arranged in parallel. The numbers of memory cells coupled to complementary data lines DL, DL are made equal to increase detection accuracy, and one dummy cell is coupled to each of DL, DL.

Furthermore, each memory cell MC is coupled at the intersection between one word line WL and one of the complementary pair data lines. Since each word line WL crosses both data line pairs, even if a noise component generated on the word line WL is transferred to the data line due to capacitive coupling, the noise component will be transferred to both data line pairs DL, D.
It appears equal to L and is canceled by the differential sense amplifier SA.

In the above addressing, complementary data line pair DL, D
When a memory cell MC coupled to one of the data lines L is selected, one of the pair of dummy word lines DWL, DWL is selected so that the dummy cell DC is always coupled to the other data line.

Although not particularly limited, the sense amplifier SA has a pair of cross-connected MO3FETs QI and Q2, and differentially amplifies minute signals appearing on the complementary data lines DL and DL by the positive feedback action of these MO3FETs. . This positive feedback operation is 2
The process is performed in stages, and starts at the same time that MO3FETQ7, which has a relatively small conductance characteristic, starts to conduct by a relatively early timing signal φpa1.
Based on the potential difference applied to the complementary data lines DL and DL by addressing, the higher data line potential falls at a slower rate and the lower one at a faster rate, while the difference widens and falls.At this time, the above potential difference increases. Since the MO5FET Q8, which has a relatively large conductance characteristic, is made conductive by the timing signal φpa2 at a certain timing, the lower data line potential rapidly decreases.

By operating the sense amplifier SA in two stages in this manner, the drop in the higher potential is prevented. In this way, the lower potential is the cross-coupled MOSFET.
The positive feedback operation ends when the voltage drops below the threshold voltage of The potential (Ov) is reached.

During the above-mentioned addressing, the stored information in the memory cell MC, which is about to be destroyed, is recovered by directly receiving the high-level or low-level potential obtained by this sensing operation. However, as described above, if the high level drops to a certain level or more with respect to the power supply voltage VCC, a malfunction will occur where the data will be read as a logic "0" while reading and rewriting are repeated several times. An active restore circuit AR is provided to prevent this malfunction. This active restore circuit AR has the function of selectively boosting only high level signals to the potential of power supply voltage Vcc without having any effect on low level signals. Since the specific circuit configuration of such active restore circuit AR is not directly related to the present invention, detailed explanation thereof will be omitted.

A data line pair DL, which is shown as a representative in the figure,
DL is MO3FETQ that constitutes column switch CW
3. Common complementary data line pair CDL, CDL via Q4
connected to. Similar MO5FETQ5. It is connected to the common complementary data line pair CDL, CDL via Q6. This common complementary data line pair CDL, CDL is connected to an input terminal of a data output buffer sofa DOB including an output amplifier and an output terminal of a data input buffer sofa DIB.

Row address decoder R-DCR and column address buffer CD CR are row address buffer R-AD
Addressing of memory cells and dummy cells is performed by forming one word line, dummy word line and column switch selection signals in response to internal complementary address signals formed by column address buffer C-ADB and column address buffer C-ADB, respectively. External address signals AXO to AXi are sent to address buffers R-AD in synchronization with timing signal φar generated by row address strobe signal RAS.
B, and transmits the internal complementary address signal formed from this to the row address decoder R-DCR,
A predetermined word line and dummy word line selection operation according to the address decoder R-OCR is performed by the word line selection timing signal φX.

In addition, external address signals AYO to AYi are sent to column address buffers C-ADB in synchronization with timing signal φac generated by column address strobe signal CAS.
The internal complementary address signal generated therefrom is transmitted to the column decoder C-0CR, and a data line selection operation is performed in accordance with the data line selection timing signal φy. Although not particularly limited, the above column decoder C-DC
As will be described later, in order to simultaneously select all data lines, R is added with a function of setting the internal complementary address signals to the same selection level in the clear operation mode.

The timing control circuit TC receives a row address strobe signal RAS, a column address strobe signal CAS, and a write enable signal WE supplied from external terminals, identifies its operation mode, and is formed accordingly. In addition to the above timing signals, it forms various time-series timing signals required for memory operations.

Note that, although not particularly limited, in order to reduce power consumption and enable continuous read operation (static column mode) by switching the column address signal with the word line in the selected state, the column system address buffer 1 and The address decoder and data output sofa DOB are composed of CMOS (complementary type) static type circuits.

FIG. 2 shows a circuit diagram of an embodiment of the unit circuit UADB that constitutes the column address buffer C-ADB.

Address signal AYn supplied from an external terminal is supplied to one input of a NAND gate circuit G1. The other input of this Nant gate circuit G1 is supplied with a timing signal φac which is set to a high level when the column address strobe signal CAS is at a low level. An internal address signal an having a phase opposite to that of the external address signal AYn is formed from the output of the Nant gate circuit G1. For example, when the column decoder circuit C-DCR forms a column selection signal using a NOR gate circuit, the output signal of the NOR gate circuit Gl is supplied to one input of the NOR gate circuit G2. The other input of this NOR gate circuit G2 is supplied with a control signal we' generated during a clearing operation, which will be described later. An internal address signal an having the same phase as the external address signal AYn during normal operation is formed from the output of the NOR gate circuit G2. Other unit circuits are also constituted by circuits similar to those described above. The control signal we'' is commonly supplied to each unit circuit.

For example, in a normal write/read operation, the control signal we' is set to a low level (logic 10'''). Therefore, the NOR gate circuit G2 operates similarly to an inverter circuit, so the internal address signal an
and an are mutually complementary signals. During the clearing operation, the control signal W6' is set to high level (logic "1"), and therefore the external address signal AY
Internal address signal an can be set to low level regardless of n. As a result, if, for example, the external address signal AYn is set to high level, the inverted internal address signal an also becomes low level, and both address signals Dn and a are set to high level.
Both n are set to a low selection level. When all internal address signals of the column system are set to low level, all of the column decoder circuits C-DCH having a NOR gate configuration that receive the signals form high level selection signals.

When one specific bit of the external column address signal is set to low level, only one bit of the inverted internal address signal is set to high level.

As a result, only half of the output signals of the column decoder circuit C-DCR are set to the selection level.

In this way, it is possible to form simultaneous selection signals consisting of various combinations. That is, by clearing the memory cells in the necessary area in the memory array MARY, it is possible to avoid problems such as an increase in power consumption due to an undesired clearing operation of the memory cells.

When the column decoder circuit C-DCR is configured to form a column selection signal using a circuit other than a NOR gate circuit, the setting of the external address signal is also changed accordingly.

Next, the clearing operation will be explained with reference to the timing diagram shown in FIG.

During clearing operation, the row address strobe signal RAS
The write enable signal WE is set to low level prior to the low level of . This means that the timing control circuit TC
is identified, and the control miK signal we' is set to high level. At this time, a signal to be written is supplied from the external terminal Din.

In addition, the operation timing signal φpa1 of the sense amplifier SA
．． The timing of generation of φpa is delayed as described later.

That is, when the row address strobe signal RAS is set to low level, the external address signal supplied in synchronization with it is regarded as the row address signal X1 and is sent via the row address buffer R-ADH which is activated at that time. The signal is transmitted to the row decoder circuit R-DCR.

For example, the word line WL1 and the dummy word line DWL designated by the selection signal formed by the row decoder circuit R-DCH are set to a high selection level in synchronization with the word line selection timing signal φX. This causes the complementary data line DL.

The storage information of the memory cell and the reference voltage from the dummy cell are transmitted to DL. In a normal write/read operation, the sense amplifier SA timing signal φPal+φpa2 is generated after the word line selection operation, but during the clear operation, it is maintained at a low level. This causes the sense amplifier SA to remain inactive.

Next, when the column address strobe signal CAS is set to low level, the external address signal supplied in synchronization with it is regarded as the column address signal Y1 and is sent via the row address buffer R-ADH which is activated at that time. and is transmitted to the row decoder circuit R-DCR. At this time, when all data lines are selected simultaneously, all bits of the address signal Y1 are set to high level.

Each unit circuit of the row decoder circuit R-OCR is
By setting all the input signals to low level, respective high level selection signals are formed. All complementary data lines DL, DL are set by these all selection signals.
They are coupled to common complementary data lines CDL and CDL, respectively, in synchronization with data line selection timing signal φy.

At the same time, the operation timing signal φaha of the main amplifier of the data input buffer sofa DIB is generated, and the write signal supplied from the external terminal Din is amplified and transmitted to the common complementary data lines CDL, CDL. At this time,
Common complementary data line CDL.

Therefore, the data lines DL and DL have a level difference according to the write signal. That is, all complementary data lines DL, DL are connected to common complementary data lines CDL, CDL.
As a result, a large load capacitance is coupled to the main amplifier, and therefore, unlike a normal write operation, only a slight level difference occurs between the individual data lines DL and DL within a relatively short period of time.

Therefore, in this embodiment, a sense amplifier SA is used in order to perform simultaneous writing to all data lines DL and DL at high speed. That is, the operation timing signal φpaLφpa2 of the sense amplifiers S and A is connected to the complementary data line D.
It is set to high level at the timing when a slight level difference occurs between L and DL according to the write signal. As a result, complementary data IJIIDL is generated by a positive feedback amplification effect similar to the read operation.

DL is made high-level and low-level at high speed, and is directly transmitted to the information storage capacitor Cs of the memory cell. In addition, the active restore circuit AR
is brought into the 11ttlJ operating state, and the dropped high level on the data line from which the sense amplifier SA operates and the low level is read from the selected memory cell is restored to a high level such as the power supply voltage Vcc.

Thereafter, the row address strobe signal RAS is once set to high level and the next row address signal X2 is taken in to switch the word line to be selected, thereby writing the same write signal to the memory cell. It should be noted that if the active restore circuit AR is brought into operation each time the word lines are switched, it is possible to prevent the high level data line from dropping. Note that when changing the signal to be written for each word line, the same operation as above may be performed.

〔effect〕

(1) Complementary data lines that are set to a small write level by simultaneous selection by simultaneously bringing multiple complementary data lines into a selected state and transmitting a scan signal to each complementary data line to put a sense amplifier into an operating state. can be amplified to high and low levels. This provides the effect that all memory cells coupled to the word line in the selected state can be simultaneously written.

(2) Through (1) above, test pattern writing for memory testing and initial settings (graphic RAM
) can be performed at high speed.

When a RAM that is accessed in units of 1 bit has a storage capacity of ft<N bits, all bits can be written in as few as N cycles.

(3) For simultaneous selection of data lines, by providing a gate circuit in the address buffer and setting the level to instruct selection to the address decoder during clearing operation,
Simultaneous selection can be performed by dividing the data line into blocks. This provides the effect that, for example, in a graphic RAM, an image in a certain area can be cleared.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the control signal instructing the clearing operation may be supplied from an independent external terminal.

Further, the unit that simultaneously selects the data lines may be provided with a gate circuit at the output section of the decoder circuit, and may form a selection signal independently of the output of the decoder circuit during the clear operation. Further, in the dynamic RAM, the row address signal and the column address signal may be supplied from independent external terminals. Also,
The complementary data line of the memory array M-ARY may be precharged to Vcc/2, and a half precharge method (dummy cellless method) may be used in which this precharge signal is used as a read reference potential.

[Application field]

The present invention can be widely applied to the dynamic RAM described above.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a dynamic RAM according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of a unit circuit constituting a column decoder circuit, and FIG. FIG. 3 is a timing diagram for explaining a clearing operation. MC...Memory cell, DC...Dummy cell, CW...Column switch, SA...Sense amplifier, AR...Active restore circuit, R-DCR...Row decoder, R-
ADB...Row address buffer, C-DCR...Column decoder, C-ADB...Column address buffer,
DOB: Data output cover, DIB: Data output cover, TC: Timing control circuit, UADB...
Unit circuit (column decoder)

Claims (1)

[Claims] 1. According to a control signal supplied from an external terminal or a combination of a plurality of control signals, a plurality of data lines are simultaneously selected, and a write signal is transmitted to the plurality of simultaneously selected data lines. A dynamic RAM that is characterized by an added clear function that puts the sense amplifier into operation after the data has been cleared. 2. The function of simultaneously selecting the plurality of data lines is to convert one of the internal complementary address signals formed according to the address signal supplied from the external terminal to the external address signal in the above operation mode. Dynamic RAM according to claim 1, characterized in that the dynamic RAM is realized by switching the decode output to a level that makes the selected level irrespective of the
. 3. The dynamic RAM according to claim 1 or 2, wherein the clearing function is performed by setting a write enable signal to a low level prior to a row address strobe signal.