JPS63140498A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To speedily write and read data to and from each memory cell and to shorten a testing time by simultaneously operating all plural blocks in each active cycle in a test mode. CONSTITUTION:A decoder circuit 10 constituted of 1st and 2nd circuits is provided. A driving signal outputted from a 1st decoder circuit is given to the sense amplifier of a memory cell array block corresponding to a row address RA8=1, while a driving signal obtained from a 2nd decoder circuit is given to the sense amplifier of a memory cell array block corresponding to a row address RA8=0. Thus, the sense amplifiers are activated in the test mode together with the blocks with the row addresses RA8=0 and RA8=1. Accordingly, all bits can be read out and written with a half of the number of cycles in a normal mode, thereby shortening the testing time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly relates to a semiconductor memory device that can simultaneously perform a functional test of a plurality of memory cells during a functional test of a memory cell. .

[Prior Art] In recent years, with the progress of higher integration in highly integrated memory devices such as dynamic MOS-RAMs, lower power consumption has been desired. Dynamic MOS-RAM
In this case, a large proportion of the total current consumption is consumed by bit line charging and discharging current.

Therefore, in each active cycle, only the memory cell array block related to the input address is operated, the others are not operated, and the bit line charge/discharge current is reduced to 1/2, 3/4, etc. (hereinafter referred to as memory cell array division). action) is being performed.

This conventional example is shown in FIGS. 3 and 4.

Figure 3 shows, for example, IM bit dynamic MO8-RA
This shows the case of M, and the entire memory cell array is divided by row address RA8 (8 represents the 8th bit of the address) and column address CA8 as shown.

Therefore, for example, in the case of external row address manual RA8-1, the block (#1.#
1-, #3. #3”) is not required, and the sense amplifier drive signal (φS) is not activated for these.
The bit line is kept in a precharged state. This situation is shown in the timing chart of FIG. In this timing chart, RAS is the row address strobe signal, CAS is the column address strobe signal, Add is the address signal, A8 is the 8th bit address signal, and φS8 is the sense amplifier drive for the RAS-1 block. The 77th block receives the sense amplifier drive signal (sense amplifier drive signal φS) for the RA8■O block.
decoded), BL, BL is the bit line pair BL
, BT represent the potentials, and φpr represents the bit line precharge clock, respectively.

FIG. 4 is a circuit diagram showing in detail a part of the semiconductor memory device shown in FIG. 3. As shown in the figure, this semiconductor memory device includes a plurality of bit line pairs BL, BL.

..., a plurality of word lines WL arranged to intersect with this bit line pair, ..., memory cells MC arranged at the intersection of the bit line and word line, and a plurality of word lines WL arranged for each bit line pair. A sense amplifier SA detects and amplifies a bit line potential in response to a sense amplifier drive signal φS, and receives a column decoder output selected according to a column address, and connects the bit line pair BL, Bτ to the data line pair I10 . The gate transistors GT and GT for connecting to I10 and the bit line pair BL for receiving the precharge clock φpr are shorted (1/2) Vc c (Vc c
j? (Z pressure) l: Consists of a precharge transistor PRT for charging.

Incidentally, in conventional semiconductor memory devices, memory cells are generally tested for function in a wafer state before the semiconductor memory device is assembled into a package. This functional test is executed by exchanging signals between a memory test device (not shown) and the semiconductor storage device. For example, first, all memory cells constituting a semiconductor memory device are set to a certain logic value (for example, "0°") by a memory tester.
Write. Next, it is determined whether or not the memory cell is functioning normally by reading the memory cell bit by bit and checking whether it matches a logic value written in advance.

[Problems to be solved by the invention] As mentioned above, in conventional semiconductor memory devices, test data had to be written and read out one bit at a time in a plurality of memory cells during a functional test of the memory cells. Therefore, as the capacity of semiconductor memory devices has increased, there has been a problem that the functional test time per semiconductor memory device has become extremely long.

The present invention has been made to solve the problems of the conventional devices as described above, and it is an object of the present invention to provide a semiconductor memory device that can significantly shorten the functional test time.

[Means for Solving the Problems] In the semiconductor memory device according to the present invention, in the normal mode, some of the memory blocks are selectively divided and operated, and in the test mode, All of the plurality of memory blocks mentioned above are operated simultaneously.

[Operation] In the present invention, all memory blocks are operated simultaneously in the test mode, so that writing and reading data to and from each memory cell can be performed quickly, thereby shortening test time.

[Example] In this example, the basic configuration of the semiconductor memory device is the same as that shown in FIGS. 3 and 4. The feature of this embodiment is that the decoder circuit 10 shown in FIG. 1 is newly added to the conventional circuit shown in FIGS. 3 and 4. This decoder circuit 10 uses a sense amplifier drive signal φ
Decode S and create a new sense amplifier drive signal φs8T
a first decoder circuit that outputs a sense amplifier drive signal φS, and a first decoder circuit that decodes the sense amplifier drive signal φS to generate a new sense amplifier drive signal φs.
and a second decoder circuit that outputs 8T.

The first decoder circuit has a row address RA8 and a test mode activation signal TE (“L” in normal mode;
In the test mode, an OR gate 1 receives "H") as input, a NAND gate 2 receives the output of this OR gate 1 and the sense amplifier drive signal φS as input, and an inverter 3 that inverts the output of this NAND gate 2. It consists of: On the other hand, the second decoder circuit is
an OR gate 4 receiving as input an inverted signal RA8 of the row address RA8 and a test mode activation signal TE;
The output of this OR gate 4 and the sense amplifier drive signal φ
NAND gate 5 which receives S as an input and this NAND gate 5
An inverter 6 inverts the output of the D gate 5.

A new sense amplifier drive signal φs8T output from the first decoder circuit is a sense amplifier (third
#3 in the diagram. #4. #7. #8 sense amplifier). On the other hand, the new sense amplifier drive signal φs8T obtained from the second decoder circuit is the row address RAS-
The signal is applied to the sense amplifiers of the memory cell array block corresponding to 0 (sense amplifiers #1, #2, #5, and #6 in FIG. 3).

FIG. 2 is a timing chart for explaining one embodiment of the present invention. In addition, in this Figure 2, RAS
, CAS, Add, A8, BL, BL, φp
r indicates the same meaning as the same symbol shown in FIG. 5, respectively. Further, TE indicates a test mode activation signal, and φs8T, +; 6s8T indicates a sense amplifier drive signal obtained from the decoder circuit 10 shown in FIG.

As shown in FIG. 2, in the test mode, row addresses RA8-0. The sense amplifiers of both blocks of RA8-1 are activated. Therefore, in test mode,
All bits can be read and written in 1/2 the number of cycles compared to the normal mode. Therefore, the test time can be reduced to 1/2 of the conventional test time. Note that in the normal mode, the same operation as in the conventional example is performed.

In the above embodiment, a semiconductor memory device that performs 1/2 division operation in the normal mode is shown, but the present invention can also be applied to cases such as 1/4, 3/8 division operation, etc. In addition, the test time is 1/4.3/
This is significantly shortened to 8.

[Effects of the Invention] As described above, according to the present invention, in the normal mode, some of the plurality of memory blocks are selectively divided and operated, but in the test mode, the plurality of memory blocks are selectively divided. By running everything at the same time, testing time can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a decoder circuit for sensor and wave drive signals used in an embodiment of the present invention. . FIG. 2 is a timing chart for explaining the operation of one embodiment of the present invention. FIG. 3 is a schematic diagram showing the overall configuration of a conventional semiconductor memory device that performs a memory cell array division operation. FIG. 4 is a circuit diagram showing in detail a part of the semiconductor memory device shown in FIG. 3. FIG. 5 is a timing chart for explaining the operation of the conventional semiconductor memory device shown in FIGS. 3 and 4. In the figure, BL and BL are bit lines, WL is a word line, MC is a memory cell, SA is a sense amplifier, 1.
4 is an OR gate, 2 and 5 are NAND gates, 3 and 6 are inverters, and 10 is a decoder circuit.

Claims (3)

[Claims] (1) A memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the intersections of these word lines and bit lines, and the memory cell array is divided into a plurality of blocks. In a semiconductor memory device in which some of these blocks selectively operate in each active cycle, the plurality of blocks all operate simultaneously in each active cycle in a test mode. semiconductor storage device. (2) The semiconductor memory device according to claim 1, further comprising simultaneous activation means for simultaneously activating drive signals of sense amplifiers included in each of the blocks in the test mode. (3) The semiconductor memory device according to claim 2, wherein the simultaneous activation means includes means for decoding the sense amplifier drive signal by a logical sum of a block selection signal and a test mode activation signal.