JPH09245486A - Ferroelectric memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a lower power consumption of a shadow RAM or the like by curtailing a required current especially in a recall mode and in a refreshing mode of the shadow RAM or the like. SOLUTION: A pair of memory arrays ARY0 and ARY1 is so arranged to be alternately made active selectively and sequentially and sense amplifiers SA0 and SA1 are so arranged to be selectively made ready with the supply of a power source voltage VCC or a ground voltage VSS to common source wires CSP0 and CSN0 or CSP1 and CSN1 corresponding to the pair of memory arrays ARY0 and ARY1. Short-circuiting switches P1 and N1 are provided respectively between the common source lines CSP0 and CSP1 and CSN0 and CSN1 to be temporarily turned ON until a corresponding sense amplifier SA0 or SA1 is made ready after the operation of selecting the word lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory, and more particularly to a shadow RAM (random access memory) having a recall mode and a refresh mode, and a technology particularly effective for use in reducing the power consumption thereof. .

[0002]

2. Description of the Related Art Ferroelectric capacitors and address selection M
A memory array in which ferroelectric memory cells including OSFETs (metal oxide semiconductor field effect transistors; in this specification, MOSFETs are collectively referred to as insulated gate field effect transistors) are arranged in a lattice pattern. There is a ferroelectric memory as a basic component. Further, as a kind of ferroelectric memory, during normal operation, the plate potential of the ferroelectric capacitor and the precharge potential of the bit line are operated in the volatile mode as an intermediate potential between the power supply voltage VCC and the ground potential VSS. , A so-called shadow RAM that operates in a non-volatile mode with the plate potential of the ferroelectric capacitor as the ground potential VSS,
For example, it is described in JP-A-7-21784.

[0003]

In the shadow RAM described above, retention of stored data in the non-volatile mode is performed by utilizing polarization of the ferroelectric substance between the electrodes of the ferroelectric capacitor of the ferroelectric memory cell, To read the retained data, after precharging the non-inverted and inverted signal lines of the complementary bit lines of the memory array to the power supply voltage VCC or the ground potential VSS in advance, the word line is selected and the address selection MOSFET of the memory cell is turned on. , Non-inversion of complementary bit lines and potential changes of inverted signal lines due to selective charge flow into the ferroelectric capacitor are performed.
Further, retention of stored data in the volatile mode is performed by utilizing charges accumulated in the interelectrode capacitance of the ferroelectric capacitor due to polarization of the ferroelectric, and readout of retained data is performed, for example, on the complementary bit line. After precharging the non-inverted and inverted signal lines to an intermediate potential between the power supply voltage VCC and the ground potential VSS, the word line is selected to turn on the address selection MOSFET of the memory cell, and the charge accumulated in the interelectrode capacitance is This is performed by detecting the non-inversion of the complementary bit line and the potential change of the inverted signal line due to the emission. Therefore, when the shadow RAM shifts from the non-volatile mode to the volatile mode when the power is turned on, the read operation in the word line unit in the non-volatile mode is executed for all the word lines, and the inter-electrode capacitance of each ferroelectric capacitor is rewritten. In addition, a so-called recall mode for accumulating charges according to the held data is required.

In the recall mode of the shadow RAM, the non-inversion of the complementary bit lines and the precharge of the inverted signal lines are performed every time the selected word line is changed, and the power supply voltage V
One of the potentials of the non-inverted signal line and the inverted signal line of the complementary bit line precharged to CC or the ground potential VSS is selectively ground potential according to the data held in the memory cell coupled to the selected word line. VSS or power supply voltage VCC
Changes to In other words, the potential of the non-inverted or inverted signal line of the complementary bit line, one of which has been changed to the ground potential VSS or the power supply voltage VCC, is supplied to the power supply voltage VCC or the ground potential VSS by the next precharge operation. In this case, the charges accumulated in the parasitic capacitance of the non-inversion or inversion signal line are discharged without being used. As a result,
Correspondingly, the required current in the recall mode increases, which hinders the low power consumption of the shadow RAM.

An object of the present invention is to reduce the current required for a shadow RAM or the like, particularly in the recall mode, to reduce the shadow RA.
It is to reduce the power consumption of M and the like.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a recall mode that can be selectively used in the non-volatile mode or the volatile mode and that is performed while precharging the bit line to the first or second power supply voltage at the time of transition from the non-volatile mode to the volatile mode is required. In a shadow RAM or the like, the memory array is divided into a plurality of blocks and activated selectively and alternately, and first and second power supplies are provided to the first and second common source lines corresponding to these memory arrays. A plurality of sense amplifiers that are selectively activated by being supplied with respective voltages are provided, and the first sense amplifiers of these sense amplifiers are provided.
Alternatively, between the second common source lines, after the word line selection operation is completed and until the first and second common source lines of the corresponding sense amplifiers are supplied with the first and second power supply voltages. Each of them is provided with a short-circuit switch that is temporarily turned on. Further, even in the refresh mode of the shadow RAM, these short-circuit switches are temporarily turned on under the same conditions as in the recall mode.

According to the above means, the charge accumulated in the parasitic capacitance of the non-inverted or inverted signal line of the corresponding common source line and the complementary bit line of the memory array by the amplification operation of one sense amplifier is detected by the other sense. It can be utilized as an operating power source for the common source line of the amplifier, and the potential of the non-inverted and inverted signal lines of these common source lines and the complementary bit lines of the corresponding memory array can be raised to the intermediate potential. As a result, it is possible to reduce the required current of the shadow RAM and the like particularly in the recall mode and the refresh mode, and reduce the power consumption of the shadow RAM and the like.

[0009]

FIG. 1 is a block diagram showing an embodiment of a shadow RAM (ferroelectric memory) to which the present invention is applied. Further, FIG. 2 shows a partial circuit diagram of one embodiment of the memory array and its peripheral portion included in the shadow RAM of FIG. Further, FIG. 3 shows an information retention characteristic diagram of one embodiment of the ferroelectric memory cell constituting the memory array of FIG. 2, and FIG.
The conceptual diagram of one embodiment for explaining the transition of the operation mode of the shadow RAM is shown. Based on these figures, first, the outline of the configuration and operation of the shadow RAM of this embodiment, the information retention characteristics of the ferroelectric memory cell, and the operation mode of the shadow RAM will be described. Note that FIG.
Although not particularly limited, each circuit element of 1) and the circuit element forming each block of FIG. 1 are formed on one semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique. Further, in FIG. 2, an MO having an arrow on its channel (back gate) part
The SFET is a P-channel type, and is distinguished from an N-channel MOSFET without an arrow.

In FIG. 1, the shadow RA of this embodiment is shown.
M is two memory arrays ARY0 and ARY1, X address decoders XD0 and XD1 provided corresponding to these memory arrays, sense amplifiers SA0 and SA1, and Y arranged on the left side of the sense amplifier SA0.
An address decoder YD is provided.

The memory arrays ARY0 and ARY1 are so-called 2-cell / 2-transistor type arrays, and as shown in FIG. 2, they are arranged parallel to the vertical direction of the drawing.
+1 word line W00-W0m or W10-W1
m and n + 1 sets of complementary bit lines B00 * to B0n * or B10 * to B1n * arranged in parallel in the horizontal direction.
(Here, for example, the non-inverted bit line B00T and the inverted bit line B00B are collectively denoted by an asterisk such as a complementary bit line B00 *. Also, when it is validated, it is selectively set to a high level. The so-called non-inverted signals and the like are indicated by adding T to the end of their names, and the inverted signals and the like that are selectively brought to the low level when they are enabled are indicated by adding B to the end of their names. The same applies hereinafter) and includes each. At the intersection of these word lines and complementary bit lines, there are (m + 1) × (n) consisting of a ferroelectric capacitor Ct or Cb and an address selection MOSFET Qt or Qb.
+1) pairs of ferroelectric memory cells are arranged in a grid pattern.

One electrode of the ferroelectric capacitors Ct or Cb of the m + 1 pairs of memory cells arranged in the same column of the memory arrays ARY0 and ARY1 corresponds to the information storage node via the address selection MOSFET Qt or Qb. Complementary bit lines B00 * to B0n * or B
Commonly coupled to non-inverted or inverted signal lines of 10 * to B1n *, respectively. In addition, the memory arrays ARY0 and ARY
The gates of the address selection MOSFETs Qt and Qb of the n + 1 pairs of memory cells arranged in the same row of 1 are commonly coupled to the corresponding word lines W00 to W0m or W10 to W1m, respectively. Memory arrays ARY0 and ARY
A predetermined plate voltage VP is commonly supplied to the other electrodes, that is, the plates of the ferroelectric capacitors Ct and Cb of all the memory cells that compose 1. The plate voltage VP is the power supply voltage VCC and the ground potential VS when the power supply voltage is applied and the shadow RAM is in the volatile mode.
When the intermediate potential between S and HVC is cut off, the power supply voltage is cut off, and the shadow RAM is set to the non-volatile mode, the ground potential VSS is applied.
That is, it is set to 0V.

The ferroelectric memory cells forming the memory arrays ARY0 and ARY1 are shown in FIG. 3 in relation to the electric field applied between the electrodes of the ferroelectric capacitors Ct and Cb and the polarization of the ferroelectric substance between the electrodes. It has information holding characteristics as shown in. That is, the initial ferroelectric substance at the point A shifts its state to the point B by applying the electric field + Ep in the positive direction between the electrodes, and the maximum polarization + Pp in the positive direction occurs. This polarization gradually decreases as the absolute value of the electric field decreases, but at the point C where the electric field becomes 0, the polarization + P
r remains. On the other hand, the polarization of the ferroelectric substance is reversed at the point D where the electric field −Ec in the opposite direction is applied between the electrodes, and the electric field −
Maximum polarization in the opposite direction at point E to which Ep is applied −Pp
Is generated. This polarization gradually decreases as the absolute value of the electric field decreases, but the polarization -Pr remains at the point F where the electric field becomes zero. Then, it makes a normal rotation at a point G to which a positive electric field + Ec is applied, and reaches the point B. Although not particularly limited, each ferroelectric memory cell is supposed to hold data of logic “1” when the polarization state of the ferroelectric substance is on the + side, and the polarization state of the ferroelectric substance is −. When it is on the side, the data of logical "0" is held.

In this embodiment, the shadow RAM is
As shown in FIG. 4, when the power supply voltage is applied, as in a normal dynamic RAM, in the volatile mode using the accumulated charge of the interelectrode capacitance of the ferroelectric capacitor Ct or Cb of each memory cell. When it operates and the power supply voltage is cut off, it operates in a non-volatile mode utilizing polarization of the ferroelectric substance between the electrodes. When the power supply voltage is turned on, the access device of the shadow RAM first sets the recall mode control signal RECM to the high level to set the memory array ARY.
0 and ARY1 word lines W00 to W0m and W1
After performing a series of recall modes for 0 to W1m, the recall mode control signal RECM is returned to the low level to set the shadow RAM to the normal volatile mode. In the recall mode, the shadow RAM performs a read operation for shifting from the non-volatile mode to the volatile mode in units of word lines, as will be described later, but these read operations in the recall mode are treated as a substantially non-volatile mode. .

When the power supply voltage of the shadow RAM is turned on, the plate of the ferroelectric capacitor of each ferroelectric memory cell is supplied with the plate voltage VP such as the intermediate potential HVC as described above. The potential serves as a reference potential that determines the interelectrode voltage of the ferroelectric capacitor. Further, when the shadow RAM is in the non-selected state in the volatile mode, the complementary bit lines B00 * to B0n * and the non-inverted and inverted signal lines of B10 * to B1n * of the memory arrays ARY0 and ARY1 are set to the intermediate potential HVC. It is charged, and this state corresponds to the zero electric field state in FIG.

On the other hand, when the shadow RAM is set to the non-volatile mode due to the disconnection of the power supply voltage, no electric field is similarly applied between the electrodes of the ferroelectric capacitors forming each ferroelectric memory, and The polarization state of the ferroelectric substance is selectively changed to point C or point F in FIG. 3 according to the logical value of the held data.
Therefore, this state does not change semipermanently. When the power supply voltage of the shadow RAM is turned on and the read operation is performed in the recall mode, the memory arrays ARY0 and A
RY1 complementary bit lines B00 * to B0n * and B1
As will be described later, 0 * to B1n * are first precharged to the power supply voltage VCC or the ground potential VSS with their non-inverted and inverted signal lines. The precharge level of each complementary bit line is the word line W00 to W0m or W10 to W1m.
When one of the specified memory cells is selectively set to the high level, it is transmitted to the information storage node of the corresponding n + 1 pairs of ferroelectric memory cells, and the polarization state of the ferroelectric capacitors of these memory cells is changed. It is forced to shift to point B or point E in FIG.

The recall mode of the shadow RAM is VCC
A memory array ARY0 and A, which is performed by a precharge method
RY1 complementary bit lines B00 * to B0n * and B1
When both the non-inverted and inverted signal lines of 0 * to B1n * are precharged to the power supply voltage VCC, the non-inverted bit line B00 of the memory cell pair that holds the data of logic "0"
In the memory cell coupled to the side of T to B0nT or B10T to B1nT, since a polarization reversal from point F to point B is involved, a relatively large amount of positive charge transfer is required, and the potentials of the corresponding non-inverted bit lines are compared. Significantly lower. However, the inverted bit lines B00B to B0nB or B10
In the memory cell coupled to the B to B1nB side, since the transition from point C to point B is accompanied by no polarization reversal, the amount of positive charge transfer is small and the potential drop of the corresponding inversion bit line is relatively small.

On the other hand, in the memory cell pair holding the data of logic "1", the memory cell coupled to the side of the inverted bit lines B00B to B0nB or B10B to B1nB,
Since the polarization inversion from the point F to the point B is accompanied, a relatively large amount of positive charge transfer is required, and the potential of the corresponding inversion bit line is relatively greatly decreased. However, in the memory cell coupled to the non-inverted bit lines B00T to B0nT or B10T to B1nT, the point C is not accompanied by the polarization inversion.
Since the transition is from the point B to the point B, the amount of movement of positive charges is small and the potential drop of the corresponding non-inverted bit line is also relatively small.

These potential changes in the complementary bit lines B00 * to B0n * and B10 * to B1n * are respectively amplified by the corresponding unit amplifier circuits of the sense amplifier SA0 or SA1 which will be described later, and have a high level such as the power supply voltage VCC. Alternatively, it becomes a low level binary read signal such as the ground potential VSS and is coupled to the selected word line n.
The interelectrode capacitance of the ferroelectric capacitors of the +1 pair of memory cells is rewritten. As a result, the shadow RAM shifts to the volatile mode, and the reading or writing of data by the access device can be accepted.

Next, the recall mode of the shadow RAM is performed by the VSS precharge method, and the memory array ARY
0 and ARY1 complementary bit lines B00 * to B0n * and B10 * to B1n * are both pre-charged to the ground potential VSS when the non-inverted and inverted signal lines of the memory cell pair holding data of logic "0". Of the memory cells connected to the inverted bit lines B00B to B0nB or B10B to B1nB, a relatively large amount of negative charge needs to be transferred because the polarization inversion from the point C to the point E is involved. The potential rises relatively large. However, in the memory cell coupled to the non-inverted bit line B00T to B0nT or B10T to B1nT side, since the transition from the point F to the point E is not accompanied by polarization inversion, the negative charge transfer amount is small, and the corresponding inversion occurs. The potential rise of the bit line is also small.

On the other hand, in the memory cell pair holding the data of logic "1", the memory cell coupled to the non-inverted bit line B00B to B0nB or B10B to B1nB side is accompanied by the polarization reversal from the point C to the point E. Therefore, a relatively large amount of negative charge movement is required, and the potential of the corresponding non-inverted bit line rises relatively large. However, in the memory cells coupled to the inverted bit lines B00B to B0nB or B10B to B1nB, since the transition from point F to point E is not accompanied by polarization inversion, the amount of negative charge transfer is small and the corresponding non-inversion occurs. The rise in the potential of the bit line is also relatively small.

These potential changes in the complementary bit lines B00 * to B0n * and B10 * to B1n * are respectively amplified by the corresponding unit amplifier circuits of the sense amplifier SA0 or SA1 which will be described later, and have a high level such as the power supply voltage VCC. Alternatively, it becomes a low-level binary read signal such as the ground potential VSS and is coupled to the selected word line n.
The interelectrode capacitance of the ferroelectric capacitors of the +1 pair of memory cells is rewritten. As a result, the shadow RAM shifts to the volatile mode, and the reading or writing of data by the access device can be accepted.

When the shadow RAM is used in the volatile mode, the ferroelectric capacitor Ct or Cb of each memory cell is used.
The charge accumulated in the inter-electrode capacitance of the
It gradually leaks through the PN junction of the source region of the FET Qt or Qb. Therefore, also in the case of the shadow RAM, as in the case of a normal dynamic RAM, the held data is read in word line units at a predetermined cycle tref according to the leak characteristic of the ferroelectric capacitor Ct or Cb and rewritten in the interelectrode capacitance. A refresh operation is required to do so. To deal with this, the shadow R of this embodiment is
The AM is provided with a refresh controller RFC including an address counter, and a so-called CBR.
(CAS Before RAS) A refresh cycle is prepared, and under the control of the refresh controller RFC,
A series of refresh operations relating to the word lines W00 to W0m and W10 to W1m can be autonomously performed. Further, a recall mode control signal RECM is prepared in the shadow RAM, and a CBR refresh cycle is executed with the recall mode control signal kept at a high level, whereby a series of data recall in the recall mode is controlled by the refresh controller RFC. The operation can be performed autonomously.

In this embodiment, when the shadow RAM is set to the recall mode or the refresh mode, the word lines W00 to W of the memory arrays ARY0 and ARY1.
The address signal for designating 0 m and W10 to W1 m is, as will be described later, a refresh controller R.
It is supplied from FC as refresh address signals RX0 to RXi. Further, these refresh address signals RX0 to RXi are sequentially counted up from the initial state of all-bit logic "0", and the least significant bit, that is, the internal address signal X0 is the memory array ARY0 or AR.
It serves to selectively designate Y1. Therefore,
In the recall mode and the refresh mode, the memory arrays ARY0 and ARY1 are sequentially and alternately designated, which is an important condition of the present invention.
The recall mode and refresh mode of the shadow RAM will be described later in detail.

Next, when the read operation is performed in the volatile mode in the shadow RAM, the non-inverted and inverted signal lines of the complementary bit lines B00 * to B0n * and B10 * to B1n * of the memory arrays ARY0 and ARY1 are the same as those described above. Are precharged to the intermediate potential HVC, the precharge potentials of these complementary bit lines are set to the word lines W00 to W00.
When W0m or W10 to W1m is alternatively set to the high level, the charge accumulated in the interelectrode capacitance of the ferroelectric capacitor Ct or Cb of the corresponding memory cell is charged with the parasitic capacitance of each bit line. It is slightly increased or decreased by being shared. The potential difference between the non-inverted and inverted signal lines is due to the sense amplifier SA0 or SA.
1 is amplified by the corresponding unit amplifier circuit of 1 to 2
It becomes a value read signal and is output from the complementary common data line CD0 * or CD1 * to the outside through the data input / output circuit IO and the data output terminal Dout.

That is, when the normal read operation in the volatile mode is performed in the shadow RAM of this embodiment, the polarization state of the ferroelectric capacitor Ct or Cb of the selected memory cell is determined by the complementary bit lines B00 * to B0n * and B1.
Between the point C or point F of FIG. 2 in which the non-inverted and inverted signal lines of 0 * to B1n * are in the precharged state, the point B corresponding to the high level after amplification or the point E corresponding to the low level after amplification. It only reciprocates, and the polarization inversion accompanying the read operation does not occur. Therefore, it is possible to reduce the number of times of rewriting of the ferroelectric memory cell per time, and thereby to prolong the service life of the ferroelectric memory.

On the other hand, when the data having the same logical value as the data held in the volatile mode in the shadow RAM is written, that is, the non-inverted write operation is performed, the polarization state of the ferroelectric capacitor Ct or Cb of the selected memory cell is
Similar to the read operation, complementary bit lines B00 * to B00
The non-inverted and inverted signal lines of 0n * or B10 * to B1n * only reciprocate between point C or point F and point B or point E in FIG. Absent. However, when writing data having a logical value different from the held data, that is, inversion writing operation, the ferroelectric capacitor C of the selected memory cell is
The polarization state of t or Cb shifts from point C to point E or from point F to point B, respectively, and is accompanied by polarization reversal.

In FIG. 2, the sense amplifier SA0 includes complementary bit lines B00 * to B0n * of the memory array ARY0.
, N + 1 unit circuits are provided corresponding to each of the unit circuits, and each of these unit circuits is a P-channel MOSFET.
P2 and N channel MOSFET N2 and P channel MOSFET P3 and N channel MOSFET
It includes a unit amplifier circuit in which a pair of CMOS (complementary MOS) inverters made of N3 are cross-coupled. P-channel MOSFET P2 forming these unit amplifier circuits
The sources of P and P3 are commonly coupled to the common source line CSP0 (first common source line), and the N-channel MOS
The sources of the FETs N2 and N3 are the common source line CSN.
0 (second common source line). Also,
The commonly coupled drains of the MOSFETs P2 and N2, that is, the commonly coupled gates of the MOSFETs P3 and N3 serve as the non-inverting input / output nodes of the respective unit circuits, and the corresponding non-inverting bit line B00 of the memory array ARY0.
T-B0nT and the common-coupled gates of MOSFETs P2 and N2, ie MOSFETs P3 and N3.
Of the respective unit circuits serve as inverting input / output nodes of the respective unit circuits and correspond to the corresponding inverting bit line B00B.
~ B0nB.

Common source line CS of sense amplifier SA0
P0 is coupled to the power supply voltage VCC (first power supply voltage) via a P-channel drive MOSFET P4, and the common source line CSN0 is an N-channel drive MOSF.
It is coupled to the ground potential VSS (second power supply voltage) via ETN4. The gate of the drive MOSFET N4 is supplied with the non-inverted internal control signal PA0T to drive the drive MOSFET N4.
The inverted signal, that is, the inverted internal control signal PA0B is supplied to the gate of P4.

Each unit circuit of the sense amplifier SA0 is further provided with a non-inverting input / output node, that is, a memory array ARY.
A pair of N-channel type provided between the non-inverted bit lines B00T to B0nT of 0 and the non-inverted common data line CD0T or the inversion input / output node thereof, that is, between the inverted bit lines B00B to B0nB and the inversion common data line CD0B. Switch MOSFETs N8 and N9, and three N-channel type precharge MOSFETs NA to NC
And a bit line precharge circuit which are connected in series and parallel. Of these, the gates of the switch MOSFETs N8 and N9 are commonly coupled to each other, and the corresponding bit line selection signals YS0 to YS are output from the Y address decoder YD.
Sn is supplied respectively. Also, precharge MOS
The timing generation circuit T is connected to the gates of the FETNA to NC.
The internal control signal PC0 is commonly supplied from G, and a predetermined precharge voltage VC is commonly supplied to the commonly connected sources of the precharge MOSFETs NB and NC.

Similarly, the sense amplifier SA1 includes n + 1 unit circuits provided corresponding to the complementary bit lines B10 * to B1n * of the memory array ARY1, and each of these unit circuits includes P channel MOSFETs P5 and N. It includes a unit amplifier circuit in which a pair of CMOS inverters composed of the channel MOSFET N5 and the P channel MOSFET P6 and the N channel MOSFET N6 are cross-coupled. The sources of P-channel MOSFETs P5 and P6 forming each unit amplifier circuit are commonly coupled to the common source line CSP1 (first common source line), and the sources of the N-channel MOSFETs N5 and N6 are common source line CSN1 (second common source line). Common source line)
Is commonly connected to Also, the commonly coupled drains of MOSFETs P5 and N5, that is, MOSFETs P6 and N5.
The commonly coupled gates of 6 serve as the non-inverting input / output nodes of each unit circuit and are coupled to the corresponding non-inverting bit lines B10T to B1nT of the memory array ARY1.
The commonly coupled gates of the OSFETs P5 and N5, that is, the commonly coupled drains of the MOSFETs P6 and N6 serve as the inverting input / output nodes of the respective unit circuits, and the corresponding inverting bit line B10B of the memory array ARY1.
It is bound to B1nB.

Common source line CS of sense amplifier SA1
P1 is coupled to the power supply voltage VCC via the P-channel drive MOSFET P7, and is connected to the common source line CSN1.
Is coupled to the ground potential VSS through the N-channel drive MOSFET N7. The gate of the drive MOSFET N7 is supplied with the non-inverted internal control signal PA1T from the timing generation circuit TG, and the gate of the drive MOSFET P7 is the inverted signal thereof, that is, the inverted internal control signal PA1B.
Is supplied.

Each unit circuit of the sense amplifier SA1 further includes its non-inverting input / output node, that is, the memory array ARY.
A pair of N-channel type provided between one non-inverted bit line B10T to B1nT and the non-inverted common data line CD1T or between its inverted input / output node, that is, between the inverted bit lines B10B to B1nB and the inverted common data line CD1B. Switch MOSFETs ND and NE, and three N-channel type precharge MOSFETs NF to NH
And a bit line precharge circuit which are connected in series and parallel. Of these, the gates of the switch MOSFETs ND and NE are commonly connected to each other, and the corresponding bit line selection signals YS0 to YS are output from the Y address decoder YD.
Sn is supplied respectively. Also, precharge MOS
The timing generation circuit T is connected to the gates of the FETs NF to NH.
The internal control signal PC1 is commonly supplied from G, and the precharge voltage VC is commonly supplied to the commonly connected sources of the precharge MOSFETs NG and NH.

When the shadow RAM is brought into the normal non-selected state in the volatile mode, the internal control signals PC0 and PC
Both 1s are set to a high level such as the power supply voltage VCC, and when the shadow RAM is selected, one of them is selectively set to a low level such as the ground potential VSS at a predetermined timing.

On the other hand, when the shadow RAM is set to the recall mode in the non-volatile mode or the refresh mode in the volatile mode, the memory arrays ARY0 and AR
Y1 word lines W00-W0m and W10-W1m
Are the refresh address signals RX0 to RX0 as described above.
Memory arrays ARY0 and AR specified by RXi
Y1, that is, the sense amplifiers SA0 and SA1 are sequentially activated alternately. In the non-selected state immediately before the recall operation or the refresh operation for the first word line, that is, the word line W00 of the memory array ARY0 is started, the internal control signals PC0 and PC1 are set to the shadow RAM in the recall mode or the refresh mode. High voltage V selectively according to the precharge method
It is set to the high level of CH or the power supply voltage VCC. Then, when the shadow RAM is brought into a selected state to activate the memory array ARY0, first the internal control signal PC0
Is at a low level, the internal control signal PC0 is
Even after the shadow RAM is deselected, it remains at the low level, and the shadow RAM is next
1 is selected to be in an active state, a common source line short circuit CSSC described later connects between common source lines CSP0 and CSP1 and CSN0 and CSN1.
It is set to the high level when the short-circuit operation between them is completed.

Similarly, the internal control signal PC1 is set to the low level in response to the shadow RAM being selected to activate the memory array ARY1, but even after the shadow RAM is deselected. When the shadow RAM is left at the low level and is next selected to activate the memory array ARY0, the common source lines CSP0 and C by the common source line short circuit CSSC are selected.
It is set to the high level when the short-circuit operation between SP1 and between CSN0 and CSN1 is completed.

The precharge voltage VC is the shadow RAM
Is set to the intermediate potential HVC when the volatile mode is set, and VC is set when the shadow RAM is set to the recall mode.
When the C precharge method is adopted, it is set to the power supply voltage VCC, and when the VSS precharge method is adopted, it is set to the ground potential VSS.

When the shadow RAM is deselected in the volatile mode, the precharge MOSFETs NA to NC and NF to NH forming the bit line precharge circuit of each unit circuit of the sense amplifiers SA0 and SA1 are supplied with the internal control signal PC0. Alternatively, when the high level of PC1 is received, it is selectively turned on, and the complementary bit lines B00 * to B0n * or B of the memory array ARY0 or ARY1 are selected.
10 * to B1n * non-inverting and inverting signal lines are set to the intermediate potential H.
Precharge to VC. When the shadow RAM is in the non-selected state in the recall mode, it is also turned on in response to the high level of the internal control signal PC0 or PC1 and the complementary bit line B00 * to B0n * or B.
Non-inversion and inversion signal lines of 10 * to B1n * are selectively supplied to the power supply voltage VCC or the ground potential V according to the precharge method.
It is SS.

In the unit amplifier circuit of each unit circuit of the sense amplifiers SA0 and SA1, the non-inverted internal control signal PA0T or PA1T is set to the high level and the inverted internal control signal PA0B is set.
Or, when PA1B is set to low level, drive MOSF
ETN4 and P4 or N7 and P7 are turned on, and common source lines CSP0 and CSN0 or CS
The power supply voltage VCC and the ground potential VSS are respectively supplied via P1 and CSN1 to enable the selective and simultaneous operation. In this operating state, each unit amplifier circuit has a corresponding complementary bit line B00 * to B0n * or B10 * to B1 from n + 1 pairs of memory cells coupled to the selected word line of the memory array ARY0 or ARY1.
Each minute read signal output via n * is amplified to be a high level or low level binary read signal. Switch MOSFETs N8 and N of each unit circuit
9 and ND and NE are selectively turned on in response to the high level of the corresponding bit line selection signals YS0 to YSn, and the corresponding complementary bit lines B00 * to B0n * or B1 of the memory array ARY0 or ARY1.
0 * -B1n * and complementary common data line CD0 * or CD1
* That is, the data input / output circuit IO is selectively connected.

In this embodiment, the sense amplifier SA0
Common source line CSP0 is a short circuit switch of the common source line short circuit CSSC, that is, a P channel MOSFE.
Common source line C of sense amplifier SA1 via TP1
The common source line CSN0 of the sense amplifier SA0 coupled to SP1 is another short circuit switch of the common source line short circuit CSSC, that is, the N-channel MOSFET N.
1 via the common source line CSN of the sense amplifier SA1
Combined with 1. The gate of the switch MOSFET N1 of the common source line short circuit CSSC is supplied with the non-inverted internal control signal SCT from the timing generation circuit TG, and the gate of the switch MOSFET P1 is supplied with its inverted signal, that is, the inverted internal control signal SCB.

The non-inverted internal control signal SCT is the shadow R
When the AM is set to the volatile mode, the ground potential VS is constantly
It is set to a low level like S. Also, shadow RAM
Is set to a normal low level when the recall mode is a nonvolatile mode or the refresh mode is a volatile mode. Until it is turned on, it is temporarily set to a high level like the power supply voltage VCC. not to mention,
The inverted internal control signal SCB is the non-inverted internal control signal SCT.
Are selectively set to high level or low level under complementary conditions.

As a result, the common source line short circuit CS
The switch MOSFETs P1 and N1 of the SC are temporarily set between the end of the word line selecting operation and the operation of the sense amplifier SA0 or SA1 when the shadow RAM is selected in the recall mode or the refresh mode. Is turned on, and the common source lines CSP0 and CSN0 of the memory array ARY0 and the memory array A
The common source lines CSP1 and CSN1 of RY1 are selectively short-circuited.

At this time, the internal control signals PC0 and PC1
As described above, after the corresponding memory array ARY0 or ARY1 is activated to bring it to a low level, the other memory array ARY1 or ARY0 is activated to bring the common source line short circuit CSSC into common source. Between lines CSP0 and CSP1 and CSN0
When the short circuit operation between CSN1 and CSN1 is completed, it is returned to the high level. In other words, between the common source lines CSP0 and CSP1 by the switch MOSFETs P1 and N1 of the common source line short circuit CSSC, and CSN.
0 and CSN1 are short-circuited, the memory array ARY0 or A activated in the immediately previous cycle is activated.
RY1 complementary bit lines B00 * to B0n * or B1
The parasitic capacitance of the non-inverting and inverting signal lines of 0 * to B1n * is 2 amplified by the sense amplifier SA0 or SA1.
The high level or low level of the value read signal is left without being precharged, and the common source line CS
The power supply voltage VCC or the ground potential VSS remains in the parasitic capacitances of P0 and CSN0 or CSP1 and CSN1. These charges indicate that the switch MOSFETs P1 and N1 of the common source line short circuit CSSC are in the ON state. By doing so, the complementary bit line B10 * of the newly activated memory array ARY1 or ARY0
To B1n * or B00 * to B0n * and the common source lines CSP1 and CSN1 or CS
Charge sharing is performed on the parasitic capacitances of P0 and CSN0, and so-called charge redistribution is performed. As a result, shadow RA
It is possible to reduce the required current in the recall mode and the refresh mode of M and reduce the power consumption of the shadow RAM. The specific operations and characteristics of the recall mode and the refresh mode will be described later in detail.

In FIG. 1, word lines W00 to W0m and word lines W of the memory arrays ARY0 and ARY1.
10 to W1m are coupled to the corresponding X address decoder XD0 or XD1 and are selectively set to the selected state. The X address decoders XD0 and XD1 are commonly supplied with the i-bit internal address signals X1 to Xi except the least significant bit from the X address buffer XB, and are supplied with the internal control signals XG0 and XG1 from the timing generation circuit TG, respectively. . The X address buffer XB is supplied with the X address signals AX0 to AXi in a time division manner via the address input terminals A0 to Ai, and the refresh address signal RX is supplied from the refresh controller RFC.
0 to RXi are supplied. The X address buffer XB further includes an internal control signal R from the timing generation circuit TG.
F and XL are supplied, refresh controller RF
An internal control signal RC is supplied to C.

The refresh controller RFC includes an address counter (not shown). When the shadow RAM is set to the refresh mode in the volatile mode or the recall mode in the non-volatile mode, the address counter performs a step operation according to the internal control signal RC supplied from the timing generation circuit TG and outputs the refresh address signals RX0 to RXi. It is formed and supplied to the X address buffer XB. The refresh address signals RX0 to RXi are sequentially counted up in the normal order, with the state of all bit logic "0" as the initial value.

The X address buffer XB is a shadow RA
When M is in the normal volatile mode and the internal control signal RF is at low level, X address signals AX0 to AXi input in a time division manner via address input terminals A0 to Ai.
Is taken in and held according to the internal control signal XL. When the shadow RAM is set to the refresh mode in the volatile mode or the recall mode in the non-volatile mode and the internal control signal RF is set to the high level, the refresh address signals RX0 to RXi supplied from the refresh controller RFC are set in accordance with the internal control signal XL. Capture and hold. Then, these X address signals AX0 to AXi or the refresh address signal R
Internal address signals X0 to Xi are formed based on X0 to RXi. Of these, the least significant bit internal address signal X0 is supplied to the timing generation circuit TG and the data input / output circuit IO, and the other internal address signals X1 to Xi.
Are commonly supplied to the X address decoders XD0 and XD1.

The X address decoders XD0 and XD1 are
Upon receiving a high level of the corresponding internal control signal XG0 or XG1, the internal control signals XG0 to Xi are selectively brought into an operating state, and the internal address signals X1 to Xi are decoded to generate the memory array ARY0.
Alternatively, the corresponding word line W00 to W0m or W10 to W1m of ARY1 is alternatively set to the selection level such as the high voltage VCH. A state in which the word lines W00 to W0m are selectively set to the selective level is referred to as an active state of the memory array ARY0, and a state in which the word lines W10 to W1m are selectively set to the selective level is called the memory array ARY1. Is called the active state. When the shadow RAM is set to the recall mode or the refresh mode, the refresh address signals RX0 to RXi are sequentially counted up in the normal order with the state of all bit logic “0” as the initial value as described above. Arrays ARY0 and ARY1
Are sequentially activated alternately.

The Y address decoder YD has an i + 1 bit internal address signal Y0 from the Y address buffer YB.
To Yi, and an internal control signal YG from the timing generation circuit TG. Also, a Y address buffer Y
B is supplied with Y address signals AY0 to AYi in a time-sharing manner through the address input terminals A0 to Ai, and an internal control signal YL from the timing generation circuit TG.

The Y address buffer YB is a shadow RA.
Address input terminals A0-A when M is selected
Y address signal AY0 supplied in a time-division manner through i
To AYi in accordance with the internal control signal YL and hold the same, and form the internal address signals Y0 to Yi based on these Y address signals to generate a Y address decoder YD
To supply. At this time, the Y address decoder YD is selectively activated by receiving the high level of the internal control signal YG, decodes the internal address signals Y0 to Yi supplied from the Y address buffer YB, and outputs the sense amplifier S.
The bit line selection signals YS0 to YSn for A are alternatively set to the high level.

Complementary common data lines CD0 * and CD1 *
Are coupled to data input / output circuit IO on the other side. The data input / output circuit IO includes a data input buffer, a data output buffer, a write amplifier and a main amplifier, and an internal address signal X of the least significant bit.
And a selection circuit for receiving 0. Of these, the input terminal of the data input buffer is coupled to the data input terminal Din, and the output terminal thereof is coupled to the input terminal of the write amplifier. The input terminal of the data output buffer is coupled to the output terminal of the main amplifier, and the output terminal thereof is coupled to the data output terminal Dout. The output terminal of the write amplifier and the input terminal of the main amplifier are selectively connected to the complementary common data line CD0 * or CD1 * via the selection circuit. The write amplifier is supplied with an internal control signal WC (not shown) from the timing generation circuit TG, and the data output buffer is supplied with the internal control signal OC.

The data input buffer of the data input / output circuit IO receives the write data input from the external access device through the data input terminal Din when the shadow RAM is selected by the write operation in the normal volatile mode. Capture and transfer to light amplifier. At this time,
The write amplifier is selectively activated by receiving the high level of the internal control signal WC, converts the write data transmitted from the data input buffer into a predetermined complementary write signal, and then outputs the complementary common data line CD0 * or CD1. Memory array A from * via sense amplifier SA0 or SA1
Write to one selected ferroelectric memory cell of RY0 or ARY1.

On the other hand, the main amplifier of the data input / output circuit IO has the memory array ARY0 when the shadow RAM is selected by the read operation in the normal volatile mode.
Alternatively, the binary read signal output from the selected one ferroelectric memory cell of ARY1 via the sense amplifier SA0 or SA1 and the complementary common data line CD0 * or CD1 * is further amplified to be stored in the data output buffer. introduce. At this time, the data output buffer is selectively operated in response to the high level of the internal control signal OC, and outputs the read signal transmitted from the main amplifier of the previous stage to the external access device via the data output terminal Dout. To do.

The timing generation circuit TG is provided with a row address strobe signal RASB and a column address strobe signal CAS supplied as an activation control signal from an external device.
B, the write enable signal WEB, the recall mode control signal RECM, and the internal address signal X0 of the least significant bit supplied from the X address buffer XB to determine the operation mode of the shadow RAM, and the various internal control signals described above. Etc. are selectively formed and supplied to each part of the shadow RAM.

FIG. 5 shows a signal waveform diagram of an embodiment in which the recall mode VCC precharge method of the shadow RAM of FIG. 1 is adopted. The specific operation and characteristics of the recall mode of the shadow RAM of this embodiment will be described with reference to FIG. In the following embodiments, the first cycle cy.0 performed by designating the first word line W00 of the memory array ARY0. 0 for the first word line W10 of the memory array ARY1
Cycle cy. 1 is exemplified. In these embodiments, the complementary bit line B00 of the memory array ARY0 is also used.
* And the complementary bit line B10 * of the memory array ARY1 are shown as typical examples.
The pair of memory cells arranged at the intersections of the word line W00 of 0 and the complementary bit line B00 * are supposed to hold the data of logic "1", and the word line W of the memory array ARY1.
A pair of memory cells arranged at the intersection of 10 and the complementary bit line B10 * holds data of logic "0".

In FIG. 5, the row address strobe signal RASB and the column address strobe signal CASB are used.
Are both set to the high level and the shadow RAM is in the non-selected state before the start of the recall mode, the sense amplifier S
Internal control signals PC0 and PC1 for A0 and SA1
Are both set to a high level like the high voltage VCH, and complementary internal control signals PA0 * and PA1 * are both set to an invalid level (here, for example, the non-inverted internal control signal PA0T is set to low level and the inverted internal control signal PA0B is set to high level). The state in which the level is set is referred to as an invalid level of the complementary internal control signal PA0 *, and the opposite state is referred to as an effective level (the same applies hereinafter). In addition, in response to the recall mode control signal RECM (not shown) being set to the high level, the precharge voltage VC is set to the power supply voltage VCC, and the plate voltage VP is set between the power supply voltage VCC and the ground potential VSS from the initial power-on. The potential is HVC. Further, the word lines W00 to W0m and W10 to W1m of the memory arrays ARY0 and ARY1 are all set to the non-selection level, that is, the ground potential VSS, and the common source line short circuit CSSC is provided.
The complementary internal control signal SC * for is set to an invalid level.

As a result, the memory arrays ARY0 and A
Both RY1 are inactivated, and the switch MOSFETs N1 and P1 of the common source line short circuit CSSC receiving the non-inverted internal control signal SCT and the inverted internal control signal SCB are both turned off. In the sense amplifiers SA0 and SA1, the precharge MOSFET of each unit circuit
NA-NC and NF-NH are turned on in response to the high level of the internal control signal PC0 or PC1, and the complementary bit lines B00 * -of the memory arrays ARY0 and ARY1.
The non-inversion and inversion signal lines of B0n * and B10 * to B1n * are both precharge voltage VC, that is, power supply voltage V
Precharged to CC. In addition, the complementary internal control signal P
Drive MOS in response to invalid level of A0 * and PA1 *
Since the FETs P4 and P7 and N4 and N7 are turned off, the common source lines CSP0 and CSN0 and CSP1 and CSN1 are both precharged to the power supply voltage VCC via a common data line precharge circuit (not shown), and the sense amplifier SA0. Each unit amplifier circuit of SA1 and SA1 is in a non-operating state.

When the shadow RAM is in the non-selected state immediately after the power is turned on, that is, before the start of the recall mode, in each memory cell of the memory arrays ARY0 and ARY1, the polarization state of the ferroelectric substance between the electrodes of the ferroelectric capacitors. Is selectively located at the point C or the point F in FIG. 3 according to the logical value of the held data, but most of the charges corresponding to the logical value of the held data are accumulated in the interelectrode capacitance of the ferroelectric capacitor. Absent.

In the shadow RAM, the column address strobe signal CASB is set to the row address strobe signal R while the recall mode control signal RECM is kept at the high level.
The read operation in the recall mode is started by executing the CBR (CAS before RAS) cycle which is set to the low level before the ASB. At this time, the write enable signal WEB (not shown) remains at the high level, and the word line to be read is alternatively designated according to the refresh address signals RX0 to RXi output from the refresh controller RFC of the shadow RAM. It As described above, the cycle cy.
0, the refresh address signals RX0 to RXi specify the word line W00 of the memory array ARY0, and the cycle cy. 1, the word line W10 of the memory array ARY1 is designated. Therefore, shadow RAM
Then, in cycle cy. In response to the fall of the row address strobe signal RASB of 0, the internal control signal PC
0 is at the low level. Also, with a slight delay, the designated word line W00 of the memory array ARY0 becomes high voltage VCH.
And a complementary internal control signal P after a predetermined time.
A0 * is temporarily set to an effective level for a predetermined period. The internal control signal PC0 is the next cycle cy. It remains at the low level even after 1 is started, and the common source line CSP by the common source line short circuit CSSC described later is used.
It is returned to a high level after the short circuit operation between 0 and CSP1 and between CSN0 and CSN1 is completed.

In the sense amplifier SA0, the internal control signal P
Upon receiving the low level of C0, the precharge operation for complementary bit lines B00 * to B0n * of memory array ARY0 is stopped. Further, in response to the selection level of the word line W00, the address selection MOSFETs Qt and Qb of the corresponding n + 1 pairs of ferroelectric memory cells of the memory array ARY0 are turned on, and the intermediate potential HVC is applied to the plate.
An electric field in the positive direction whose absolute value is the potential difference between the power supply voltage VCC and the intermediate potential HVC, that is, HVC, is simultaneously applied between both electrodes of the ferroelectric capacitors of the memory cells receiving the plate voltage VP. In the n + 1 pairs of ferroelectric memory cells coupled to the word line W00, as described above, when it holds data of logic “1”, for example, the memory cells coupled to the non-inverted bit lines B00T to B0nT side. 3 shifts from point C to point B in FIG. 3, and the polarization state of the memory cell coupled to the side of the inverted bit lines B00B to B0nB is inverted from point F to point B. If it holds data of logic "0", the non-inverted bit line B
The polarization state of the memory cells coupled to the 00T to B0nT side is inverted from the point F to the point B, and the inverted bit lines B00B to B00
The polarization state of the memory cell coupled to the 0 nB side shifts from point C to point B as it is.

As a result, for example, in the memory cell pair arranged at the intersection of the word line W00 and the complementary bit line B00 * of the memory array ARY0 and holding the data of logic "1",
In the memory cell coupled to the inversion bit line B00B, the polarization inversion from the point F to the point B is performed, so that a relatively large amount of positive charge transfer is required, and the potential of the inversion bit line B00B relatively decreases. However, in the memory cell coupled to the non-inverted bit line B00T, since the transition from the point C to the point B is not accompanied by the polarization inversion, the positive charges are less transferred, and the potential drop of the non-inverted bit line B00T is relatively small. small. The potential difference between the non-inverted and inverted signal lines of the complementary bit lines B00 * to B0n * depends on the complementary internal control signal PA0 *.
Is the effective level, and the common source lines CSP0 and CS
When the power supply voltage VCC and the ground potential VSS are supplied to N1, they are respectively amplified by the corresponding unit amplifier circuits of the sense amplifier SA0 and become high level or low level binary read signals. These binary read signals are written in the interelectrode capacitance of the ferroelectric capacitors of the n + 1 pairs of memory cells coupled to the selected word line W00, and the data recall for the word line W00 is completed.

The shadow RAM has cycle c when the row address strobe signal RASB and the column address strobe signal CASB are returned to the high level.
y. 0 ends the data recall operation, but in this embodiment, as described above, the cycle cy. Even after the end of 0, the internal control signal PC0 for the sense amplifier SA0 remains at the low level, so the common source line CSP0
And CSN0 and complementary bit lines B00 * to B0n *
In the non-inversion and inversion signal lines, that is, in the parasitic capacitance thereof, a high level such as the power supply voltage VCC or a low level such as the ground potential VSS is left without being precharged. Further, in the shadow RAM, the internal control signal RC (not shown) is set to the high level in response to the high level of the row address strobe signal RASB, and the address counter of the refresh controller RFC is counted up. Therefore, the refresh address signals RX0 to RXi are
It is updated to specify the word line W10 of the memory array ARY1.

Next, the column address strobe signal CA
SB and the row address strobe signal RASB are set to the low level again at a predetermined interval, and the cycle cy. 1
In the shadow RAM, first, the internal control signal PC1 for the sense amplifier SA1 is set to the low level, and the designated word line W10 of the memory array ARY1 is set to the selection level of the high voltage VCH with a slight delay. After the complementary internal control signal SC * is temporarily set to the effective level for a predetermined period after a predetermined time, the complementary internal control signal P *
A0 * is temporarily set to the effective level for a predetermined period, and the internal control signal PC0 for the sense amplifier SA0 is returned to the high level. The internal control signal PC1 has the next cycle c
y. It remains at the low level even after 2 is started, and the common source line CS by the common source line short circuit CSSC
After the short-circuit operation between P0 and CSP1 and between CSN0 and CSN1 is completed, it is returned to the high level.

In the sense amplifier SA1, the internal control signal P
In response to the low level of C1, the precharge operation for complementary bit lines B10 * to B1n * of memory array ARY1 is stopped. Further, in response to the selection level of the word line W10, the address selection MOSFETs Qt and Qb of the corresponding n + 1 pairs of ferroelectric memory cells of the memory array ARY1 are turned on, and between the electrodes of the ferroelectric capacitors of each memory cell. , A positive electric field whose absolute value is HVC is applied all at once.

As a result, in the memory cell pair which is arranged at the intersection of the word line W10 and the complementary bit line B10 * of the memory array ARY1 and holds the data of logic "0", in the memory cell coupled to the non-inverted bit line B10T. Point F
Since the polarization inversion from the point to the point B is performed, a relatively large amount of positive charge needs to be moved, and the potential of the non-inverted bit line B10T decreases relatively greatly. However, the inverted bit line B1
In the memory cell coupled to 0B, since the transition is from point C to point B without polarization reversal, the movement of positive charges is small and the potential drop of the inversion bit line B10B is relatively small.

Such complementary bit lines B10 * to B1n
Regarding the potential difference between the non-inverted and inverted signal lines, the switch MOSFETs P1 and N1 of the common source line short circuit CSSC are first turned on by receiving the effective level of the complementary internal control signal SC *, and the common source line of the sense amplifier SA0. Power supply voltage V left on complementary bit lines B00 * to B0n * of CSP0 and CSN0 and memory array ARY0
When CC and the ground potential VSS are transmitted to the common source lines CSP1 and CSN1, they are respectively amplified by the corresponding unit amplifier circuits of the sense amplifier SA1, and are temporarily at a high level such as the power supply voltage VCC or the intermediate potential HV.
Expanded to a low level like C. Then, it receives the effective level of the complementary internal control signal PA1 * and drives the drive MOSFE.
TP7 and N7 are turned on and the common source line CS
Power supply voltage VCC and ground potential VSS for P1 and CSN1
Is further supplied to a high level such as the power supply voltage VCC or a low level such as the ground potential VSS, and becomes a complete binary read signal. These binary read signals are written in the interelectrode capacitances of the ferroelectric capacitors of the n + 1 pairs of memory cells coupled to the selected word line W10, thereby ending the data recall for the word line W10.

By the way, the common source lines CSP0 and CSN0 of the sense amplifier SA0 and the memory array AR
The capacitance values of the parasitic capacitances coupled to the non-inverting and inverting signal lines of the complementary bit lines B00 * to B0n * of Y0 are the common source lines CSP1 and CSN1 of the sense amplifier SA1 and the complementary bit lines B10 * of the memory array ARY1. ~
The capacitance value of the parasitic capacitance coupled to the non-inverted and inverted signal lines of B1n * is set to be substantially the same value. Therefore, the switch MOSFETP of the common source line short circuit CSSC
1 and N1 are turned on, the sense amplifier SA
0 common source lines CSP0 and CSN0 and high level and low level accumulated in the parasitic capacitances of the non-inverted and inverted signal lines of the complementary bit lines B00 * to B0n * of the memory array ARY0. CSN1 and memory array ARY
It is almost bisected by the charge share between the non-inversion of one complementary bit line B10 * to B1n * and the parasitic capacitance of the inversion signal line. Therefore, for example, the potential of the inverted bit line B10B of the memory array ARY1 having a small potential drop is immediately raised to the power supply voltage VCC, but the potential of the non-inverted bit line B10T having a large potential drop is once lowered to the intermediate potential HVC. After that, the complementary internal control signal PA1 *
Is lowered to the ground potential VSS.

Hereinafter, the word line W of the memory array ARY0
01-W0m and the word lines W11-W1m of the memory array ARY1 repeat the same data recall operation, and the data held in the inter-electrode capacitances of the ferroelectric capacitors of all the memory cells coupled to these word lines correspond to the held data. The written charge is written. As a result, the shadow RAM shifts to the volatile mode and can accept read or write access from the access device.

In this embodiment, word lines W00-W
As described above, the series of data recall operations for 0m and W10 to W1m are performed by sequentially and alternately designating the memory arrays ARY0 and ARY1. Each time, the switch MOSFETP of the common source line short-circuit CSSC
Charge sharing or charge redistribution through 1 and N1 takes place. In other words, in this shadow RAM adopting the VCC precharge method, one of the sense amplifiers SA0 or S0
The common source lines CSP0 and C by the amplification operation of A1.
The ground potential VSS, that is, the negative charge accumulated in the parasitic capacitance of SN0 and complementary bit lines B00 * to B0n * or the parasitic capacitance of common source lines CSP1 and CSN1 and complementary bit lines B10 * to B1n * is abandoned by the precharge operation. The other sense amplifier S
Common source lines CSP1 and CSN1 of A1 or SA0
Alternatively, it can be utilized as an operating power source for CSP0 and CSN0, which can reduce the required current in the recall mode and reduce the power consumption of the shadow RAM.

FIG. 6 shows a signal waveform diagram of an embodiment when the VSS precharge system in the recall mode of the shadow RAM of FIG. 1 is adopted. In this embodiment, complementary bit lines B00 * to B0n * and B10 * are used.
Since it basically follows the embodiment of FIG. 5 except that the precharge potentials of B1n * are set to the ground potential VSS, description will be added only to the different parts.

In FIG. 6, the non-inverted and inverted signal lines of the complementary bit lines B00 * to B0n * of the memory array ARY0 are set to the internal control signal P when the shadow RAM is in the non-selected state.
By setting C0 to a high level like the power supply voltage VCC, it is precharged to the ground potential VSS. This precharge potential is the cycle cy. 0
Is started and the designated word line W00 is brought into a selected state, so that n + 1 coupled to this selected word line W00.
It selectively rises large or small depending on the data held in the paired ferroelectric memory cells. That is, the memory array A
Between both electrodes of the ferroelectric capacitors of the n + 1 pairs of memory cells coupled to the word line W00 of RY0, the word line W
00 is the selection level and its address selection MOSFET
When Qt and Qb are turned on, the ground potential VS
A potential difference between S and the intermediate potential HVC, that is, an electric field in the opposite direction whose absolute value is HVC is applied all at once. In these memory cells, for example, when data of logic "1" is held, the polarization state of the memory cells coupled to the non-inverted bit lines B00T to B0nT is inverted from point C to point E in FIG. The polarization states of the memory cells coupled to the bit lines B00B to B0nB are not reversed and the points F to E are not inverted.
Move to. Further, when the data of logic "0" is held, the polarization state of the memory cell coupled to the inverted bit lines B00B to B0nB is inverted from the point C to the point E, and the non-inverted bit lines B00T to B0nT are turned on. The polarization state of the memory cell coupled to the point shifts from the point F to the point E as it is.

As a result, in the memory cell pair which is arranged at the intersection of the word line W00 and the complementary bit line B00 * of the memory array ARY0 and holds the data of logic "1", in the memory cell coupled to the non-inverted bit line B00T. Point C
Since the polarization inversion from the point to the point E is performed, a relatively large movement of the negative charge is required, and the potential of the non-inversion bit line B00T rises relatively large. However, the inverted bit line B0
In the memory cell coupled to 0B, since the transition is from point F to point E without polarization reversal, the movement of negative charges is small and the potential rise of the inversion bit line B00B is relatively small. Regarding the potential difference between the non-inverted and inverted signal lines of the complementary bit lines B00 * to B0n *, the complementary internal control signal PA0 * is set to the effective level, and the common source lines CSP0 and CSN1 are supplied with the power supply voltage VCC and the ground potential VSS, respectively. As a result, the corresponding unit amplifier circuit of the sense amplifier SA0 respectively amplifies them to obtain a high level or low level binary read signal. Further, these binary read signals are written in the inter-electrode capacitance of the ferroelectric capacitors of the n + 1 pairs of memory cells coupled to the selected word line W00, and in response thereto, the data recall regarding the word line W00 ends. Common source line CSP0 and CSN
0 and the non-inverted and inverted signal lines of the complementary bit lines B00 * to B0n *, that is, the high level and the low level accumulated in the parasitic capacitance thereof, are stored in the next cycle cy. It is retained even after 1 is started.

On the other hand, the non-inverted and inverted signal lines of the complementary bit lines B10 * to B1n * of the memory array ARY1 are precharged to the ground potential VSS when the internal control signal PC1 is set to the high level. This precharge potential is equal to the cycle cy. When 1 is started and the word line W10 is selected, the voltage rises selectively large or small depending on the data held in the n + 1 pairs of ferroelectric memory cells coupled to the selected word line W10. Further, the potential difference between the non-inverted and inverted signal lines of the complementary bit lines B10 * to B1n * first receives the effective level of the complementary internal control signal SC * to turn on the switch MOSFETs P1 and N1 of the common source line short circuit CSSC. Common source lines CSP0 and CSN0 of the sense amplifier SA0 and complementary bit lines B00 * to B of the memory array ARY0.
The power supply voltage VCC and the ground potential VSS remaining at 0n * are transmitted to the common source lines CSP1 and CSN1, and are temporarily expanded to a high level such as the intermediate potential HVC or a low level such as the ground potential VSS. Then, receiving the effective level of the complementary internal control signal PA1 *,
High level such as power supply voltage VCC or ground potential VSS
As described above, the binary read signal is expanded to a low level and written into the inter-electrode capacitance of the ferroelectric capacitors of the n + 1 pairs of memory cells coupled to the word line W10.

Hereinafter, the word line W of the memory array ARY0
01-W0m and the word lines W11-W1m of the memory array ARY1 are repeatedly subjected to the same data recall operation, and then a recall mode control signal R (not shown)
The ECM is set to the low level, and the shadow RAM shifts to the volatile mode. In addition, a series of data recall operations are performed by sequentially and alternately designating the memory arrays ARY0 and ARY1, and each time charge sharing, that is, charge redistribution is performed via the switch MOSFETs P1 and N1 of the common source line short circuit CSSC. As a result, even when the VSS precharge method is adopted, the same effect as that of the embodiment of FIG. 5 can be obtained, and the power consumption of the shadow RAM can be reduced.

FIG. 7 shows a signal waveform diagram of an embodiment of the refresh mode of the shadow RAM of FIG.
In this embodiment, the recall mode control signal RECM (not shown) is fixed to the low level and the memory array A
RY0 and ARY1 complementary bit lines B00 * to B0n *
In addition, except that the precharge potential of B10 * to B1n * is set to the intermediate potential HVC, it basically follows the embodiment of FIG.

In FIG. 7, the non-inverted and inverted signal lines of the complementary bit lines B00 * to B0n * of the memory array ARY0 are set to the internal control signal P when the shadow RAM is in the non-selected state.
By setting C0 to a high level like the power supply voltage VCC, it is precharged to the intermediate potential HVC. This precharge potential is the cycle c in the refresh mode.
y. When 0 is started and the designated word line W00 is brought into the selected state, n + 1 coupled to this word line W00
It selectively rises or falls depending on the data held in the pair of ferroelectric memory cells, that is, the direction of the charge accumulated in the inter-electrode capacitance. That is, for example, a complementary bit line B00 * to which a memory cell pair holding data of logic "1" is coupled.
Then, the positive charge is discharged from the information storage node of the memory cell coupled to the non-inverted bit line B00T to raise the potential of the non-inverted bit line B00T, and the memory cell coupled to the inverted bit line B00B Since the negative charges are discharged from the information storage node, the potential of the inverted bit line B00B decreases.

Such complementary bit lines B00 * to B0n
Regarding the potential difference between the non-inverted and inverted signal lines of *, the complementary internal control signal PA0 * is set to the effective level, and the common source line CSP
0 and CSN1 are supplied with the power supply voltage VCC and the ground potential VSS, respectively, and are amplified by the corresponding unit amplifier circuits of the sense amplifier SA0 to become high level or low level binary read signals. These binary read signals are rewritten in the interelectrode capacitance of the ferroelectric capacitors of the n + 1 pairs of memory cells coupled to the selected word line W00, and the refresh operation for the word line W00 ends. In addition, the high level and the low level accumulated in the common source lines CSP0 and CSN0 and the non-inverted and inverted signal lines of the complementary bit lines B00 * to B0n *, that is, the parasitic capacitances thereof are the cycle cy. It is retained even after 1 is started.

Next, the non-inverted and inverted signal lines of the complementary bit lines B10 * to B1n * of the memory array ARY1 receive the high level of the internal control signal PC1 and receive the intermediate potential HVC.
Precharged. This precharge potential is equal to the cycle cy. When 1 is started and the word line W10 is selected, the data held in the n + 1 pairs of ferroelectric memory cells coupled to this word line W10, that is, the direction of the charge accumulated in the inter-electrode capacitance thereof is changed. Selectively increase or decrease. Further, the potential difference between the non-inverted and inverted signal lines of the complementary bit lines B10 * to B1n * is such that the switch MOSFETs P1 and N1 of the common source line short circuit CSSC are turned on in response to the effective level of the complementary internal control signal SC *. And the common source line CS of the sense amplifier SA0
Power supply voltage VCC left on complementary bit lines B00 * to B0n * of P0 and CSN0 and memory array ARY0
And the ground potential VSS is common source lines CSP1 and CS
By being transmitted to N1, for the time being, it rises to the predetermined potential V1 or drops to the predetermined potential V2. Upon receiving the effective level of the complementary internal control signal PA1 *, the complementary internal control signal PA1 * is expanded to a high level such as the power supply voltage VCC or a low level such as the ground potential VSS to form a complete binary read signal, which is coupled to the word line W10. The inter-electrode capacitance of the ferroelectric capacitors of the n + 1 pairs of memory cells is rewritten.

The predetermined potential V1 is the power supply voltage VC.
An intermediate potential between C and the intermediate potential HVC, that is, (VCC-
HVC) / 2, and the predetermined potential V2 is an intermediate potential between the intermediate potential HVC and the ground potential VSS, that is, (HVC-VSS) / 2, that is, HVC / 2. Needless to say.

Hereinafter, the word line W of the memory array ARY0
After the similar refresh operation is repeated for 01 to W0m and the word lines W11 to W1m of the memory array ARY1, the shadow RAM ends the refresh mode. In addition, the series of refresh operations is performed by sequentially designating the memory arrays ARY0 and ARY1 alternately, and each time, charge sharing, that is, charge redistribution through the switch MOSFETs P1 and N1 of the common source line short circuit CSSC is performed. As a result, even in the refresh mode, the same effect as that of the embodiment of FIG. 5 can be obtained, and the power consumption of the shadow RAM can be reduced.

The operational effects obtained from the above embodiments are as follows. That is, (1) a recall mode that is selectively usable in the nonvolatile mode or the volatile mode and is performed while precharging the bit line to the first or second power supply voltage at the time of transition from the nonvolatile mode to the volatile mode. Required shadow R
In an AM or the like, a memory array is divided into a plurality of blocks and selectively and sequentially alternately activated, and the first and second power source voltages are applied to the first and second common source lines corresponding to these memory arrays. A plurality of sense amplifiers that are selectively operated by being respectively supplied are provided, and after the word line selection operation is completed between the first or second common source lines of these sense amplifiers. By providing short-circuit switches that are temporarily turned on until the first and second common source lines of the corresponding sense amplifier are supplied to the first and second common source lines, respectively, The charge accumulated in the parasitic capacitance of the non-inverted or inverted signal line of the corresponding common source line and the complementary bit line of the memory array due to the amplifying operation of the amplifier is transferred to the sense amplifier of the other sense amplifier. Used as operating power for Nsosu line, the effect of the potential of the non-inverted and inverted signal lines of the complementary bit lines of these common source lines and the corresponding memory array can be increased to the intermediate potential can be obtained.

(2) According to the above item (1), shadow RA
The effect that the required current such as M in the recall mode can be reduced is obtained. (3) In the above items (1) and (2), the short-circuit switch is temporarily turned on in the refresh mode of the shadow RAM under the same conditions as in the recall mode, so that the shadow RAM and the like are not turned on. In particular, the effect that the required current in the refresh mode can be reduced is obtained. (4) According to the above items (1) to (3), shadow R
It is possible to obtain the effect that the power consumption of AM and the like can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, memory arrays ARY0 and ARY1
Can be divided into a plurality of memory mats including its direct peripheral circuits. Further, the shadow RAM can include a plurality of pairs of memory arrays that are activated alternately in the recall mode and the refresh mode, and a plurality of memory arrays that are not arranged in pairs are provided and these memory arrays are sequentially arranged. It may be activated. Furthermore, the shadow RAM is, for example, × 4 bits, ×
An arbitrary bit configuration such as 8 bits or x16 bits can be adopted, and the block configuration, names of start control signals and internal control signals, combinations and effective levels, polarity of power supply voltage, and the like can adopt various embodiments.

In FIG. 2, the shadow RAM can have various array configurations such as a so-called 1 cell / 1 transistor type. In addition, the memory arrays ARY0 and AR
Y1 may include a redundant element, and each may have a shared sense form. The common source line short circuit CSSC may be an N-channel MOS, for example, when only the recall mode of the VCC precharge system is targeted.
It can be configured with only the FET N1 or can be configured with only the P-channel MOSFET P1 when only the recall mode of the VSS precharge system is targeted. Each of the switch MOSFETs P1 and N1 may be replaced with a so-called complementary switch in which P-channel and N-channel MOSFETs are connected in parallel. Various embodiments can be adopted for the specific configurations of the memory arrays ARY0 and ARY1, the sense amplifiers SA0 and SA1, the conductivity type of the MOSFET, and the like.

In FIG. 3, the information retention characteristic of the ferroelectric memory cell is a standard example and does not limit the present invention. In FIG. 4, various embodiments can be adopted as the activation conditions and the like for setting the shadow RAM to the recall mode. 5 to 7, the names and absolute time relations of the activation control signals, the internal control signals, and the internal signals, and their effective levels are not limited to those in this embodiment. The short circuit of the common source line by the common source line short circuit CSSC is performed by, for example, the memory array AR.
It can be similarly utilized for a continuous normal read or write mode performed while alternately activating Y0 and ARY1.

In the above description, the case where the invention made by the present inventor is mainly applied to a shadow RAM which is a field of application which is the background of the invention has been described. It can also be applied to a normal ferroelectric memory which does not have it, and a digital integrated circuit device such as a single-chip microcomputer which incorporates these ferroelectric memories. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a ferroelectric memory including a plurality of memory arrays that are activated at least sequentially and alternately, and an apparatus or system including such a ferroelectric memory.

[0086]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a recall mode that can be selectively used in the non-volatile mode or the volatile mode and that is performed while precharging the bit line to the first or second power supply voltage at the time of transition from the non-volatile mode to the volatile mode is required. In a shadow RAM or the like, the memory array is divided into a plurality of blocks and activated selectively and alternately, and first and second power supplies are provided to the first and second common source lines corresponding to these memory arrays. A plurality of sense amplifiers that are selectively activated by being supplied with respective voltages are provided, and the word line selection operation is completed between the first or second common source lines of these sense amplifiers. Is temporarily turned on during the period from the time when the first and second common source lines of the corresponding sense amplifier are supplied with the first and second power supply voltages. That provide a short-circuit switch, respectively, these short-circuit switch, shadow RAM
In the refresh mode of the above, by selectively turning it on under the same conditions as in the case of the recall mode, the non-inversion or inversion of the corresponding common source line and the complementary bit line of the memory array by the amplification operation of one sense amplifier. The charge accumulated in the parasitic capacitance of the signal line is used as the operating power supply for the common source line of the other sense amplifier, and the potentials of these common source lines and the non-inverted and inverted signal lines of the complementary bit lines of the corresponding memory array are used. Can be raised to an intermediate potential. As a result, Shadow R
It is possible to reduce the required current especially in the recall mode and the refresh mode of AM and the like, and reduce the power consumption of the shadow RAM and the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of a shadow RAM to which the present invention is applied.

FIG. 2 is a partial circuit diagram showing one embodiment of a memory array included in the shadow RAM of FIG. 1 and a peripheral portion thereof;

FIG. 3 is an information holding characteristic diagram showing one embodiment of a ferroelectric memory cell constituting the memory array of FIG. 2;

FIG. 4 is a conceptual diagram showing an embodiment for explaining a transition of operation modes of the shadow RAM shown in FIG.

5 is a VC in a recall mode of the shadow RAM shown in FIG.
It is a signal waveform diagram which shows one Example when adopting a C precharge system.

6 is a VS of recall mode of the shadow RAM of FIG.
It is a signal waveform diagram which shows one Example when adopting a S precharge system.

7 is a signal waveform diagram showing an embodiment of a refresh mode of the shadow RAM of FIG.

[Explanation of symbols]

ARY0 to ARY1 ... Memory array, XD0 to XD1
X address decoder, X0 to Xi, X internal address signal, XB, X address buffer, RFC, refresh controller, SA0 to SA1, sense amplifier, CSP0 to CSP1, CSN0 to CSN1, common source line, CSSC ... Common source line short circuit, C
D0 * -CD1 * ... Complementary common data line, YD ... Y address decoder, Y0-Yi ... Y internal address signal,
YB ... Y address buffer, IO ... data input / output circuit, TG ... timing generation circuit. Din ... Data input terminal, Dout ... Data output terminal, RASB ... Row address strobe signal input terminal, CASB ... Column address strobe signal input terminal, WEB ... Write enable signal input terminal, RECM ... Recall mode control signal , A0 to Ai ... Address input terminals. W00-
W0m, W10-W1m ... Word line, B00 * -B0
n *, B10 * to B1n * ... Complementary bit lines, Qt, Q
b ... Address selection MOSFET, Ct, Cb ... Ferroelectric capacitor, VP ... Plate voltage, VC ... Precharge voltage, PC ... Precharge control signal, CSP
0-CSP1, CSN0-CSN1 ... Common source line, YS0-YSn ... Bit line selection signal, P1-P7
... P-channel MOSFET, N1 to NH ... N-channel MOSFET. tref ... Refresh cycle.
cy. 0-cy. 1 ... Access cycle, VCC ...
Power supply voltage, VSS ... Ground potential, HVC ... Intermediate potential,
VCH ... High voltage.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasushi Nagashima 2326 Imai, Ome City, Tokyo, Hitachi Device Development Center (72) Inventor Seiji Narui 2326 Imai, Ome City, Tokyo Hitachi Device Development Center, Ltd. In (72) Inventor Yasunobu Aoki 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitate Cho-LS Engineering Co., Ltd.

Claims (5)

[Claims] 1. A plurality of memory arrays in which ferroelectric memory cells are arranged in a grid pattern and are selectively activated, and corresponding first and second memory arrays are provided corresponding to the memory arrays. Between a plurality of sense amplifiers that are selectively operated by supplying the first and second power supply voltages to the common source line of the plurality of sense amplifiers and the first or second common source line of the plurality of sense amplifiers. 2. A ferroelectric memory, comprising: a short-circuit switch provided in each of the. 2. The short-circuiting switch, in a predetermined operation mode in which the plurality of memory arrays are sequentially activated alternately, corresponds to the first short-circuiting switch after the word line selecting operation for one of the memory arrays is completed. 2. The ferroelectric memory according to claim 1, wherein the ferroelectric memory is temporarily turned on until the first and second power source voltages are supplied to the first and second common source lines. 3. The operation mode is a recall mode which is performed by precharging a designated bit line of the memory array to the first or second power supply voltage. 2. Ferroelectric memory. 4. The operation mode is a refresh mode which is performed by precharging a designated bit line of the memory array to an intermediate potential between the first and second power supply voltages. Alternatively, the ferroelectric memory according to claim 2. 5. The ferroelectric memory comprises an address counter that autonomously generates an address for sequentially and alternately designating the plurality of memory arrays in the recall mode and the refresh mode. And claim 1, claim 2, claim 3 or claim 4
Ferroelectric memory.