JP3741231B2 - Nonvolatile storage device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile memory device, for example, a ferroelectric memory and a technology that is particularly effective for its low power consumption.
[0002]
[Prior art]
Ferroelectric memory cells including ferroelectric capacitors and address selection MOSFETs (metal oxide semiconductor field effect transistors. In this specification, MOSFETs are collectively referred to as insulated gate field effect transistors) are arranged in a lattice pattern. A nonvolatile memory device such as a ferroelectric memory using the memory array as a basic component is described in, for example, Japanese Patent Application Laid-Open No. 6-243690. These ferroelectric memories are provided in correspondence with each bit line of the memory array, amplifying a minute read signal output from each selected ferroelectric memory cell to each bit line, and a plurality of them for rewriting. A sense amplifier including a unit amplifier circuit is provided.
[0003]
[Problems to be solved by the invention]
In the conventional ferroelectric memory as described above, so-called destructive reading is performed by reading the retained information of the selected ferroelectric memory cell by polarization inversion, and a normal dynamic RAM (random access memory) or the like is used. Similarly, it is necessary to rewrite read information. In the ferroelectric memory, a selection operation is performed in units of word lines. In the memory array, a predetermined number of ferroelectric memory cells coupled to a designated word line are selected at the same time. For this reason, each unit amplifier circuit of the sense amplifier is selectively and simultaneously activated by supplying the power source voltage VCC and the ground potential VSS to the common source line, and supplies the minute read signal on the corresponding bit line to the power source. A binary read signal having a high level such as the voltage VCC or a low level such as the ground potential VSS is used. These binary read signals are rewritten to a predetermined number of ferroelectric memory cells coupled to the selected word line, and selectively transmitted to the main amplifier in accordance with a Y address signal input from the outside, so that an output buffer To the outside of the ferroelectric memory via the data output terminal.
[0004]
That is, in the conventional ferroelectric memory, the ferroelectric memory cells constituting the memory array are not limited to only selectively outputting a read signal of 1 to several bits specified by the Y address signal. The selected state is simultaneously selected in units of word lines, the stored information is destroyed and rewritten, and a large number of unit amplifier circuits constituting the sense amplifier are simultaneously activated, and each bit line of the memory array The precharge operation is repeated. As a result, the required operating currents of the sense amplifier and the bit line precharge circuit are increased, and the low power consumption of the ferroelectric memory, which is increasing in scale and capacity, is hindered.
[0005]
An object of the present invention is to reduce the power consumption of a nonvolatile memory device such as a ferroelectric memory whose scale and capacity are being increased.
[0006]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0007]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a sense amplifier including a memory array in which ferroelectric memory cells including ferroelectric capacitors and address selection MOSFETs are arranged in a lattice pattern, and a plurality of unit amplifier circuits provided corresponding to each bit line of the memory array Is precharged to the same potential as the plate voltage supplied to the plate of the ferroelectric capacitor of the ferroelectric memory cell. Also, a dummy capacitor precharged to a potential different from the plate voltage is provided, and after the designated word line selection operation is completed, the dummy capacitor and the designated bit line are connected, and the sense amplifier Only the unit amplifier circuit corresponding to the designated bit line is selectively activated. In addition, when a ferroelectric memory or the like has a plurality of memory arrays that are selectively activated, each bit of the memory array that is in an inactive state is precharged to different bit lines of adjacent memory arrays. The capacity of the line is used as the dummy capacity for each bit line of the active memory array.
[0008]
According to the above-described means, the unit amplifier circuit of the sense amplifier can be selectively selected without adding a special capacitor as a dummy capacitor and without destroying information held in the non-selected memory cell coupled to the selected word line. The operating state can be achieved, and the precharge potential of the bit line corresponding to the non-selected memory cell can be held as it is without being discharged. As a result, it is possible to reduce the required operating current of the sense amplifier and the bit line precharge circuit and to reduce the power consumption of a ferroelectric memory or the like that is increasing in scale and capacity.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing one embodiment of a ferroelectric memory (nonvolatile memory device) to which the present invention is applied. First, the outline of the configuration and operation of the ferroelectric memory according to this embodiment will be described with reference to FIG. The circuit elements constituting each block in FIG. 1 are not particularly limited, but are formed on one semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique.
[0010]
Referring to FIG. 1, the ferroelectric memory of this embodiment has a pair of memory arrays ARYL and ARYR, which are arranged so as to occupy most of the semiconductor substrate area. Memory arrays ARYL and ARYR, as will be described later, m + 1 word lines WL0 to WLm or WR0 to WRm arranged in parallel in the vertical direction in the figure, and n + 1 sets arranged in parallel in the horizontal direction in the figure. Complementary bit lines BL0 * to BLn * or BR0 * to BRn * (Here, for example, the non-inverted bit line BL0T and the inverted bit line BL0B are represented by adding * as a complementary bit line BL0 *. A so-called non-inverted bit line or the like that is selectively set to high level when it is enabled is indicated by adding a T to the end of the name, and is selectively set to low level when it is enabled. Inverted bit lines and the like are indicated with B. The same applies hereinafter. At the intersections of these word lines and complementary bit lines, (m + 1) × (n + 1) pairs of ferroelectric memory cells each consisting of a ferroelectric memory cell and an address selection MOSFET are arranged in a lattice pattern.
[0011]
A predetermined plate voltage VPL or VPR is supplied from an internal voltage generating circuit (not shown) to the ferroelectric capacitor plates of all the ferroelectric memory cells constituting the memory arrays ARYL and ARYR. In this embodiment, the plate voltage VPL for the memory array ARYL is set to a quarter potential of the power supply voltage VCC, that is, the absolute potential Vq of VCC / 4, and the plate voltage VPR for the memory array ARYR is equal to the power supply voltage VCC. The potential is 3/4, that is, the absolute potential 3Vq of 3VCC / 4. The reason why the plate voltages VPL and VPR are set to such a potential will become clear later.
[0012]
The word lines WL0 to WLm and WR0 to WRm constituting the memory arrays ARYL and ARYR are coupled to the corresponding X address decoder XDL or XDR below, and are alternatively set to a selection level. The X address decoders XDL and XDR are commonly supplied with i + 1-bit internal address signals X0 to Xi from the X address buffer XB, and are commonly supplied with the internal control signal XG from the clock generation circuit CG. The X address buffer XB is supplied with X address signals AX0 to AXi via X address input terminals AX0 to AXi, and is supplied with an internal control signal AL from the clock generation circuit CG.
[0013]
The X address buffer XB captures and holds the X address signals AX0 to AXi input via the X address input terminals AX0 to AXi according to the internal control signal AL when the ferroelectric memory is selected. Internal address signals X0 to Xi are formed on the basis of the X address signal and supplied to the X address decoder XD. The X address decoder XD is selectively activated by setting the internal control signal XG to a high level and, for example, the internal address signal Xi of the most significant bit to a high level or a low level. The internal address signals X0 to Xi supplied from are decoded, and the corresponding word lines WL0 to WLm or WR0 to WRm of the memory array ARYL or ARYR are alternatively set to a selection level such as the high voltage VCH. The most significant bit internal address signal Xi is also supplied to the Y address decoder YD. The high voltage VCH is set to a positive potential higher than the power supply voltage VCC by at least the threshold voltage of the address selection MOSFET of the ferroelectric memory cell.
[0014]
Next, complementary bit lines BL0 * to BLn * and BR0 * to BRn * constituting memory arrays ARYL and ARYR are coupled to corresponding unit circuits of sense amplifier SA via bit line precharge circuit PL or PR. . Shared sense signals SHL0 to SHLn and SHR0 to SHRn, common source line signals CSP0 to CSPn, CSN0 to CSNn, and bit line selection signals YS0 to YSn (not shown) are supplied from the Y address decoder YD to the sense amplifier SA. The bit line precharge circuits PC and PL are commonly supplied with a precharge control signal PC from the clock generation circuit CG and are supplied with predetermined precharge voltages VCL and VCR from the internal voltage generation circuit, respectively.
[0015]
Bit line precharge circuits PL and PR respectively include n + 1 unit circuits provided corresponding to complementary bit lines BL0 * to BLn * or BR0 * to BRn * of memory array ARYL or ARYR. Each includes three N-channel precharge MOSFETs connected in series-parallel. The three precharge MOSFETs constituting each unit circuit of the bit line precharge circuits PL and PR are selectively turned on in response to the high level of the precharge control signal PC, and the memory arrays ARYL or ARYR are turned on. The non-inverted and inverted signal lines of the corresponding complementary bit lines BL0 * to BLn * or BR0 * to BRn * are precharged to the precharge voltage VCL or VCR, respectively.
[0016]
Sense amplifier SA includes n + 1 unit circuits provided corresponding to complementary bit lines BL0 * to BLn * and BR0 * to BRn * of memory arrays ARYL and ARYR. Each of these unit circuits is a pair of CMOS. (Complementary MOS) A unit amplifier circuit in which inverters are cross-coupled is included. The complementary input / output nodes of the unit amplifier circuit of each unit circuit are coupled to the corresponding complementary bit lines BL0 * to BLn * of the memory array ARYL via a pair of corresponding N-channel shared MOSFETs on the left side thereof, and to the right side thereof. Are coupled to the corresponding complementary bit lines BR0 * to BRn * of the memory array ARYR via another pair of corresponding N-channel shared MOSFETs. Further, it is coupled to the complementary common data line CD * via a corresponding pair of N-channel type switch MOSs.
[0017]
The sources of the two P-channel MOSFETs and N-channel MOSFETs constituting the unit amplifier circuit of each unit circuit of the sense amplifier SA are commonly coupled, and the corresponding common source line signals CSP0 to CSPn or CSN0 to CSNn from the Y address decoder YD. Are supplied respectively. Also, corresponding shared control signals SHL0 to SHLn are respectively supplied to the gates of the shared MOSFET pairs provided on the left side of each unit circuit, and the corresponding shared control signals are supplied to the gates of the shared MOSFET pair provided on the right side. SHR0 to SHRn are respectively supplied. Corresponding bit line selection signals YS0 to YSn are respectively supplied to the gates of the pair of switch MOSFETs of each unit circuit.
[0018]
As a result, the shared MOSFET pair provided on the left side of each unit circuit of the sense amplifier SA is selectively turned on in response to the high level of the corresponding shared control signals SHL0 to SHLn, and the corresponding complementary of the memory array ARYL. The bit line and the complementary input / output node of the corresponding unit amplifier circuit are selectively connected. In addition, the shared MOSFET pair provided on the right side of each unit circuit is selectively turned on in response to the high level of the corresponding shared control signals SHR0 to SHRn, and corresponds to the corresponding complementary bit line of the memory array ARYR. The unit amplifier circuit is selectively connected to the complementary input / output node.
[0019]
On the other hand, in the unit amplifier circuit constituting each unit circuit of the sense amplifier SA, the corresponding common source line signals CSP0 to CSPn or CSN0 to CSNn are effective levels such as the potential 2Vq, the power supply voltage VCC, the ground potential VSS, or the potential 2Vq, respectively. As a result, a minute read signal output via a corresponding complementary bit line is amplified from a ferroelectric memory cell coupled to a selected word line of the memory array ARYL or ARYR. Thus, a binary read signal having a high level such as the potential 2Vq or the power supply voltage VCC or a low level such as the ground potential VSS or the potential 2Vq is used. Further, the pair of switch MOSFETs constituting each unit circuit is selectively turned on in response to the high level of the corresponding bit line selection signals YS0 to YSn, and the complementary input / output node of the corresponding unit circuit, that is, the unit amplifier circuit, The complementary common data line CD * is selectively connected.
[0020]
The specific configurations and operations of the memory arrays ARYL and ARYR and their peripheral parts will be described later in detail.
[0021]
The Y address decoder YD is supplied with j + 1-bit internal address signals Y0 to Yj from the Y address buffer YB, and is supplied with the most significant bit internal address signal Xi from the X address buffer XB. Control signals YG, SH1 to SH2, CS and YS are supplied. The Y address buffer YB is supplied with Y address signals AY0 to AYj via Y address input terminals AY0 to AYj, and is supplied with an internal control signal AL from the clock generation circuit CG. The internal control signals SH1 to SH2 are selectively set to a high level such as the power supply voltage VCC at a predetermined timing at which the shared control signals SHL0 to SHLn or SHR0 to SHRn should be alternatively set to a high level. Further, the internal control signal CS is selectively set to a high level at a predetermined timing at which the common source line signals CSP0 to CSPn and CSN0 to CSNn are alternatively set to effective levels, and the internal control signal YS is selected to select a bit line. The signals YS0 to YSn are selectively set to the high level at a predetermined timing at which the signals YS0 to YSn should be alternatively set to the high level.
[0022]
The Y address buffer YB captures and holds Y address signals AY0 to AYj input via the Y address input terminals AY0 to AYj in accordance with the internal control signal AL when the ferroelectric memory is selected. The internal address signals Y0 to Yj are formed based on the Y address signal of and supplied to the Y address decoder YD. The Y address decoder YD is selectively activated in response to the high level of the internal control signal YG, and decodes the internal address signals Y0 to Yi supplied from the Y address buffer YB. Then, it is determined which one of the memory arrays ARYL or ARYR is activated according to the internal address signal Xi, and the shared control signals SHL0 to SHLn and SHR0 to SHRn are selectively set to a high voltage according to the internal control signals SH1 and SH2. The common source line signals CSP0 to CSPn and CSN0 to CSNn and the bit line selection signals YS0 to YSn are alternatively set to a predetermined effective level or a high level of the power supply voltage VCC according to the internal control signals CS and YS. And
[0023]
Complementary common data line CD * is coupled to main amplifier MA, which includes a write amplifier and a read amplifier. Among these, the input terminal of the write amplifier is coupled to the output terminal of the input buffer IB, and the output terminal is coupled to the complementary common data line CD *. The input terminal of the read amplifier is coupled to the complementary common data line CD *, and its output terminal is coupled to the input terminal of the output buffer OB. The input terminal of input buffer IB is coupled to data input terminal Din, and the output terminal of output buffer OB is coupled to data output terminal Dout. An internal control signal WC (not shown) is supplied from the clock generation circuit CG to the write amplifier of the main amplifier MA, and an internal control signal OC is supplied to the output buffer OB.
[0024]
When the ferroelectric memory is selected in the write mode, the input buffer IB takes in write data input via the data input terminal Din and transmits it to the write amplifier of the main amplifier MA. At this time, the write amplifier of the main amplifier MA is selectively activated in response to the high level of the internal control signal WC, and the write data transmitted from the input buffer IB is set to a predetermined complementary write signal, and then complementary common. Data is written from the data line CD * to the selected pair of ferroelectric memory cells in the memory array ARYL or ARYR via the sense amplifier SA.
[0025]
On the other hand, the read amplifier of the main amplifier MA has a sense amplifier SA and complementary common data from the pair of ferroelectric memory cells selected in the memory array ARYL or ARYR when the ferroelectric memory is selected in the read mode. The read signal output via the line CD * is amplified and transmitted to the output buffer OB. At this time, the output buffer OB is selectively activated in response to the high level of the internal control signal OC, and a read signal transmitted from the read amplifier of the main amplifier MA is transmitted from the data output terminal Dout to the outside of the ferroelectric memory. Output to.
[0026]
The clock generation circuit CG is supplied with a chip enable signal CEB, a write enable signal WEB, and an output enable signal OEB as start control signals from external access devices via external terminals CE, WE, and OEB. The clock generation circuit CG selectively forms the various internal control signals and the like based on these activation control signals and supplies them to each part of the ferroelectric memory.
[0027]
FIG. 2 shows a partial circuit diagram of an embodiment of a memory array and its peripheral part included in the ferroelectric memory of FIG. Based on this figure, the specific configuration and operation of the memory arrays ARYL and ARYR and their peripheral parts of the ferroelectric memory of this embodiment will be described. In the following circuit diagrams and the like, MOSFETs with an arrow attached to the channel (back gate) portion are P-channel type, and are distinguished from N-channel MOSFETs without an arrow.
[0028]
In FIG. 2, the memory arrays ARYL and ARYR are so-called two-cell / two-transistor type arrays, and m + 1 word lines WL0 to WLm or WR0 to WRm arranged in parallel in the vertical direction in the figure, in the horizontal direction. Each includes n + 1 sets of complementary bit lines BL0 * to BLn * or BR0 * to BRn * arranged in parallel. At the intersection of these word lines and complementary bit lines, there are (m + 1) × (n + 1) pairs of ferroelectric memory cells each consisting of a ferroelectric capacitor Cst and an address selection MOSFET Qst or a ferroelectric capacitor Csb and an address selection MOSFET Qsb. Arranged in a grid.
[0029]
One electrode of the ferroelectric capacitors Cst and Csb of the m + 1 pairs of memory cells arranged in the same column of the memory arrays ARYL and ARYR is connected to the corresponding complementary bit lines BL0 * to BLn via the corresponding address selection MOSFETs Qst or Qsb. * Or BR0 * to BRn * are commonly coupled to non-inverted or inverted signal lines, respectively. The gates of the address selection MOSFETs Qst and Qsb of n + 1 pairs of memory cells arranged in the same row of the memory arrays ARYL and ARYR are commonly coupled to the corresponding word lines WL0 to WLm or WR0 to WRm, respectively. A predetermined plate voltage VPL or VPR is commonly supplied to the other electrode or plate of the ferroelectric capacitors Cst and Csb of all the memory cells constituting the memory arrays ARYL and ARYR.
[0030]
When word lines WL0 to WLm and WR0 to WRm constituting memory arrays ARYL and ARYR are set to a non-selection level such as ground potential VSS when the ferroelectric memory is set to a non-selection state, In accordance with internal address signals X0 to Xi, a selection level such as high voltage VCH is set alternatively. Further, the non-inverted and inverted signal lines of the complementary bit lines BL0 * to BLn * and BR0 * to BRn * correspond to the bit line precharge circuit PL or PR described later when the ferroelectric memory is in a non-selected state. Is precharged to the precharge voltage VCL or VCR, that is, the potential Vq or 3Vq. Further, the plate voltage VPL supplied to each ferroelectric memory cell in the memory array ARYL is set to the potential Vq, that is, VCC / 4, and the plate voltage VPR supplied to each ferroelectric memory cell in the memory array ARYR is 3Vq. That is, 3 VCC / 4.
[0031]
As a result, the address selection MOSFETs Qst and Qsb constituting the ferroelectric memory cells of the memory arrays ARYL and ARYR are selectively set when the corresponding word lines WL0 to WLm or WR0 to WRm are set to the selection level of the high voltage VCH. And is selectively connected between one electrode of the ferroelectric capacitor Cst or Csb and the non-inverted or inverted signal line of the corresponding complementary bit line BL0 * to BLn * or BR0 * to BRn *. To do. Further, the ferroelectric capacitors Cst and Csb constituting each ferroelectric memory cell are selectively logic “1” in accordance with the polarization state of the ferroelectric as the interelectrode material when no electric field is applied between the electrodes. The data “0” or “0” is held semipermanently, and a predetermined electric field is applied between both electrodes, thereby outputting a minute read signal corresponding to the held data. Information holding characteristics of the ferroelectric memory cells constituting the ferroelectric memory and specific operations in each operation mode of the ferroelectric memory will be described in detail later.
[0032]
Next, bit line precharge circuits PL and PR include n + 1 unit circuits provided corresponding to complementary bit lines BL0 * to BLn * and BR0 * to BRn * of memory arrays ARYL and ARYR, respectively. Each unit circuit includes three N-channel type precharge MOSFETs N9 to NB or NC to NE coupled in series and parallel. A precharge control signal PC is commonly supplied from the clock generation circuit CG to the gates of the precharge MOSFETs N9 to NB and NC to NE, and precharge MOSFETs NA and NB and ND and NE to the commonly coupled sources are precharged. The voltages VCL and VCR are supplied in common. Note that the precharge control signal PC is set to a high level such as the power supply voltage VCC when the ferroelectric memory is in a non-selected state. Low level. The precharge voltage VCL is set to the potential Vq, that is, VCC / 4, and the precharge voltage VCR is set to the potential 3Vq, that is, 3VCC / 4.
[0033]
Thereby, the precharge MOSFETs N9 to NB and NC to NE constituting the unit circuits of the bit line precharge circuits PL and PR are set to the high level of the precharge control signal PC when the ferroelectric memory is in a non-selected state. Are simultaneously turned on, and the non-inverted and inverted signal lines of the complementary bit lines BL0 * to BLn * and BR0 * to BRn * of the memory arrays ARYL and ARYR are precharged to the potential Vq or 3Vq, respectively.
[0034]
On the other hand, the sense amplifier SA includes n + 1 unit circuits provided corresponding to the complementary bit lines BL0 * to BLn * and BR0 * to BRn * of the memory arrays ARYL and ARYR, respectively. It includes a unit amplifier circuit in which a pair of CMOS inverters composed of a P channel MOSFET P1 and an N channel MOSFET N1, and a P channel MOSFET P2 and an N channel MOSFET N2 are cross-coupled.
[0035]
The sources of the P-channel MOSFETs P1 and P2 constituting the unit amplifier circuit of each unit circuit of the sense amplifier SA are commonly coupled, and the corresponding common source line signals CSP0 to CSPn are supplied from the Y address decoder YD, respectively. The sources of the N-channel MOSFETs N1 and N2 are commonly coupled, and corresponding common source lines CSN0 to CSNn are supplied from the Y address decoder YD, respectively. The commonly coupled drains of the MOSFETs P1 and N1, that is, the commonly coupled gates of the MOSFETs P2 and N2, are the non-inverting input / output nodes BS0T to BSnT of the respective unit amplifier circuits, respectively. Are connected to their inverted input / output nodes BS0B to BSnB, respectively.
[0036]
Complementary input / output nodes BS0 * to BSn * of the unit amplifier circuit of each unit circuit of the sense amplifier SA are on the left side thereof corresponding complementary bit lines BL0 * to BL0 * of the memory array ARYL via N-channel shared MOSFETs N5 and N6. It is coupled to BLn * and on the right side thereof is coupled to corresponding complementary bit lines BR0 * to BRn * of memory array ARYR via N-channel shared MOSFETs N7 and N8. The gates of shared MOSFETs N5 and N6 are commonly coupled, and corresponding shared control signals SHL0 to SHLn are supplied from Y address decoder YD, respectively. The gates of shared MOSFETs N7 and N8 are also commonly connected, and corresponding shared control signals SHR0 to SHRn are supplied from Y address decoder YD, respectively.
[0037]
Each unit circuit of the sense amplifier SA further includes a pair of N-channel type switch MOSFETs N3 and N4 provided between the complementary input / output nodes BS0 * to BSn * of the unit amplifier circuit and the complementary common data line CD *. The gates of these switch MOSFETs N3 and N4 are commonly coupled, and corresponding bit line selection signals YS0 to YSn are supplied from the Y address decoder YD.
[0038]
In this embodiment, the shared control signals SHL0 to SHLn and SHR0 to SHRn supplied to the shared MOSFETs N5 and N6 and N7 and N8 of each unit circuit of the sense amplifier SA are used when the ferroelectric memory is in a non-selected state. When all are at a low level such as the ground potential VSS and selected, they are alternatively set at a high level such as the high voltage VCH under predetermined conditions.
[0039]
As a result, the shared MOSFETs N5 and N6 and N7 and N8 of each unit circuit of the sense amplifier SA are in the selected state, and the corresponding shared control signals SHL0 to SHLn or SHR0 to SHRn are set to the high level. Are alternately turned on, and the complementary input / output nodes BS0 * to BSn * of the corresponding unit amplifier circuit of the sense amplifier SA and the corresponding complementary bit lines BL0 * to BLn * or BR0 * to BRn of the memory array ARYL or ARYR. * Selectively connect to the connection. Since the high levels of the shared control signals SHL0 to SHLn and SHR0 to SHRn are set to the high voltage VCH as described above, the non-inverted and inverted signals of the complementary bit lines BL0 * to BLn * and BR0 * to BRn * The high level in the line is not limited by the threshold voltages of shared MOSFETs N5 and N6 and N7 and N8.
[0040]
Next, the common source line signals CSP0 to CSPn and CSN0 to CSNn supplied to the unit amplifier circuit of each unit circuit of the sense amplifier SA are respectively connected to the ground potential VSS or the power source when the ferroelectric memory is not selected. An invalid level such as the voltage VCC is set. When the ferroelectric memory is selected to activate the memory array ARYL, it is alternatively set to an effective level such as the potential 2Vq or the ground potential VSS at a predetermined timing, and the memory array ARYR is When the active state is selected, the power supply voltage VCC or the potential 2Vq is set to an effective level alternatively at a predetermined timing. Needless to say, the potential 2Vq is half of the power supply voltage VCC, that is, VCC / 2.
[0041]
As a result, the unit amplifier circuit of each unit circuit of the sense amplifier SA has the corresponding common source line signals CSP0 to CSPn and CSN0 to CSNn set to effective levels such as the potential 2Vq, the ground potential VSS, the power supply voltage VCC, or the potential 2Vq, respectively. As a result, the operation state is set alternatively, and one ferroelectric memory cell arranged at the intersection of the selected word line of the memory array ARYL or ARYR and the corresponding complementary bit line passes through the complementary bit line. The minute readout signal outputted in this manner is amplified to be a binary readout signal having a high level such as the power supply voltage VCC or the potential 2Vq or a low level such as the ground potential VSS or the potential 2Vq.
[0042]
On the other hand, the bit line selection signals YS0 to YSn supplied to the switch MOSFETs N3 and N4 of each unit circuit of the sense amplifier SA are all set to a low level like the ground potential VSS when the ferroelectric memory is not selected. When the ferroelectric memory is selected, it is alternatively set to a high level like the power supply voltage VCC at a predetermined timing in accordance with the internal address signals Y0 to Yj.
[0043]
As a result, the switch MOSFETs N3 and N4 of each unit circuit of the sense amplifier SA are selectively turned on in response to the high level of the corresponding bit line selection signals YS0 to YSn, and the complementary input / output nodes of the corresponding unit amplifier circuit. A connection state is selectively established between BS0 * to BSn * and complementary common data line CD *.
[0044]
FIG. 3 shows an information retention characteristic diagram of one embodiment of the ferroelectric memory cells constituting the memory arrays ARYL and ARYR of FIG. Based on the figure, the information retention characteristics and operation outline of the ferroelectric memory cells constituting the memory arrays ARYL and ARYR of the ferroelectric memory will be described.
[0045]
In FIG. 3, the ferroelectric memory cells constituting the memory arrays ARYL and ARYR have an electric field applied between the electrodes of the ferroelectric capacitors Cst or Csb and ferroelectrics used as a material between these ferroelectric capacitors. It has a hysteresis information retention characteristic as illustrated in relation to body polarization. That is, the initial ferroelectric in the state of point A shifts its state to point B when a positive electric field + Ep corresponding to the absolute value of the potential Vq, for example, is applied between the two electrodes. It produces maximum polarization + Pp. This polarization gradually decreases as the absolute value of the electric field decreases, but a predetermined remanent polarization remains at point D where the electric field becomes zero. On the other hand, the polarization state of the ferroelectric substance is reversed at the point E where the electric field -Ec in the reverse direction is applied as a boundary. For example, the electric field -Ep in the reverse direction corresponding to the absolute value of the potential Vq is applied. This produces a maximum polarization -Pp in the reverse direction. This polarization gradually decreases as the absolute value of the electric field becomes smaller, but also remains at point I where the electric field becomes zero. Then, forward rotation is performed at the point H to which the electric field + Ec in the positive direction is applied, and the point B is returned.
[0046]
In this embodiment, the ferroelectric memory cells coupled to the non-inverted signal line side of the complementary bit lines BL0 * to BLn * and BR0 * to BRn * of the memory arrays ARYL and ARYR are not particularly limited. When the body polarization state is on the + side in FIG. 3, data of logic “1” is held, and when it is on the − side, data of logic “0” is held. In addition, the ferroelectric memory cell coupled to the inverted signal line side of the complementary bit lines BL0 * to BLn * and BR0 * to BRn * has a logic "when the polarization state of the ferroelectric is on the-side in FIG. It is assumed that 1 "data is held, and when it is on the + side, logic" 0 "data is held. Each operating point indicating the transition of the polarization state of the ferroelectric in the ferroelectric memory cell will be re-cited in the following description of the specific operation of the ferroelectric memory.
[0047]
FIG. 4 shows a signal waveform diagram of one embodiment of a read operation for activating the memory array ARYL of the ferroelectric memory of FIG. 1, and FIG. 5 is a conceptual diagram for explaining the operation principle. It is shown. FIG. 6 shows a signal waveform diagram of one embodiment of a read operation for activating the memory array ARYR of the ferroelectric memory of FIG. 1, and FIG. 7 is a diagram for explaining the operation principle. A conceptual diagram is shown. Based on these drawings, the specific operation and characteristics of the ferroelectric memory of this embodiment in the read mode will be described. In the following signal waveform diagrams and conceptual diagrams, logic “1” is arranged at the intersection of the word line WL0 and the complementary bit line BL0 * of the memory array ARYL or the intersection of the word line WR0 and the complementary bit line BR0 * of the memory array ARYR. A case where a ferroelectric memory cell that holds the data is designated will be illustrated, and a specific description of the read operation will be made by taking this as an example. In these explanations, the explanation is first made on the memory array ARYL, and only a different part of the memory array ARYR is explained.
[0048]
First, in FIG. 4, when the chip enable signal CEB is set to a high level such as the power supply voltage VCC and the ferroelectric memory is not selected, the precharge control signal PC for the bit line precharge circuits PL and PR is The power supply voltage VCC is set to a high level, and the precharge voltages VCL and VCR are constantly set to potentials Vq and 3Vq, respectively. Further, the shared control signals SHL0 to SHLn and SHR0 to SHRn for the sense amplifier SA are all set to a low level like the ground potential VSS, and the common source lines CSP0 to CSPn and CSN0 to CSNn are set to the ground potential VSS or the power supply voltage VCC, respectively. Such an invalid level. Further, the word lines WL0 to WLm and WR0 to WRm of the memory arrays ARYL and ARYR are all set to a non-selection level such as the ground potential VSS, and the plate voltages VPL and VPR for the memory arrays ARYL and ARYR are constantly at potentials, respectively. Vq and 3Vq.
[0049]
As a result, in the memory arrays ARYL and ARYR, the address selection MOSFETs Qst and Qsb of all the ferroelectric memory cells are turned off in response to the unselected levels of the word lines WL0 to WLm and WR0 to WRm, and the ferroelectric capacitors No electric field is substantially applied between the Cst and Csb electrodes. The non-inverted and inverted signal lines of the complementary bit lines BL0 * to BLn * and BR0 * to BRn * of the memory arrays ARYL and ARYR are precharged by the corresponding precharge MOSFETs of the bit line precharge circuit PL or PR, The precharge voltage VCL or VCR, that is, the potential Vq or the potential 3Vq. At this time, each of the ferroelectric memory cells constituting the memory arrays ARYL and ARYR has a ferroelectric polarization state at either point D or point I in FIG. Holds data of “0”.
[0050]
In the sense amplifier SA, the shared MOSFETs N5 and N6 and N7 and N8 of each unit circuit are turned off in response to the low levels of the corresponding shared control signals SHL0 to SHLn and SHR0 to SHRn, and the unit amplifier circuit of each unit circuit is In response to the invalid levels of the corresponding common source line signals CSP0 to CSPn and CSN0 to CSNn, they are rendered inoperative. Complementary input / output nodes BS0 * to BSn * of each unit amplifier circuit hold a precharge potential according to the immediately preceding cycle, for example, potential Vq. This potential includes a circuit in which sense amplifier SA corresponds to a bit line precharge circuit. In reality, it gradually decreases.
[0051]
By the way, when the ferroelectric memory is brought into a non-selected state, for example, a pair of ferroelectric memory cells arranged at the intersection of the word line WL0 and the complementary bit line BL0 * of the memory array ARYL and holding data of logic “1”. Among them, the plate of the ferroelectric capacitor Cst on the non-inverted bit line side is supplied with a plate voltage VPL having a potential Vq as shown on the left side of FIG. Equivalently, a charge + Qr corresponding to the remanent polarization at point D in FIG. 3 is accumulated.
[0052]
At this time, the address selection MOSFET Qst, that is, the switch Swt is in the off state as described above, and the ferroelectric capacitor Cst and the bit line capacitance Cdt of the corresponding non-inverted bit line BL0T are disconnected. In addition, the shared MOSFETs N5 to N8 of the sense amplifier SA, that is, the switch Sst are also in the OFF state, and the dummy capacitance Cyt including the parasitic capacitance of the non-inverting input / output node BS0T of the sense amplifier SA and the non-inverting bit line BR0T of the memory array ARYR Isolated from inverted bit line BL0T. The bit line capacitance Cdt of the non-inverted bit line BL0T of the memory array ARYL is precharged to the same potential Vq as the precharge voltage VCL, that is, the plate voltage VPL, by the corresponding unit circuit of the bit line precharge circuit PL, and the dummy capacitance Cyt The bit line capacitance of the non-inverted bit line BR0T is precharged to the precharge voltage VCR, that is, the potential 3Vq by the corresponding unit circuit of the bit line precharge circuit PR.
[0053]
On the other hand, of the pair of ferroelectric memory cells holding the data of logic “1”, the plate of the ferroelectric capacitor Csb on the inverted bit line side is as shown on the right side of FIG. The plate voltage VPL having the potential Vq is supplied, and the information storage capacitor Csb is equivalently stored with a charge −Qr corresponding to the residual polarization at the point I in FIG. At this time, the switches Swb and Ssb are still in the off state, and the bit line capacitance Cdb of the non-inverting bit line BL0T of the memory array ARYL and the bit line capacitance of the non-inverting bit line BR0T of the memory array ARYR serving as the dummy capacitor Cyb are respectively Precharged to potential Vq or 3Vq.
[0054]
In the ferroelectric memory, the chip enable signal CEB is set to the low level while the write enable signal WEB (not shown) is set to the high level, so that the read mode is selectively selected and the read operation of the stored data is started. . At this time, the X address input terminals AX0 to AXi are supplied with a combination of X address signals AX0 to AXi designating the word line WL0 of the memory array ARYL in synchronization with the falling edge of the chip enable signal CEB. The Y address signals AY0 to AYj are supplied to the terminals AY0 to AYj in a combination specifying the complementary bit line BL0 *, that is, the bit line selection signal YS0.
[0055]
In the ferroelectric memory, first, in response to the fall of the chip enable signal CEB, the shared control signal SHR0 corresponding to the complementary bit line BR0 * of the memory array ARYR to be inactivated is alternatively set to the high voltage VCH. It is considered as a high level. In addition, the precharge control signal PC for the bit line precharge circuits PL and PR is set to the low level with a predetermined time delay, and the designated word line WL0 of the memory array ARYL to be activated is alternatively set to the high voltage. A selection level such as VCH is used. The shared control signal SHL0 corresponding to the complementary bit line BL0 * of the memory array ARYL is alternatively set to a high level such as the high voltage VCH with a slight delay, and after the predetermined time has elapsed, the shared control signal SHR0 is While returning to the low level such as the ground potential VSS, the common source lines CSP0 and CSN0 corresponding to the complementary bit lines BL0 * of the memory array ARYL are alternatively set to the effective level of the potential Vq or the ground potential VSS.
[0056]
In the ferroelectric memory, in response to the high level of the shared control signal SHR0, the pair of shared MOSFETs N7 and N8 corresponding to the sense amplifier SA are alternately turned on, and the correspondence between the complementary input / output node BS0 * and the memory array ARYR The complementary bit line BR0 * is connected. At this time, since the precharge control signal PC is still kept at the high level as described above, the non-inverted and inverted input / output nodes of the complementary input / output node BS0 * of the sense amplifier SA are the bit line precharge circuit. Precharged to the precharge voltage VCR, that is, the potential 3Vq by the unit circuit corresponding to PR. In sense amplifier SA, shared MOSFETs N5 and N6 corresponding to complementary input / output node BS0 * are kept off, so that the potential of complementary bit line BL0 * of memory array ARYL does not change.
[0057]
After a predetermined time, when the precharge control signal PC is set to the low level, the precharge MOSFETs N9 to NB and NC to NE of the bit line precharge circuits PL and PR are all turned off, and the complementary bit lines BL0 of the memory arrays ARYL and ARYR * -BLn * and BR0 * -BRn * and the precharge operation for complementary input / output nodes BS0 * -BSn * of sense amplifier SA are stopped. Further, when the word line WL0 is alternatively set to the selection level with a slight delay, the address selection MOSFETs Qst and Qsb of the n + 1 pairs of ferroelectric memory cells coupled to the word line WL0 are simultaneously turned on. Since the non-inverted and inverted signal lines of the complementary bit lines BL0 * to BLn * are precharged to the same potential Vq as the plate voltage VPL, between the electrodes of the ferroelectric capacitors Cst and Csb of each ferroelectric memory cell An electric field is not applied to, and its polarization state does not change.
[0058]
When a predetermined time elapses after the word line WL0 is set to the selection level and the shared control signal SHL0 is alternatively set to the high level of the high voltage VCH, the complementary bit line BL0 * of the memory array ARYL and the sense amplifier SA A ferroelectric capacitor of a pair of ferroelectric memory cells coupled to complementary input / output node BS0 * and complementary bit line BR0 * of memory array ARYR and coupled to complementary bit line BL0 * of memory array ARYL Capacitance Cst or Csb of Cst and Csb, bit line capacitance Cdt or Cdb of the non-inverted and inverted signal line of the complementary bit line BL0 *, and non-inverted and inverted input / output node of the complementary input / output node BS0 * of the sense amplifier SA And the parasitic capacitance, i.e., duplication, of the non-inverted and inverted signal lines of the complementary bit line BR0 * of the memory array ARYR. Between the over capacity Cyt or Cyb, charge sharing charge accumulated in the capacitor is performed.
[0059]
For this reason, for example, when the remanent polarization is in the positive direction, the potential of the non-inverted bit line BL0T to which the ferroelectric memory cell holding data of logic “1” is coupled is read relatively high from the precharge potential Vq. The potential of the inverted bit line BL0B to which the ferroelectric memory cell holding the data of logic “1” is coupled is relatively low from the precharge potential Vq because the potential increases to the potential Vt1 and the remanent polarization is in the reverse direction. The reading potential rises to Vb1. At this time, the potentials of the non-inverting input / output node BS0T and the non-inverting bit line BR0T are decreased from the precharge potential 3Vq to the read potential Vt1, and the potentials of the inverting input / output node BS0B and the inverted bit line BR0B are precharge potential 3Vq. To the read potential Vb1.
[0060]
Here, the connection operation in the memory arrays ARYL and ARYR and the sense amplifier SA is assumed to be performed between the complementary bit line BL0 * of the memory array ARYL and the complementary input / output node BS0 * of the sense amplifier SA, that is, the complementary bit line BR0 * of the memory array ARYR. A memory by charge sharing is divided into an array connection in which connection is made between and a word line connection in which connection between these complementary bit lines and complementary input / output nodes and the ferroelectric capacitor Cst or Csb is made. The level change of each part of the arrays ARYL and ARYR and the sense amplifier SA will be described.
[0061]
First, as shown in FIG. 5B, the complementary bit line BL0 * of the memory array ARYL precharged to the potential Vq, the complementary input / output node BS0 * of the sense amplifier SA precharged to the potential 3Vq, and the memory array. In the array connection in which the connection between the complementary bit lines BR0 * of the ARYR is performed, the potential Vo of the complementary bit lines BL0 * and BR0 * and the complementary input / output node BS0 * when the charge sharing is assumed to be completed is complementary. The bit line capacitance values of the non-inverted and inverted signal lines of the bit line BL0 * are Cdt and Cdb, respectively, and the non-inverted and inverted input / output nodes of the complementary input / output node BS0 * and the non-inverted and inverted signals of the complementary bit line BR0 * When the values of the dummy capacitance composed of the parasitic capacitance of the line are respectively Cyt and Cyb,
Vo = (VqCdt + 3VqCyt) / (Cdt + Cyt) (1)
Or
Vo = (VqCdb + 3VqCyb) / (Cdb + Cyb) (2)
It becomes.
[0062]
Further, when the dummy capacitance values Cyt and Cyb are small enough to ignore the parasitic capacitance of the complementary input / output node BS0 * of the sense amplifier SA,
Cyt ≒ Cdt
Cyb≈Cdb
When the parasitic capacitance of the complementary input / output node BS0 * of the sense amplifier SA and the parasitic capacitance of the complementary bit line BR0 * are assumed to be the same,
Cyt ≒ 2Cdt
Cyb ≒ 2Cdb
It becomes. Therefore, when the above equations (1) and (2) are so small that the parasitic capacitance of the complementary input / output node BS0 * of the sense amplifier SA is negligible,
Vo≈2Vq
That is, when it is assumed that the potential of the power supply voltage VCC is ½, and the parasitic capacitance of the complementary input / output node BS0 * and the parasitic capacitance of the complementary bit line BR0 * are the same,
Vo≈2.3Vq
Both values are close to 2Vq.
[0063]
On the other hand, as shown in FIG. 5C, the complementary bit lines BL0 * and BR0 * whose potential has been changed to the potential Vo, and the selected ferroelectric memory cell of the complementary input / output node BS0 * and the memory array ARYL. When the word line is connected to the ferroelectric capacitor Cst or Csb, the charges Qst and Qsb corresponding to the polarization state of the ferroelectric capacitors Cst and Csb when the charge sharing is assumed to be The capacitance values of the ferroelectric capacitors Cst and Csb are Cst and Csb, respectively, the charge amounts corresponding to the remanent polarization at points D and I in FIG. 3 are + Qr and −Qr, respectively, and the complementary bit line BL0 * after charge sharing And the non-inverted and inverted signal lines of BR0 * and the non-inverted and inverted input / output nodes of complementary input / output node BS0 *. When the respective Vt and Vb,
Qst + Vt (Cdt + Cyt) = + Qr + Vo (Cdt + Cyt)
Qsb + Vb (Cdb + Cyb) = − Qr + Vo (Cdb + Cyb)
That means
Qst = + Qr− (Vt−Vo) (Cdt + Cyt) (3)
Qsb = −Qr− (Vb−Vo) (Cdb + Cyb) (4)
There is a relationship.
[0064]
As is apparent from FIG. 3, the above equation (3) indicates that the charge Qstp at the intersection L with the charge axis at which the electric field is zero, that is, the potential Vt is Vq,
Qstp = + Qr- (Vq-Vo) (Cdt + Cyt) (5)
And the potential Vp corresponding to the intersection N with the electric field axis at which Qst is zero,
Vp = Vo + Qr / (Cdt + Cyt)
And
Vt = Vo
When
Qst = + Qr
The above equation (4) is expressed by a straight line 2 that is parallel to the straight line 1 and whose absolute value is smaller by 2Qr. Since the above equation (5) is Vo> Vq,
Qstp = + Qr + (Vo−Vq) (Cdt + Cyt)
It goes without saying that.
[0065]
From the above, the ferroelectric memory cell which is arranged at the intersection of the word line WL0 and the non-inverted bit line BL0T and whose polarization state at the time of non-selection is at the point D in FIG. The ferroelectric memory cell, whose polarization state is moved to the intersection C between the straight line 1 and the hysteresis characteristic curve and arranged at the intersection of the word line WL0 and the inverted bit line BL0B and whose polarization state at the time of non-selection is at the point I, The polarization state is shifted to the intersection K between the straight line 2 and the hysteresis characteristic curve. As a result, the potential of the non-inverted bit line BL0T changes to the potential Vt1 corresponding to the electric field at the point C, and the potential of the inverted bit line BL0B changes to the potential Vb1 corresponding to the electric field at the point K. A potential difference serving as a so-called minute read signal is obtained in the inversion and inversion bit lines. In this read operation, the polarization state of the ferroelectric memory cell coupled to the non-inverted bit line BL0T is not inverted, but the polarization state of the ferroelectric memory cell coupled to the inverted bit line BL0B is reversed. Inverted in the positive direction.
[0066]
The minute potential difference obtained between the non-inverted bit line BL0T and the inverted bit line BL0B by the read operation using the charge share is that the corresponding common source lines CSP0 and CSN0 are set to the effective level of the potential 2Vq or the ground potential VSS, respectively. Thus, the signal is amplified by the corresponding unit amplifier circuit of the sense amplifier SA, and becomes a binary read signal having a high level such as the potential 2Vq or a low level such as the ground potential VSS. Then, the bit line selection signal YS0 corresponding to the Y address signals AY0 to AYj is set to the high level, so that it is alternatively transmitted to the complementary common data line CD *, and further from the read amplifier of the main amplifier MA to the output buffer OB and The data is output to the outside of the ferroelectric memory through the data output terminal Dout.
[0067]
On the other hand, the binary read signals established on the non-inverted and inverted signal lines of the complementary bit line BL0 * are the two electrodes of the ferroelectric capacitors Cst and Csb of the pair of ferroelectric memory cells in the selected state of the memory array ARYL. Also transmitted in between. Among these, in the ferroelectric memory cell coupled to the non-inverted bit line BL0T and having a polarization state at a point C in FIG. 3, the polarization state is obtained by setting the non-inverted bit line BL0T to a high level such as the potential 2Vq. Moves to point B, and rewriting is performed without polarization reversal. In a ferroelectric memory cell coupled to the inverted bit line BL0B and having a polarization state at the point K, the polarization state is shifted to the point G when the inverted bit line BL0B is set to a low level such as the ground potential VSS. Rewriting with polarization inversion is performed. In these ferroelectric memory cells, the read operation is completed, and the non-selected bit line BL0T and the inverted bit line BL0B are precharged again to the precharge potential VCL, that is, the potential Vq, so that the polarization state is changed to the point D or Moving to point I, this polarization state is maintained as nonvolatile information.
[0068]
Meanwhile, while the above read operation is performed on the pair of ferroelectric memory cells arranged at the intersection of the word line WL0 and the complementary bit line BL0 * of the memory array ARYL, the word line WL0 of the memory array ARYL and the other complementary bit lines. In the remaining n pairs of ferroelectric memory cells arranged at the intersections of BL1 * to BLn *, the address selection MOSFET Qs is turned on, but the corresponding shared control signals SHL1 to SHLn are set to the low level and the complementary bit line BL1. Since the potential of the non-inverted and inverted signal lines of * to BLn * is kept at the precharge potential Vq, no electric field is applied between both electrodes of the ferroelectric memory cell, and the ferroelectric polarization state Is retained without being destroyed. When attention is paid to the memory array ARYR, the non-inverted and inverted signal lines of the complementary bit line BR0 * are changed to the potential Vt1 or Vb1, but the other complementary bit lines BR1 * to BRn * are not compatible. Since the shared control signals SHR1 to SHRn to be set to the low level, the potentials of the non-inverted and inverted signal lines are kept at the precharge potential 3Vq.
[0069]
Next, in FIG. 6, when a read operation is performed by designating a pair of memory cells arranged at the intersection of the word line WR0 and the complementary bit line BR0 * of the memory array ARYR, in the ferroelectric memory, first, in the chip In response to the fall of enable signal CEB, shared control signal SHL0 corresponding to complementary bit line BL0 * of memory array ARYL to be inactivated is alternatively set to a high level such as high voltage VCH. In addition, the precharge control signal PC for the bit line precharge circuits PL and PR is set to the low level after a predetermined time delay, and the designated word line WR0 of the memory array ARYR to be activated is alternatively set to the high voltage. A selection level such as VCH is used. The shared control signal SHR0 corresponding to the complementary bit line BR0 * of the memory array ARYR is alternatively set to a high level such as the high voltage VCH with a slight delay, and after a predetermined time has elapsed, the shared control signal SHL0 is The common source lines CSP0 and CSN0 corresponding to the complementary bit lines BR0 * of the memory array ARYR are alternatively set to the effective level of the power supply voltage VCC or the potential 2Vq.
[0070]
In the ferroelectric memory, in response to the high level of the shared control signal SHL0, the pair of shared MOSFETs N5 and N6 corresponding to the sense amplifier SA are alternately turned on, and the correspondence between the complementary input / output node BS0 * and the memory array ARYL The complementary bit line BL0 * is connected. At this time, since the precharge control signal PC is still kept at the high level as described above, the non-inverted and inverted input / output nodes of the complementary input / output node BS0 * of the sense amplifier SA are the bit line precharge circuit. Precharge voltage VCL, that is, potential Vq is precharged by a corresponding unit circuit of PL. In sense amplifier SA, shared MOSFETs N7 and N8 corresponding to complementary input / output node BS0 * are kept off, so that the potential of complementary bit line BR0 * of memory array ARYR does not change.
[0071]
After a predetermined time, when the precharge control signal PC is set to the low level, the precharge MOSFETs N9 to NB and NC to NE of the bit line precharge circuits PL and PR are all turned off, and the complementary bit lines BL0 of the memory arrays ARYL and ARYR * -BLn * and BR0 * -BRn * and the precharge operation for complementary input / output nodes BS0 * -BSn * of sense amplifier SA are stopped. If the word line WR0 is alternatively set to the selection level with a slight delay, the address selection MOSFETs Qst and Qsb of the n + 1 pairs of ferroelectric memory cells coupled to the word line WR0 are turned on at the same time. Since the non-inverted and inverted signal lines of the complementary bit lines BR0 * to BRn * are precharged to the same potential 3Vq as the plate voltage VPL, between the electrodes of the ferroelectric capacitors Cst and Csb of each ferroelectric memory cell An electric field is not applied to, and its polarization state does not change.
[0072]
When a predetermined time elapses after the word line WR0 is set to the selection level and the shared control signal SHR0 is alternatively set to the high level such as the high voltage VCH, the complementary bit line BR0 * of the memory array ARYR and the sense amplifier Information storage of a pair of ferroelectric memory cells coupled to the complementary bit line BR0 * of the memory array ARYR is connected between the complementary input / output node BS0 * of the SA and the complementary bit line BL0 * of the memory array ARYL. The capacitance Cst or Csb and the bit line capacitance Cdt or Cdb of the complementary bit line BR0 * and the parasitic capacitance of the complementary input / output node BS0 * of the sense amplifier SA and the complementary bit line BL0 * of the memory array ARYL, that is, the dummy capacitance Cyt or Cyb. Charge sharing of charge is performed between them.
[0073]
For this reason, for example, when the remanent polarization is in the positive direction, the potential of the non-inverted bit line BR0T to which the ferroelectric memory cell holding data of logic “1” is coupled is read from the precharge potential 3Vq. The potential of the inversion bit line BR0B to which the ferroelectric memory cell holding the data of logic “1” is coupled is lowered from the precharge potential 3Vq because the potential decreases to the potential Vt2 and the remanent polarization is in the reverse direction. The read potential is lowered to Vb2. At this time, the potentials of the non-inverting input / output node BS0T and the non-inverting bit line BL0T rise from the precharge potential Vq to the read potential Vt2, and the potentials of the inverting input / output node BS0B and the inverted bit line BL0B are precharge potential Vq. To the read potential Vb2.
[0074]
As shown in FIG. 7B, the complementary bit line BR0 * of the memory array ARYR precharged to the potential 3Vq, the complementary input / output node BS0 * of the sense amplifier SA precharged to the potential Vq, and the memory array ARYL. When the array is connected to the complementary bit line BL0 *, the potential Vo ′ of the complementary bit lines BL0 * and BR0 * and the complementary input / output node BS0 * when the charge sharing is assumed to be finished is
Vo ′ = (3VqCdt + VqCyt) / (Cdt + Cyt) (6)
Or
Vo ′ = (3VqCdb + VqCyb) / (Cdb + Cyb) (7)
It becomes.
[0075]
Further, the above equations (6) and (7) are obtained when the parasitic capacitance of the complementary input / output node BS0 * of the sense amplifier SA is small enough to be ignored.
Vo '≒ 2Vq
That is, when it is assumed that the potential of the power supply voltage VCC is ½, and the parasitic capacitance of the complementary input / output node BS0 * and the parasitic capacitance of the complementary bit line BR0 * are the same,
Vo '≒ 1.7Vq
The potential Vo when the memory array ARYL in FIGS. 4 and 5 is designated is a symmetric value about a straight line with zero electric field.
[0076]
On the other hand, as shown in FIG. 7C, the complementary bit lines BL0 * and BR0 * whose potential has been changed to the potential Vo ′, and the selected ferroelectric memory of the complementary input / output nodes BS0 * and the memory array ARYR. Charges Qst and Qsb corresponding to the polarization state of the ferroelectric capacitors Cst and Csb when it is assumed that the charge sharing is completed when the word line is connected to the ferroelectric capacitor Cst or Csb of the cell. ,
Qst + Vt (Cdt + Cyt) = + Qr + Vo ′ (Cdt + Cyt)
Qsb + Vb (Cdb + Cyb) = − Qr + Vo ′ (Cdb + Cyb)
That means
Qst = + Qr− (Vt−Vo ′) (Cdt + Cyt) (7)
Qsb = −Qr− (Vb−Vo ′) (Cdb + Cyb) (8)
There is a relationship.
[0077]
As is apparent from FIG. 3, the above equation (7) expresses the charge Qstp ′ at the intersection R with the charge axis where the electric field is zero, that is, the potential Vt is 3 Vq
Qstp ′ = + Qr− (3Vq−Vo ′) (Cdt + Cyt) (9)
And a potential Vp ′ corresponding to the intersection point P with the electric field axis at which the charge Qst is zero,
Vp ′ = Vo ′ + Qr / (Cdt + Cyt)
And
Vt = Vo '
When
Qst = + Qr
The above equation (8) is expressed by a straight line 4 that is parallel to the straight line 3 and whose absolute value is smaller by 2Qr. In addition, since the above equation (9) satisfies 3Vq> Vo ′, the code relationship remains as it is.
[0078]
From the above, a ferroelectric memory cell that is arranged at the intersection of the word line WR0 and the non-inverted bit line BR0T and whose polarization state at the time of non-selection is at the point D in FIG. 3 is subjected to the charge sharing. The ferroelectric memory cell, whose polarization state is shifted to the intersection F between the straight line 3 and the hysteresis characteristic curve and is arranged at the intersection of the word line WR0 and the inverted bit line BR0B and whose polarization state at the time of non-selection is at the point I, The polarization state is shifted to the intersection H between the straight line 4 and the hysteresis characteristic curve. As a result, the potential of the non-inverted bit line BR0T changes to the potential Vt2 corresponding to the electric field at the point F, and the potential of the inverted bit line BR0B changes to the potential Vb2 corresponding to the electric field at the point H. A potential difference serving as a minute read signal is obtained for the inversion and the inversion bit line. In this read operation, the polarization state of the ferroelectric memory cell coupled to the non-inverted bit line BR0T is inverted from the positive direction to the reverse direction, but the ferroelectric memory cell coupled to the inverted bit line BR0B. The polarization state of is not reversed.
[0079]
The minute potential difference obtained between the non-inverted bit line BR0T and the inverted bit line BR0B by the read operation using the charge share is that the corresponding common source lines CSP0 and CSN0 are set to the effective level of the power supply voltage VCC or the potential 2Vq, respectively. Thus, the signal is amplified by the corresponding unit amplifier circuit of the sense amplifier SA, and becomes a binary read signal having a high level such as the power supply voltage VCC or a low level such as the potential 2Vq. Then, the bit line selection signal YS0 corresponding to the Y address signals AY0 to AYj is set to the high level, so that it is alternatively transmitted to the complementary common data line CD *, and further from the read amplifier of the main amplifier MA to the output buffer OB and The data is output to the outside of the ferroelectric memory through the data output terminal Dout.
[0080]
On the other hand, the binary read signal established on the complementary bit line BR0 * is directly transmitted to the ferroelectric capacitors Cst and Csb of the pair of ferroelectric memory cells in the selected state of the memory array ARYR. Among these, in the ferroelectric memory cell that is coupled to the non-inverted bit line BR0T and whose polarization state is at the point F in FIG. 3, the polarization of the non-inverted bit line BR0T is set to a high level such as the power supply voltage VCC. The state moves to point B, and rewriting is performed with polarization inversion. In the ferroelectric memory cell coupled to the inverted bit line BR0B and having the polarization state at the point H, the polarization state is shifted to the point G when the inverted bit line BR0B is set to a low level such as the potential 2Vq. Rewriting without polarization reversal is performed. In these ferroelectric memory cells, the read operation is completed, and the non-selected bit line BR0T and the inverted bit line BR0B are returned to the precharge potential VCR, that is, the potential 3Vq, so that the polarization state is set to point D or point I, respectively. Migrate and keep this.
[0081]
Incidentally, while the above read operation is performed on the pair of ferroelectric memory cells arranged at the intersection of the word line WR0 and the complementary bit line BR0 * of the memory array ARYR, the word line WR0 of the memory array ARYR and the other complementary bit lines. In the remaining n pairs of ferroelectric memory cells arranged at the intersections of BR1 * to BRn *, the address selection MOSFET Qs is turned on, but the corresponding shared control signals SHR1 to SRLn are set to the low level and the complementary bit line BR1 *. Since the potential of the non-inverted and inverted signal lines of .about.BRn * is kept at the precharge potential of 3 Vq, no electric field is applied between both electrodes of the ferroelectric memory cell, and the ferroelectric polarization state is also changed. Retained without being destroyed. Further, when attention is paid to the memory array ARYL, the non-inverted and inverted signal lines of the complementary bit line BL0 * are changed to the potential Vt2 or Vb2, but for the other complementary bit lines BL1 * to BLn *, Since the corresponding shared control signals SHR1 to SHRn are set to the low level, the non-inverted and inverted signal lines are kept at the precharge potential Vq.
[0082]
As described above, in this embodiment, the non-inverted and inverted bit lines of the complementary bit lines BL0 * to BLn * and BR0 * to BRn * of the memory arrays ARYL and ARYR are used as the ferroelectric capacitors of the ferroelectric memory cells. Precharged to the same potential as the plate voltage supplied to the plate. In addition, the bit line capacitance of the complementary bit line of the memory array that is deactivated is used as a dummy capacitance for the bit line of the memory array that is activated, and these dummy capacitors are the memory array that is activated. Is precharged to a potential different from the plate voltage. When the selected word line selection operation is completed, the dummy capacitor and the designated bit line are selectively connected, and the unit corresponding to the designated bit line of the sense amplifier SA. Only the amplifier circuit is alternatively activated.
[0083]
As a result, the unit amplifier circuit of the sense amplifier SA is selectively operated without adding a special capacitor as a dummy capacitor and without destroying information held in the non-selected memory cell coupled to the selected word line. In addition, the precharge potential of the bit line corresponding to the non-selected memory cell can be held as it is without being discharged. As a result, the required operating current of the sense amplifier and the bit line precharge circuit can be greatly reduced, and the power consumption of the ferroelectric memory, which is increasing in scale and capacity, can be achieved. .
[0084]
FIG. 8 shows a partial block diagram of a second embodiment of a ferroelectric memory to which the present invention is applied. FIG. 9 shows a memory array ARY0 to ARY2 and one embodiment of its peripheral portion. A partial circuit diagram is shown. FIG. 10 shows a signal waveform diagram of one embodiment of the read operation for activating the memory array ARY0 of the ferroelectric memory of FIG. 8, and FIG. 11 shows that the memory array ARY1 is activated. A signal waveform diagram of one embodiment of the read operation is shown. The ferroelectric memory according to this embodiment basically follows the embodiment shown in FIGS. 1 to 7, and therefore, only the portions different from this will be described. Further, the following description regarding the memory arrays ARY0 to ARY3, the sense amplifiers SA0 to SA2, and the bit line connection circuits S0 to S1 will be made with representative examples.
[0085]
In FIG. 8, the ferroelectric memory of this embodiment includes four memory arrays ARY0 to ARY3. Among these, the memory arrays ARY1 and ARY2 are paired so as to share the sense amplifier SA1, and the memory arrays ARY0 and ARY3 occupy the corresponding sense amplifiers SA0 or SA2, respectively.
[0086]
Corresponding plate voltages VP0 to VP3 are respectively supplied to the memory arrays ARY0 to ARY3 from an internal voltage generation circuit (not shown). The sense amplifiers SA0 to SA2 are supplied with corresponding precharge control signals PC0 to PC2 and shared control signals SHR0, SHL1 and SHR1 and SHL2 from a clock generation circuit CPG (not shown), and also from the internal voltage generation circuit. The precharge voltages VC0 to VC2 are supplied. Further, n + 1-bit common source line signals CSP00 to CSP0n, CSN00 to CSN0n to CSP20 to CSP2n, and CSN20 to CSN2n are supplied to the sense amplifiers SA0 to SA2 from a Y address decoder YD (not shown). The plate voltages VP0 and VP3 and the precharge voltages VC0 and VC2 are set to the potential Vq, and the plate voltages VP1 and VP2 and the precharge voltage VC1 are set to the potential 3Vq.
[0087]
In this embodiment, the ferroelectric memory further includes bit line connection circuits S0 and S1 provided between adjacent memory arrays ARY0 and ARY1, and between memory arrays ARY2 and ARY3, respectively. These bit line connection circuits are supplied with n + 1 bit bit line connection control signals S00 to S0n and S10 to S1n from a Y address decoder YD (not shown).
[0088]
Here, the memory arrays ARY0 to ARY3 are, for example, m + 1 word lines W00 to W0m arranged in parallel with the vertical direction in the figure, as represented by the memory array ARY0 in FIG. N + 1 sets of complementary bit lines B00 * to B0n * arranged in parallel with each other. At the intersections of these word lines and complementary bit lines, (m + 1) × (n + 1) pairs of ferroelectric memory cells each comprising a ferroelectric capacitor Cst or Csb and an address selection MOSFET Qst or Qsb are arranged in a lattice pattern. . Corresponding plate voltages VP0 to VP3 are commonly supplied to the plates of the ferroelectric capacitors Cst and Csb of the ferroelectric memory cells constituting the memory arrays ARY0 to ARY3.
[0089]
The sense amplifiers SA0 to SA2 include, for example, n + 1 unit circuits provided corresponding to the complementary bit lines B00 * to B0n * of the memory array ARY0, as represented by the sense amplifier SA0 of FIG. Each of the unit circuits includes a unit amplifier circuit UA in which a pair of CMOS inverters are cross-coupled, a bit line precharge circuit composed of three N-channel type precharge MOSFETs NM to NO, and each unit amplifier circuit UA. Two switch MOSFETs (not shown) provided between the complementary input / output nodes and the complementary common data line CD0 * are included. Two shared N-channel MOSFETs NG and NH are provided between the complementary input / output nodes of each unit amplifier circuit UA and the corresponding complementary bit lines B00 * to B0n * of the right memory array ARY0.
[0090]
Each unit circuit of the sense amplifier SA1 includes another pair of shared MOSFETs NK and NL provided between the complementary input / output node of the unit amplifier circuit UA and the complementary bit lines B10 * to B1n * of the left memory array ARY1. Each unit circuit of the sense amplifier SA2 includes a pair of shared MOSFETs (not shown) provided between the complementary input / output nodes of the unit amplifier circuit UA and the complementary bit lines B30 * to B3n * of the left memory array ARY3. Including. Each unit circuit of the sense amplifiers SA0 to SA2 further includes a pair of N-channel type switch MOSFETs provided between the complementary input / output nodes of the unit amplifier circuit UA and the complementary common data lines CD0 * to CD2 *. Is not shown.
[0091]
Common source line signals CSP10 to CSP1n and CSN10 to CSN1n (not shown) are supplied from the Y address decoder YD to the unit amplifier circuits UA constituting each unit circuit of the sense amplifier SA1. A precharge control signal PC0 is commonly supplied to the gates of the precharge MOSFETs ND to NF, and a precharge voltage VC0 is commonly supplied to the commonly coupled sources of the precharge MOSFETs NE and NF. A shared control signal SHR0 is commonly supplied to the gates of the shared MOSFETs NG and NH.
[0092]
Next, each of the bit line connection circuits S0 to S1 is, for example, the complementary bit lines B00 * to B0n * and B10 * to B1n * of the memory arrays ARY0 and ARY1, as represented by the bit line connection circuit S0 in the figure. N + 1-type n + 1 pairs of switch MOSFETs NI and NJ provided corresponding to the N channel type. The gates of these switch MOSFET pairs are commonly coupled, and corresponding bit line connection control signals S00 to S0n are supplied from the Y address decoder YD.
[0093]
In FIG. 10, when the ferroelectric memory is not selected, both the precharge control signals PC0 and PC1 are set to a high level such as the power supply voltage VCC, and the shared control signals SHL0 and SHR0 to SHR1 are both high. It is set to a high level like the voltage VCH. The bit line connection control signals S00 to S0n are all set to a low level such as the ground potential VSS, and the word lines W00 to W0m and W10 to W1m are all set to a non-selection level such as the ground potential VSS. Further, the common source line signal lines CSP00 to CSP0n are all set to the invalid level of the ground potential VSS, and the common source line signal lines CSN00 to CSN0n are all set to the invalid level of the power supply voltage VCC.
[0094]
Thereby, the complementary bit lines B00 * to B0n * of the memory array ARY0 are connected to the corresponding unit circuit via the shared MOSFETs NG and NH of the sense amplifier SA0, and the precharge voltage VC0, that is, the potential via the precharge MOSFETs ND to NF. Precharged to Vq. Also, the complementary bit lines B10 * to B1n * and B20 * to B2n * of the memory arrays ARY1 and ARY2 are connected to corresponding unit circuits via the shared MOSFETs NK and NL and NP and NQ of the sense amplifier SA1, and the precharge MOSFET NM. Is precharged to the precharge voltage VC1, that is, the potential 3Vq through .about.NO.
[0095]
When the chip enable signal CEB is set to the low level and the ferroelectric memory is selected, the precharge control signals PC0 and PC1 are first set to the low level such as the ground potential VSS, and correspond to the designated memory array ARY0. While the shared control signal SHL0 is kept at a high level, the shared control signal SHL1 corresponding to the adjacent memory array ARY1 across the bit line connection circuit S0 is set to a low level such as the ground potential VSS. Further, the word line W00 of the memory array ARY0 designated with a slight delay is alternatively set to the selection level such as the high voltage VCH, and the complementary bit lines B00 * and B10 * of the memory arrays ARY0 and ARY1 are slightly delayed. The bit line connection control signal S00 corresponding to 1 is alternatively set to a high level such as the power supply voltage VCC, and the common source line signal lines CSP00 and CSN00 corresponding to the complementary bit line B00 * are alternatively selected a little later. Is set to an effective level such as the potential 2Vq or the ground potential VSS.
[0096]
As a result, first, in response to the low level of the shared control signal SHL1, the connection between the complementary bit lines B10 * to B1n * of the memory array ARY1 and the corresponding unit circuit of the sense amplifier SA1 is cut off, and the selection level of the word line W00. In response, the address selection MOSFETs Qst and Qsb of the corresponding n + 1 ferroelectric memory cells in the memory array ARY0 are turned on simultaneously. At this time, as described above, the plate voltage VP0 having the potential Vq is commonly supplied to the plates of the ferroelectric capacitors Cst and Csb of all the ferroelectric memory cells constituting the memory array ARY0, and the complementary bit line B00. All the non-inverted and inverted signal lines of * to B0n * are precharged to the potential Vq. For this reason, the polarization state of the n + 1 ferroelectric memory cells coupled to the word line W00 does not change despite the address selection MOSFETs Qst and Qsb being turned on, and the complementary bit lines B00 * to B0n. The levels of non-inverted and inverted signal lines of * do not change.
[0097]
When the selection operation of the word line W00 is completed and the bit line connection control signal S00 is alternatively set to the high level, the complementary bit line B00 * of the memory array ARY0 and the corresponding complementary bit line B10 * of the memory array ARY1 Are alternately connected, and charge sharing is performed between these complementary bit lines and the ferroelectric capacitors Cst and Csb of the selected ferroelectric memory cell. As a result, the potential of the non-inverted bit line B00T rises from the precharge potential Vq to a relatively high potential Vt3, and the potential of the inverted bit line B00B rises from the precharge potential Vq to a relatively low potential Vb3. At this time, the potential of the non-inverted bit line B10T decreases from the precharge potential 3Vq to the potential Vt3, and the potential of the inverted bit line B10B decreases from the precharge potential 3Vq to the potential Vb3.
[0098]
When the predetermined time has elapsed and the bit line connection control signal S00 is returned to the low level, the complementary bit line B10 * of the memory array ARY1 is separated from the corresponding complementary bit line B00 * of the memory array ARY0. Further, the minute potential difference between the non-inverted bit line B00T and the inverted bit line B00B is obtained by causing the common source line signals CSP00 and CSN00 to have an effective level such as the potential 2Vq or the ground potential VSS, thereby corresponding units of the sense amplifier SA0. Each of the signals is amplified by the amplifier circuit UA, and becomes a binary read signal in which the potential 2Vq is at a high level and the ground potential VSS is at a low level. A high level of a bit line selection signal (not shown) is received and transmitted to the complementary common data line CD0 *, and further output to the outside of the ferroelectric memory via the corresponding main amplifier and output buffer, and at the same time, the memory array ARY0. The ferroelectric memory cell in the selected state is rewritten.
[0099]
On the other hand, when the memory array ARY1 is activated, in the ferroelectric memory, the shared control signals SHR0 and SHR1 corresponding to the memory arrays ARY0 and ARY2 receive the ground potential VSS in response to the fall of the chip enable signal CEB. Low level. Further, the word line W10 of the memory array ARY1 designated with a slight delay is alternatively set to the selection level such as the high voltage VCH, and the complementary bit lines B00 * and B10 * of the memory arrays ARY0 and ARY1 are slightly delayed. The bit line connection control signal S00 corresponding to 1 is alternatively set to a high level such as the power supply voltage VCC, and the common source line signal lines CSP10 and CSN10 corresponding to the complementary bit line B10 * are alternatively selected a little later. The power supply voltage VCC or the potential is 2Vq.
[0100]
As a result, the low level of the shared control signals SHR0 and SHR1 is first received, and between the complementary bit lines B00 * to B0n * of the memory array ARY0 and the corresponding unit circuit of the sense amplifier SA0 and the complementary bit line B20 * of the memory array ARY2. The connection between .about.B2n * and the corresponding unit circuit of the sense amplifier SA1 is broken. In response to the selection level of the word line W10, the address selection MOSFETs Qst and Qsb of the corresponding n + 1 ferroelectric memory cells in the memory array ARY1 are turned on simultaneously. At this time, the plate voltage VP1 having a potential of 3Vq is commonly supplied to the plates of the ferroelectric capacitors Cst and Csb of all the ferroelectric memory cells constituting the memory array ARY1, and the complementary bit lines B10 * to B1n * are supplied. All non-inverted and inverted signal lines are precharged to a potential of 3 Vq. For this reason, the polarization state of the n + 1 ferroelectric memory cells coupled to the word line W10 of the memory array ARY1 does not change, and the levels of the non-inverted and inverted signal lines of the complementary bit lines B10 * to B1n * do not change. .
[0101]
When the selection operation of the word line W10 is completed and the bit line connection control signal S00 is alternatively set to the high level, the complementary bit line B10 * of the memory array ARY1 and the corresponding complementary bit line B00 * of the memory array ARY0 Are connected to each other, and charge sharing is performed between the complementary bit lines and the ferroelectric capacitors Cst and Csb of the selected ferroelectric memory cell of the memory array ARY1. As a result, the potential of the non-inverted bit line B10T of the memory array ARY1 decreases from the precharge potential 3Vq to the relatively high potential Vt4, and the potential of the inverted bit line B10B decreases from the precharge potential 3Vq to the relatively low potential Vb4. To do. At this time, the potential of the non-inverted bit line B00T of the memory array ARY0 rises from the precharge potential Vq to the potential Vt4, and the potential of the inverted bit line B10B rises from the precharge potential Vq to the potential Vb4.
[0102]
When the predetermined time has elapsed and the bit line connection control signal S00 is returned to the low level, the complementary bit line B00 * of the memory array ARY0 is separated from the corresponding complementary bit line B10 * of the memory array ARY1. Further, the minute potential difference between the non-inverted bit line B10T and the inverted bit line B10B is obtained by causing the common source line signals CSP10 and CSN10 to have an effective level such as the power supply voltage VCC or the potential 2Vq, thereby corresponding units of the sense amplifier SA1. Each is amplified by the amplifier circuit UA to become a binary read signal having the power supply voltage VCC at a high level and the potential 2Vq at a low level. A high level of a bit line selection signal (not shown) is received and transmitted to the complementary common data line CD1 *, and further output to the outside of the ferroelectric memory via the corresponding main amplifier and output buffer, and the memory array ARY1. The ferroelectric memory cell in the selected state is rewritten.
[0103]
As described above, in the ferroelectric memory of this embodiment, the corresponding complementary bit lines of both memory arrays are arranged between the memory arrays ARY0 and ARY1 and ARY2 and ARY3 which are arranged adjacent to each other and which are not substantially paired. Bit line connection circuits S0 and S1 are provided for selectively connecting each other. The complementary bit lines B00 * to B0n * and B10 * to B1n * and B20 * to B2n * and B30 * to B3n * constituting the adjacent memory arrays ARY0 and ARY1 and ARY2 and ARY3 have different potentials Vq or 3Vq, respectively. And the bit line capacitance acts as the dummy capacitance Cyt or Cyb when the other memory array is activated. As a result, also in this embodiment, it is possible to obtain the same effects as those of the embodiment of FIGS. 1 to 7, thereby achieving low power consumption of the ferroelectric memory.
[0104]
In this embodiment, the bit line precharge circuit composed of three N-channel MOSFETs is shared by, for example, a pair of memory arrays ARY1 and ARY2 that share the sense amplifier SA1, as in the prior art. The chip size of the ferroelectric memory including the memory array pair is reduced.
[0105]
The effects obtained from the above embodiments are as follows. That is,
(1) Sense including a memory array in which ferroelectric memory cells including a ferroelectric capacitor and an address selection MOSFET are arranged in a lattice pattern, and a plurality of unit amplifier circuits provided corresponding to each bit line of the memory array In a nonvolatile memory device such as a ferroelectric memory having an amplifier, a bit line of a memory array is precharged to the same potential as a plate voltage supplied to a plate of a ferroelectric capacitor of a ferroelectric memory cell. Also, a dummy capacitor precharged to a potential different from the plate voltage is provided, and after the designated word line selection operation is completed, the dummy capacitor and the designated bit line are connected, and the sense amplifier Only the unit amplifier circuit corresponding to the designated bit line is selectively activated. As a result, the unit amplifier circuit of the sense amplifier can be selectively activated without destroying the information held in other non-selected memory cells coupled to the selected word line, and is compatible with non-selected memory cells. As a result, the precharge potential of the bit line can be held as it is without discharging.
[0106]
(2) According to the above item (1), the required operating current of the sense amplifier and the bit line precharge circuit can be greatly reduced.
(3) According to the above item (2), it is possible to achieve the effect of reducing the power consumption of a ferroelectric memory or the like that is being increased in scale and capacity.
(4) In the above items (1) to (3), a plurality of memory arrays that are selectively activated are provided in a ferroelectric memory or the like, and the bit lines of adjacent memory arrays are precharged to different potentials. Then, by using the capacity of each bit line of the memory array in the inactive state as the dummy capacity for each bit line of the memory array in the active state, the above-mentioned (( The effect that the effects of items 1) to (3) can be obtained is obtained.
[0107]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the ferroelectric memory does not require the shared sense method to be used, and each memory array can be divided into a plurality of memory mats including its peripheral portion. In addition, the ferroelectric memory can adopt a so-called address multiplex system in which the X address signal and the Y address signal are supplied in a time-division manner through a common address input terminal, and the number of bits of each address signal is also set. Is optional. Ferroelectric memory can take any bit configuration such as x4 bit, x8 bit or x16 bit, its block configuration, names of start control signals and internal control signals, combinations and effective levels, and polarity of power supply voltage Can take various embodiments.
[0108]
In FIG. 2, the memory arrays ARYL and ARYR of the ferroelectric memory can include a predetermined number of redundant elements, and various array configurations including a so-called 1-cell 1-transistor type can be adopted. In addition, when the operating current for bit line precharging is not a problem, the shared MOSFETs N5 and N6 and N7 and N8 may be turned on or off simultaneously. In this embodiment, the designated bit line of the memory array ARYL or ARYR and the corresponding unit circuit of the sense amplifier SA are selectively connected, and the unit amplifier circuit of the sense amplifier SA is alternatively selected. For example, a predetermined number of the complementary bit lines of the memory arrays ARYL and ARYR and the unit amplifier circuit of the sense amplifier SA are group-divided into groups, and these groups are selectively connected as a unit to set the operation state. Also good. The memory arrays ARYL and ARYR, the bit line precharge circuits PL and PR, the specific configuration of the sense amplifier SA, the conductivity type of the MOSFET, etc. can take various embodiments, and the plate voltages VPL and VPR and the precharge voltages VCL and VCR. The specific potential such as is also arbitrary.
[0109]
In FIG. 3, the information retention characteristic of the ferroelectric memory cell is a standard example and does not limit the present invention. 4 and 6, the activation control signal, internal control signal, absolute time relationship and effective level of the word line and complementary bit line, etc. of the ferroelectric memory are not limited to this embodiment. In FIG. 8, the ferroelectric memory can include any number of memory arrays and their peripheral parts. In FIG. 9, when the operating current for bit line precharging does not matter so much, the switch MOSFETs NI and NJ of the bit line connection circuits S0 and S1 may be simultaneously turned on or off. 10 and 11, the activation control signal and internal control signal of the ferroelectric memory, and the absolute time relationship and effective level of the word line and complementary bit line can be arbitrarily set.
[0110]
Further, in the above embodiment, the bit line capacitance of the corresponding complementary bit line of the adjacent memory array is used as the dummy cell for the read operation, but a dedicated dummy cell can be provided instead. In this case, only one dedicated dummy cell may be provided, and this dummy cell and the designated complementary bit line of the memory array may be alternatively connected.
[0111]
In the above description, the case where the invention made mainly by the present inventor is applied to the ferroelectric memory, which is the field of use behind it, has been described. However, the present invention is not limited to this. The present invention can also be applied to a digital integrated circuit device such as a single chip microcomputer incorporating a shadow RAM having a mode or a ferroelectric memory. The present invention can be widely applied to a nonvolatile memory device having a memory array in which at least ferroelectric memory cells are arranged in a lattice and a device or system including the nonvolatile memory device.
[0112]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, a sense amplifier including a memory array in which ferroelectric memory cells including ferroelectric capacitors and address selection MOSFETs are arranged in a lattice pattern, and a plurality of unit amplifier circuits provided corresponding to each bit line of the memory array Is precharged to the same potential as the plate voltage supplied to the plate of the ferroelectric capacitor of the ferroelectric memory cell. Also, a dummy capacitor precharged to a potential different from the plate voltage is provided, and after the designated word line selection operation is completed, the dummy capacitor and the designated bit line are connected, and the sense amplifier Only the unit amplifier circuit corresponding to the designated bit line is selectively activated. In addition, when a ferroelectric memory or the like has a plurality of memory arrays that are selectively activated, each bit of the memory array that is in an inactive state is precharged to different bit lines of adjacent memory arrays. The capacity of the line is used as the dummy capacity for each bit line of the active memory array. As a result, the unit amplifier circuit of the sense amplifier is selectively brought into an operating state without adding a special capacitor as a dummy capacitor and without destroying information held in an unselected memory cell coupled to the selected word line. In addition, the precharge potential of the bit line corresponding to the non-selected memory cell can be held as it is without being discharged. As a result, the required operating currents of the sense amplifier and the bit line precharge circuit can be greatly reduced, and the power consumption of a ferroelectric memory or the like that is being increased in scale and capacity can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a ferroelectric memory to which the present invention is applied.
2 is a circuit diagram showing one embodiment of a memory array and its peripheral part included in the ferroelectric memory of FIG. 1; FIG.
3 is an information retention characteristic diagram showing one embodiment of a ferroelectric memory cell constituting the memory array of FIG. 2. FIG.
4 is a signal waveform diagram showing one embodiment of a read operation for activating a memory array ARYL of the ferroelectric memory of FIG. 1; FIG.
5 is a conceptual diagram for explaining an operation principle of a read operation for activating a memory array ARYL of the ferroelectric memory in FIG. 1; FIG.
6 is a signal waveform diagram showing an example of a read operation for activating the memory array ARYR of the ferroelectric memory of FIG. 1; FIG.
7 is a conceptual diagram for explaining the operating principle of a read operation that activates the memory array ARYR of the ferroelectric memory of FIG. 1; FIG.
FIG. 8 is a partial block diagram showing a second embodiment of a ferroelectric memory to which the present invention is applied;
9 is a partial circuit diagram showing one embodiment of a memory array and its peripheral part included in the ferroelectric memory of FIG. 8; FIG.
10 is a signal waveform diagram showing one example of a read operation for activating the memory array ARY0 of the ferroelectric memory in FIG. 8; FIG.
11 is a signal waveform diagram showing an example of a read operation for activating the memory array ARY1 of the ferroelectric memory in FIG. 8; FIG.
[Explanation of symbols]
ARYL, ARYR: Memory array, XDL, XDR: X address decoder, XB: X address buffer, PL, PR: Bit line precharge circuit, SA: Sense amplifier, YD: Y address decoder, YB: ... Y address buffer, MA ... main amplifier, IB ... input buffer, OB ... output buffer, CG ... clock generation circuit.
Din: Data input terminal, Dout: Data output terminal, CEB: Chip enable signal input terminal, WEB: Write enable signal input terminal, OEB: Output enable signal input terminal, AX0 to AXi: X address input terminal , AY0 to AYj... Y address input terminal.
WL0 to WLm, WR0 to WRm... Word line, BL0 * to BLn *, BR0 * to BRn *... Complementary bit line, Cst, Csb... Ferroelectric capacitor, Qst, Qsb. VPR: Plate voltage, PC: Precharge control signal, VCL, VCR: Precharge voltage, SHL0 to SHLn, SHR0 to SHRn: Shared control signal, BS0 * to BSn *: Each of the sense amplifier unit amplifier circuits Complementary input / output nodes, CSP0 to CSPn, CSN0 to CSNn: common source line signal, YS0 to YSn: bit line selection signal, CD *: complementary common data line.
Cst, Csb: Ferroelectric capacitor capacity, Cdt, Cdb: Bit line capacity, Cyt, Cyb: Dummy capacity, Swt, Swb, Sst, Ssb: Switch.
ARY0 to ARY3 ... Memory array, VP0 to VP3 ... Plate voltage, XD0 to XD3 ... X address decoder, SA0 to SA2 ... Sense amplifier, S0 to S1 ... Bit line connection circuit, PC0 to PC2 ... Precharge Control signal, VC0 to VC2... Precharge voltage, SHL1 to SHL2, SHR0 to SHR1... Shared control signal, CD0 * to CD2 *.
W00 to W0m to W20 to W2m... Word line, B00 * to B0n * to B20 * to B2n *... Complementary bit line, UA... Sense amplifier unit amplifier circuit, S00 to S0n.
P1-P2 P channel MOSFET, N1-NQ N-channel MOSFET.

Claims (3)

Having a plurality of memory arrays selectively activated;
Each of the plurality of memory arrays is
A bit line precharged to a first potential;
A word is provided between a ferroelectric capacitor that receives the plate voltage, which is the first potential, on one electrode thereof, and the bit line corresponding to the other electrode of the ferroelectric capacitor, the gate of which corresponds to the corresponding word. A ferroelectric memory cell including an address select MOSFET commonly coupled to the line;
A dummy capacitor precharged to a second potential different from the first potential;
Switch means for selectively connecting between the dummy capacitor and the designated bit line;
And capacity of the ferroelectric capacitor, and read out and the capacitance of said corresponding bit line, the data held in the specified the ferroelectric memory cell by charge sharing between the capacitor of the dummy capacitance,
The dummy capacitor and the switch means are provided corresponding to the bit line,
The nonvolatile memory device according to claim 1, wherein the dummy capacitor for the memory array to be activated is formed by using the capacity of the corresponding bit line of another memory array that is not activated . In claim 1,
The nonvolatile memory device includes a sense amplifier including a plurality of unit amplifier circuits provided corresponding to the bit lines,
The non-volatile storage device according to claim 1, wherein the unit amplifier circuit is selectively activated in response to designation of the corresponding ferroelectric memory cell. In claim 2,
The plurality of memory arrays include first and second memory arrays;
The bit lines constituting the first memory array are precharged to a first potential having an absolute value of one-fourth of the power supply voltage of the circuit,
The bit lines constituting the second memory array are precharged to a second potential having an absolute value of three-fourths of the power supply voltage of the circuit,
The first and second common source line signals for selectively operating the unit amplifier circuit are:
When the first memory array is activated, a third potential having an absolute value of two-fourths of the power supply voltage of the circuit or a ground potential of the circuit is set to its effective level,
A nonvolatile memory device characterized in that, when the second memory array is activated, the power supply voltage of the circuit or the third potential is set to its effective level.

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