TW579519B - Semiconductor memory device - Google Patents

Abstract

A row address decoder of a semiconductor memory device generates internal row address signals RAD0:11 and /RAD0:11 by switching most significant bit and least significant bit of row address signals RA0:11 and /RA0:11 that correspond to address signals A0 to A11, respectively. In a twin cell mode, the least significant bits RAD0 and /RAD0 of the internal row address signals corresponding to the most significant bits RA11 and /RA11 of the row address signal that are not used are selected simultaneously by row address decoder, and two adjacent word lines are activated simultaneously. Consequently, the configuration of memory cell in the semiconductor memory device can electrically be switched from the normal single memory cell type to the twin memory cell type.

Description

579519 Description of the invention [Technical field to which the invention belongs] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor that uses two memory cells to store 1-bit memory data of memory information expressed as binary information. Memory device. [Prior art] As a representative example of a semiconductor memory device, a DRAM (Dynamic Random Access Memory: dynamic random access memory), a memory cell that usually stores 1-bit data includes a transistor, And a capacitor, and because the structure of the memory unit itself is simple, it is most suitable for high integration and large capacity of semiconductor devices, and can be used in various electronic devices. FIG. 13 is a circuit diagram showing a memory cell array arranged in rows and rows on a memory cell array in a DRAM (hereinafter, this type of DRAM is referred to as a single memory cell type). The composition system includes a transistor and a capacitor. Referring to FIG. 13, the memory unit 100 includes an N-channel MOS transistor N101 and a capacitor C101. The N-channel MOS transistor N101 is connected to the bit line BL and the capacitor C 101, and its gate is connected to the word line WL. The other end, which is different from the connection between the capacitor C101 and the N-channel MOS transistor N101, is connected to the unit board 110. The N-channel MOS transistor N101 is driven by a word line WL that is activated only during data writing and data reading, and is turned on only during data writing and data reading. cutoff. 5 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 579519 Capacitor C 1 0 1 stores binary information “1”, “0” according to whether there is an accumulated charge. When data is written to the capacitor C 101, the bit line BL is pre-charged to the power supply voltage Vcc or the ground voltage V D D in accordance with the written data. Then, the N-channel M 0 S transistor and the body N 1 0 1 are turned on by activation of the word line WL, and corresponding binary information is transmitted from the bit line BL through the N-channel M 0 S transistor N 1 0 1%. A voltage of "1" "" is applied to the capacitor C 1 0 1. This allows capacitor C101 to be charged and discharged, and data to be written. On the other hand, when reading data, the bit line B L is precharged to a voltage Vcc / 2 in advance. Then, by activating the word line WL, the N-channel MOS transistor N101 is turned on, and the bit line BL and the capacitor C101 are turned on. Thereby, a small voltage change corresponding to the storage state of the capacitor C 1 0 1 will appear on the bit line BL, and a sense amplifier (not shown) will amplify the small voltage change to the voltage Vcc or the ground voltage GND . The voltage level of the bit line BL corresponds to the state of the data being read. Here, in the memory cell of DRAM, the charge of capacitor C101, which is equivalent to storing data, will leak due to various reasons, and gradually disappear. That is, the memory data will disappear over time. Therefore, in D R AM, at the time of data reading, before the voltage change of the bit line B L corresponding to the data of billions of data cannot be detected, the so-called rewrite is performed once the data is read out. < reinstatement of incoming changes. % Although the refresh operation is indispensable in DRAM, the refresh operation becomes a disadvantage from the viewpoint of speeding up the operation. Therefore, it is known that it is a kind of dual-memory-type memory that allocates two bits of 1-bit memory data, 6 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc. The technology can increase the interval between renewal operations and speed up the access to memory data. Fig. 14 is a circuit diagram showing the arrangement of memory cells arranged in rows and columns on a memory cell array in a dual memory cell type DRAM. Referring to FIG. 14, the memory cell in the DRAM is a dual memory cell type composed of two memory cells 100A and 100B that are allocated to 1-bit memory data and allocated to store its memory data and inverted data of the memory data, respectively. . The memory unit 100A includes an N-channel MOS transistor N102 and a capacitor C102; and the memory unit 100B includes an N-channel MOS transistor N103 and a capacitor C103. N-channel MOS transistor N102 is connected to azimuth element line BL and capacitor C 1 2 of bit line pair BL, / BL, and its gate is connected to word line WLn (n is an even number greater than 0) . The N-channel MOS transistor N102 is driven by the word line WLn which is activated only during data writing and data reading, and is turned on only during data writing and data reading. cutoff. The N-channel MOS transistor N103 'is connected to the other directional element line / BL of the bit line pair bl, / BL and the capacitor C103, and its gate is connected to the word line WLn + i. The N-channel MOS transistor N103 is driven by WLn + 1 which is activated simultaneously with WLn, and is turned on only during data writing and data reading, and is turned off at other times. Denya C102 and C103 'store binary information "1" and "〇" according to whether there is an accumulated charge. Capacitor C103 is the inverted data of the memory data stored in capacitor C02. One end of the capacitor c 1 02 is connected to 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 7 on the N-channel MOS transistor N102, and the other end is connected to the unit board 110. One end of the capacitor C103 is connected to the n-channel MOS transistor N103 'and the other end is connected to the unit board 110. When writing 1-bit memory data to the capacitors C 1 02 and C 1 03, the bit line BL is precharged to one of the power supply voltage Vcc or the ground voltage VDD corresponding to the written data, and the bit is set. The element line / BL is precharged to a voltage different from the bit line BL. Then, the word lines wLn, WLn + 1 are simultaneously activated to simultaneously turn on the N-channel MOS transistors N1 02, 1 03, and the corresponding memory is stored from the bit line BL through the N-channel M 0 S transistor N 1 0 2 The voltage of the data is applied to the capacitor C 102; the voltage corresponding to the inverted data of the memorized data is applied to the capacitor C103 from the bit line / BL through the N-channel MOS transistor N103. With this, the capacitors C102 and C103 can be written with 1-bit memory data. On the other hand, when reading data, the bit lines B L and / B L are precharged to a voltage Vcc / 2 in advance. Then, by simultaneously activating the word lines WLn, WLn + I, the N-channel MOS transistors N102, N103 are simultaneously turned on, the bit line BL and the capacitor C102 are energized, and the bit line / BL and the capacitor C103 are energized. As a result, a slight voltage change in the opposite direction will occur on the bit lines BL and / BL, and a sense amplifier (not shown) will detect the potential difference between the bit lines BL and / BL and amplify the voltage to Vcc Or ground voltage GND. The amplified voltage level corresponds to the state of the data being read. The dual memory unit allocates two memory units to 1-bit data. Although it does indeed double the area of the memory unit compared with the conventional memory unit, the two memory units store each other inversely. The transferred information is 326 \ Patent Specification (Supplement) 92-〇2 \ 911336〇l.doc 579519, so the amplitude of the potential difference between the bit line pair BL and / BL will increase, the operation will be more stable, and the The advantage of increasing the interval between refresh actions. Furthermore, in the current dual memory cell DRAM, although the data is read out, the bit line pair BL, / BL is precharged to a voltage of 1/2 Vcc as in the single memory cell DRAM described above, but the Blessing, when the memory data is read out by the bit line pair BL, / BL, since the voltage of the bit line pair BL, / BL will change to each other in the opposite direction, when compared with the single memory cell type DRAM described above There are two times the amplitude of the voltage change on the bit line corresponding to the memory data, and the dual memory cell DRAM has the advantage of high-speed access to data during data read. As mentioned above, the single memory cell type DRAM shown in FIG. 13 and the double memory cell type DRAM shown in FIG. 14 only allocate one memory cell or two memory cells to the 1-bit memory data. There are differences. The basic structure of the remaining memory units is the same. Therefore, in the process of manufacturing a semiconductor memory device, if it is not separately produced a single memory cell type and a dual memory cell type from the beginning, but if the single memory cell type can be switched to a dual memory cell type during the manufacturing process, it is expected to have The advantages of manufacturing process reduction or flexible corresponding stages, and manufacturing cost reduction. Here, when switching from a single memory cell type to a dual memory cell type, although the pattern switching of the aluminum wiring can be used to switch in the wiring step, this method requires the mask pattern to be separated. The photomask steps are different accordingly, so the manufacturing cost cannot be reduced sufficiently. On the other hand, if the electrical switching can be performed without accompanying the switching of the structure of the semiconductor memory device, the single memory cell type and the dual memory cell 9 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc type The mask pattern can be unified, and since the mask steps can also be unified, the manufacturing cost can be greatly reduced. [Summary of the Invention] Therefore, the present invention was developed to solve such a problem, and its object is to provide a semiconductor memory device capable of switching a single memory cell type to a dual memory cell type in the configuration of the memory cell. A semiconductor memory device that performs this switching operation electrically. According to the present invention, a semiconductor memory device is provided with a memory cell array including a plurality of memory cells arranged in rows and columns; a plurality of word lines arranged in a column direction; and a plurality of bits arranged in a row direction. A line pair; and a decoder, which selects a specifically designated word line and a specifically designated bit line pair from a plurality of word lines and a plurality of bit line pairs, respectively, according to a specially designated address signal of each of the plurality of memory cells ; Among them, when two memory cells are used to store the 1-bit memory data signal of the memory information expressed as binary information, the dual-cell mode signal is activated, and the decoder will select the word line for activating the two memory cells. And bit line pairs, and the two memory units' store the memory data and the inverted data of the memory data, respectively. Preferably, the decoder generates an internal column address signal for selecting a specially designated word line according to the address signal. When the dual-cell mode signal is activated, then the designated bit of the internal column address signal is also selected. The logic level of the element corresponds to the first word line at the first logic level, and the logic level of the designated bit corresponds to the second word line at the second logic level. Preferably, the specified bit is the lowest order bit of the internal column address signal; the decoder is the one that does not prevent the 10-326 \ Patent Specification (Supplement) 92- when the dual-unit mode signal is activated. 02 \ 91133601.doc uses the highest order bit of the address signal to the lowest order bit of the internal column address signal, and allocates the lowest order bit of the address signal to the highest order of the internal column address signal Bit. Preferably, a semiconductor memory device is further provided with a refresh control circuit for periodically performing a refresh operation in order to maintain the memory information; the refresh control circuit generates a memory cell row for designating a refresh operation object The restoration column address; the restoration column address contains a part of at least one bit of self-recovery address bit, which is used to specify a part of the memory cell array to perform the restoration operation. ; The decoder includes a selection circuit, which selects at least one part of the self-recovery address bits from the restoring column addresses which are different depending on whether the dual-unit mode signal is activated. As described above, in the semiconductor memory device of the present invention, according to the dual cell mode signal, it is possible to electrically switch from a semiconductor memory device having a function as a normal single memory cell type to a semiconductor memory device having a function as a dual cell memory type. Semiconductor memory device. Therefore, if the semiconductor memory device according to the present invention is used, it is not necessary to switch the reticle pattern to be separately manufactured, but the number of reticle and process can be reduced to reduce the manufacturing cost. [Embodiment] (Best Mode for Implementing the Invention) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In addition, the same or corresponding parts are denoted by the same reference numerals in the drawings, and the description thereof will not be repeated. (Embodiment 1) 11 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 579519 Fig. 1 is a schematic block diagram showing the overall structure of a semiconductor memory device according to Embodiment 1 of the present invention. Referring to FIG. 1, the semiconductor memory device 10 includes a control signal terminal 12, an address terminal 14, and a data input / output terminal 16. The semiconductor memory device 10 includes a control signal buffer 18, an address buffer 20, and an input / output buffer 22. Furthermore, the semiconductor memory device 10 includes a control circuit 24, and a column address. Decoder 2 6, Row Address Decoder 2 8, Input / Output Control Circuit 30, Sense Amplifier 32, and Billion Cell Array 34. In addition, in FIG. 1, for the semiconductor memory device 10, Only the main parts of data input and output are representatively displayed. The memory cell array 34 is a billion-element component group in which the billion-element units are arranged in rows and rows; and it is composed of four groups that can operate independently. Correspondingly, the 100 million cell array 34 is composed of four groups. The column address decoder 26, the row address decoder 28, the input / output control circuit 3 0, and the sense amplifier 32 are also provided respectively. Four. Control signal terminals 1 2 are command control signals that accept chip selection signal / CS, column address selection | communication number / RAS, row address strobe signal / CAS, and write enable signal / WE. Control signal Buffer 18, which takes the chip from the control signal terminal 12 Selection signal / CS, column address strobe signal / RAS, row address strobe signal / CAS and write enable signal / WE and latched 're-output, to the control circuit 2 4... Address terminal 14 It accepts the address signals A0 ~ An (η is a natural number) and the group address signals BAA0 and BAA1. The address buffer 20 includes a column address buffer and a row address buffer (not shown). The address buffer 12 of the address buffer 20 is 12 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 579519 The punch is to take the address signals AO ~ An and the group address signals BAO and BAl and latch them. Lock, and then output the column address signal RA to the column address decoder 2 6 corresponding to the group indicated by the group address signal BAO, BA1 < 0: η >, / RA < 〇: η > (for arbitrary symbols X, χ < 〇 ·· means X < 0 > ~ X < η >). In addition, the row address buffer of the address buffer 20 takes the address signals A0 ~ An and the group address signals BAO and BΑ1 and latches them, and then matches the group address signals BA 0 and BA. The row address decoder 28 corresponding to the group indicated by 1 outputs a row address signal CA < 0: n >, / CA < 0: η >. The data input / output terminal 16 is a terminal for outputting and inputting the read / write data with the outside in the semiconductor memory device 10; when the data is written, it accepts the externally input data DQ0 ~ DQi (I is a natural number) When the data is read, the data DQ0 to DQi are output to the outside. The input / output buffer 22 is used to read and latch data DQ0 to DQi during data writing, and output the internal data ID Q to the input / output control circuit 30. On the other hand, the input / output buffer 22 is used to output the internal data IDQ received from the input / output control circuit 30 to the data input / output terminal 16 when the data is read. The control circuit 24 fetches the instruction control signal from the control signal buffer 18, and controls the column address decoder 26, the row address decoder 28, and the input / output buffer 22 according to the received instruction control signal. The column address decoder 26 is based on the column address signal R A received from the address buffer 20 < 0: η >, / RA < 0: n >, and a signal R A D for selecting a word line on the memory cell array 34 is generated. < 0: η >, / R A D < 0: η >. Then, the column address decoder 26, according to the signal R A D < 0: η >, 13 3 Patent Specification (Supplement) 92-02 \ 91133601 .doc / RAD < 0: η > to decode a column address and select a word line on the memory cell array 34 corresponding to the decoded address. Then, the selected word line can be activated by the zigzag driver. The row address decoder 28 is based on the row address signal CA of the slave address buffer 20. < 0: η >, / CA < 0: η > to decode a row to select a bit line pair in which the hundred million cells corresponding to the decoded row address are dropped. When data is written, the input / output control circuit 30 outputs the internal data IDQ received from the output device 22 to the sense amplifier 32 and the sense amplifier 32. Then, the address is decoded according to the logic level of the internal data id Q The bit line pair selected by the device 2 8 is precharged to the power supply or ground voltage GND. With this, internal data can be written to the memory cells on the memory cell array 34 connected to the word line and the bit, where the word line is activated by the column address decoder 26, and the bit by the row address The decoder 28 selects and is precharged by the sense amplifier 32. On the other hand, during data reading, the sense amplifier 32 precharges the bit line pairs selected by the row address decoder 28 Vcc / 2, and after detecting / amplifying the slight voltage change generated by corresponding reading in the selected bit line pair, the logic bit of the read data is judged to be output to the input / output control circuit 30. Then, the input-output control circuit outputs the read-out data received from the sense amplifier 32 to the amplifier 22. As mentioned above, the memory cell array 34 is composed of groups that can be moved independently, and each of the groups of the memory cell array 34 is listed in 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc The bit does not show the accepted address, I column 34 is put into the buffer, and the row presses the Vcc element line to the IDQ element line. The data is read until the voltage is out of the data, and then it goes to 30, and the four that are in and out are transparently connected to the column address decoder 26 through the word lines arranged in the column direction on the group, and through the group. The bit line pairs arranged in the row direction are connected to the sense amplifier 32. FIG. 2 is a circuit diagram showing a memory cell array 34 arranged on a memory cell array 34 of a semiconductor memory device 10. In addition, in FIG. 2, ^ indicates the four memory cells adjacent to the column direction among the memory cells arranged on the memory cell array 34. Referring to FIG. 2, the memory unit 3 4 0 includes an N channel MOS transistor 4 NO and a capacitor C0; the memory unit 341 includes an N channel MOS transistor N1 and a capacitor C1; the memory unit 3 42 includes There are N-channel MOS transistor N2 and capacitor C2; the memory unit 343 includes N-channel MOS transistor N3 and capacitor C3. The N-channel MOS transistor NO is connected to the bit line BL and the capacitor C0, and its gate is connected to the word line WL0. The N-channel MOS transistor NO is driven by the word line WL0 that is activated only during data writing and data reading, and is turned on only during data writing and data reading. < Outside time will expire. Capacitor C0 stores binary information "1" and "0" according to whether or not there is an accumulated charge. One end of the capacitor C0 is connected to the N-channel MOS transistor NO, and the other end is connected to the unit board 77. Then, through the N * channel MOS transistor NO, the charge in and out are completed with the bit line BL, and data is written / read out to the capacitor C0. The N-channel MOS transistor N1 is connected to the bit line / BL and the capacitor C1, and its gate is connected to the word line WL1. N-channel MOS transistor 15 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 579519 N 1 is driven by the word line WL 1 which is activated only during data writing and data reading, and only It is turned on when data is written and when data is read, and other times are closed. Capacitor C1 stores binary information "1" and "0" according to whether there is a stored charge. One end of the capacitor C1 is connected to the N-channel MOS transistor N1, and the other end is connected to the unit board 77. Then, through the N channel MOS transistor N1, the charge line is completed with the bit line / BL, and data is written to / read from the capacitor C1. The N-channel MOS transistor N2 is connected to the bit line / BL and the capacitor C2, and its gate is connected to the word line WL2. The N-channel MOS transistor N2 is driven by the word line WL2 which is activated only during data writing and data reading, and is turned on only during data writing and data reading, and at other times, cutoff. Capacitor C2 stores binary information "1" and "0" according to whether or not a charge is accumulated. One end of the capacitor C2 is connected to the N-channel MOS transistor N2, and the other end is connected to the unit board 77. Then, through the v-channel MOS transistor N2, the charge in and out are completed with the bit line / BL, and the data is written to / read from the capacitor C2. The N-channel MOS transistor N3 is connected to the bit line BL and the capacitor C3 ', and its gate is connected to the word line WL3. The N-channel MOS transistor N3 is driven by the word line WL 3 which is activated only during data writing and data reading, and is turned on only during data writing and data reading, and at other times It will be closed. The electric valley device C3 'stores binary data according to whether or not it has accumulated electric charges. 16 3 of 6 \ Patent Specification (Supplement) 92-02 \ 91133601.doc News "1", "0". One end of the capacitor C3 is connected to the N-channel MOS transistor N3, and the other end is connected to the unit board 77. Then, through the n-channel M0S transistor N3, the charge is transferred in and out with the bit line BL, and data is written to / read from the capacitor C3. When the semiconductor memory device 10 has a function as a single memory cell type semiconductor memory device, one bit of data can be stored in each of the memory cells 3 40 to 3 4 3. Then, when data is written / read to each of the memory cells 3 40 to 3 4 3, the corresponding word lines WL0 to WL3 are activated, and the bit line BL or bit line of the memory cell is connected. / BL Carries in and out of charge. On the other hand, when the semiconductor memory device 10 has a function as a double memory cell type semiconductor memory device, the adjacent memory cells 34 and 341 can store 1-bit data and use the adjacent memory cells. 342, 3 43 stores 1-bit data. The memory unit 3 4 3 is used to store the inverted logical level of the memory data of the memory unit 3 4 2. Then, when the data of the memory units 340 and 341 constituting the double memory unit is entered, the bit line BL can be precharged to the specified voltage corresponding to the target memory, and the bit line / BL can correspond to the memory data. Reverse the data and precharge to the specified voltage. Then, the word lines WL0 and WL1 are simultaneously activated, and the charge corresponding to the memory data is supplied from the bit line BL to the capacitor co, and the charge corresponding to the inverted data of the memory data is supplied from the bit line / BL to the capacitor C1. In addition, when data is written to the memory units 342, 3 4 3 constituting a double memory unit, the bit line BL can be pre-charged to correspond to the memory data to 17 326 Transmitting Manual (Supplement) 92-02 \ 91133601 .doc 579519, and the bit line / BL can be precharged to the specified voltage corresponding to the inverted data of the memory data. Then, the word lines WL2 and WL3 are simultaneously activated, and the charge corresponding to the memory data is supplied from the bit line BL to the capacitor C2, and the charge corresponding to the inverted data of the billion data is supplied from the bit line / BL to the capacitor C3. In this way, when the semiconductor memory device 10 is used as a dual memory cell, the data of the bit line pair BL, / BL is written in reverse to each other, and the adjacent word lines are activated at the same time, thereby, the adjacent Two memory cells in the row direction store 1-bit data. FIG. 3 is a schematic diagram illustrating the composition of the memory area in each group of the memory cell array 34. In addition, in the following description, when the semiconductor memory device 10 is operated as a normal single memory cell type semiconductor memory device, it has a memory capacity of 128M (million) bits and a word configuration of "x 3 2 ”semiconductor memory device function. That is, when the semiconductor memory device 10 is used as a normal single memory cell type, the highest order bit of the address signal An is All (n = 11). Referring to FIG. 3, each of the groups of the memory cell array 34 is composed of areas 51 to 56, and the entire area has a memory capacity of 32M bits (128M bits / 4 groups). Each of the groups of the memory unit 34 is arranged with 8 丨 92 word lines, and can be according to the signal RAD < 0: 1 1 >, / RAD < 0: 1 1》 and select the specified word line. In addition, the column address signal R A < 0: 1 1 >, / 1 ^ < 〇: 11 >, points 3!] Corresponds to the signal of the address signal from the outside, which is 0 ~ 11; the column address signal RA < 1 1〉, / R A < 1 1 > represents the highest order bit of the column address; and the column address signal R A < 0 >, / R A < 0 > indicates the lowest order bit of the column address. 18 326 \ Patent Specification (Supplement) 92-02 \ 91133601 .doc 579519 Memory area 5 1 ~ 5 3 ′ and memory area 5 4 ~ 5 6, the memory structure is the same, and can be based on the signal rad < 〇: 11 >, / RAD < 〇: i >, and the word lines of the same location are relatively selected in the respective regions. Areas 51 and 52 and areas 54, 55 are based on signal / rad < 11 > Logic · The selection level is selected, and areas 53, 56 are based on the signal rad < 11 > Logic-Select the level. Then, when the signal / RAD < i 丨 > When areas 51 and 52 and areas 54 and 55 are selected, areas 51 and 54 are selected according to the signal / rad. < 10 > is selected according to the logic level, and areas 52 and 55 are selected according to the signal RAD < 10 > is selected. Similarly, according to the signal raD < 0: ^ 1 1 >, / RAD < 0: 1 1 > lower order bits, the more subdivided area will be selected, and finally according to RAD < 0: 11 >, / RAD < 〇: ιι > The designated word line will be selected. Here, in the semiconductor memory device 10, when the column address signal RA is used, < 0: 11 >, / RA < 0: 11 > and generate a signal rad < 0: 11 >, / RAD < 0: 1 1 > column address signal RA < 0: 1 1〉, / RA < 〇: 1 1 > the highest order bit and the lowest order bit will be replaced to generate a signal RAD < 0: 1 1 >, / RAD < 0: 11 >. That is, the highest order bit RA of the 歹 IJ address < 1 1 >, / RA < 1 1 > assigned to signal RAD separately < 0: 1 1 >, / RADCO: 11> lowest order bit RAD < 0 >, / RAD < 0 >; and the lowest order bit RA of the column address < Ο >, / RA < Ο > assigned separately to signal RAD < Ο: 1 1 >, / RAD < Ο: 1 1〉 The highest order bitRAD < 1 1 >, / RAD < 1 1 >. Then, when the semiconductor memory device 10 has a dual memory cell type semiconductor memory device with a memory capacity of 64 megabits and a word configuration of "X 3 2", 19 326 \ Patent Specification (Supplement) 92-02 \ 91133601. doc function, when generating RAD < Ο: 1 1 >, / RAD < Ο: 1 lowest order bit RAD < 0 >, / RAD < 0> is selected at any time. Thereby, as shown in FIG. 3, adjacent word lines 61, 62, and word 64 are selected at the same time, and as shown in FIG. 2, adjacent memories are selected at the same time to form a double memory unit. In addition, when the semiconductor memory device 10 has a dual memory cell type semiconductor function as a memory capacity bit and the word configuration is "X 3 2", the uppermost bit of the column address signal is > , / RA < 1 0 > while the column address signal RA < 11 >, / RA < Since it is not used, the address signal RA is changed even in the semiconductor memory device 10 < 1 1 >, / RA < 1 1 > Corresponding signal RAD · / RAD < 0 >, there is no problem in specifying the address. Figure 4 shows the RAD generated in the column address decoder 26. < 0: 11 >, / RAD < 0: 11 > lowest order bit RAD / RAD < 0 > RAD < 0 > The circuit configuration of the generating circuit {? Referring to FIG. 4, RAD < 0 > The generating circuit includes: the highest order bit RA that accepts dual signals / TWIN and column address < 11 > Gate 71; Inverts the output of NAND gate 71 before outputting a signal RADInverter 72; Accepts dual cell mode signal / TWIN and column address bit / RA < 1 1 > NAND gate 73; and output signal / RAD after inverting NAND β output < 0 > inverter 74. Dual cell mode signal / TWIN is a signal of the logic bit L (logic low) level when the semiconductor memory device 10 is a function of a dual memory cell type semiconductor memory device; in the manufacture of the semiconductor memory device 1026 \ patent specification ( (Supplement) 92 · 02 \ 91133601.doc I > When often, the line 6 is selected. 3: The unit will be 6 4 megabytes worth of RA. < 1 0 II > write and column < 0 >, < 0 > Cell mode NAND < 0 > When the uppermost level of the stomach 73 is set, the logic level can be set by using 20 579519 to connect the dual-unit mode signal / TWIN to the power supply node or to the ground node. When the dual-cell mode signal / TWIN is at the L level, the NAND gates 71 and 73 correspond to the column address signal RA. < 1 1 >, / RA < 1 1 > The signal of the Η level is output independently regardless of the logic level, whereby the lowest order bit RAD < 0 >, / RAD < 〇 > are selected (lowest bit RAD < 〇 >, / RAD < 0 > The logical level is selected at L level). In addition, in the above description, the dual-unit mode signal / TWIN is generated by switching over the bo cable of its signal line, but it can also be set as one of the commands provided by the outside, and it can also be set for exclusive use. Terminals. Alternatively, a fuse circuit can also be set internally, and the dual-unit mode signal / TWIN can be set according to whether the fuse element of the fuse circuit is cut off during manufacture. As described above, if the semiconductor memory device 10 according to this embodiment is used, the adjacent word lines are activated at the same time according to the dual-cell mode signal, and the semiconductor memory device of the single-memory cell type is switched to the dual-electric mode. Memory cell type semiconductor memory devices, so it is not necessary to switch the mask pattern to separate production during the mask step phase, but the manufacturing cost can be reduced according to the reduction of the number of masks and the reduction of manufacturing steps. (Embodiment 2) The semiconductor memory device 1 of Embodiment 1 can be switched from a single memory cell type semiconductor memory device having a memory capacity of 12 8M bits and a word structure of "x32" to a memory capacity of 64M bits. And a semiconductor memory device of the double memory cell type of “X 3 2”, but the semiconductor memory device 10A of the second embodiment can be further switched to a memory capacity of 21 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 579519 6 4M bits, and the word structure is a double memory cell type semiconductor memory device of "x 1 6". As described above, the refresh operation is indispensable in DRAM, and during the refresh operation, each of the memory units that are the object of the refresh can perform the reading, amplification, and rewriting of data, and can retain the memory data. The refresh operation is performed on a word line arranged on the memory cell array, and the action cycle (hereinafter referred to as the refresh cycle) is considered in the refresh interval which can ensure the retention of data in each of the billion units. And word line before deciding. Referring again to FIG. 3, when a refresh operation is performed in each group of the memory cell array 34 in the semiconductor memory device 10 of Embodiment 1, according to the address signals A0 ~ A Π received by the address terminal 14 Column address signal RA < 0: 11 >, / RA < 0: 11 >, 4096 word lines in each of the regions 51 to 53 and 54 to 56 can be sequentially activated in each of the regions 51 to 53 and 54 to 56. That is, the restoration of all the 100 million units is completed with 4096 times of renewal operations (hereinafter, a case where 4096 times of renewal operations are required until the renewal of all the memory units is completed is referred to as "4K refresh", As will be described later, a total of 8192 word lines in areas 51 to 56 are activated in sequence, and a case where 8 192 renewal actions are required to complete the renewal of all memory cells is referred to as "8 K renewal"). The semiconductor memory device 10 A of the second embodiment is capable of 8K restoration, and in order to select 8 1 92 zigzag lines in sequence, a column address signal Ra is provided. < 1 2 >, / RA < 1 2>. Then, during the renewal operation, according to the column address signal RA < 0: 12 >, / RA < 0: 12 > Activating 8 1 92 zigzag lines in sequence in each group of memory cell array J 34 and completing 8 1 92 times 22 326 \ Patent Specification (Supplement) 92 -02 \ 91133601.doc 579519 into the restoration of all memory units. In the semiconductor memory device 10A, the uppermost bit RA < 1 2 >, / RA < 12 > Assign to signal RAD < 0: 12 >, / RAD < 0: 12 > lowest bit RAD < 0 >, / RAD < 0 > When the semiconductor memory device I 0 A has a function as a semiconductor memory device of a dual memory cell type, it is the same as the semiconductor memory device 1 of the first embodiment by using the lowest-order bit RAD < 0 >, / RAD < 0 > All are activated to have a function as a semiconductor memory device having a memory capacity of 64 Mbits and a word configuration of "X 1 6". The reason for this is that when the semiconductor memory device 10A has a function as a semiconductor memory device with a memory capacity of 64M bits and a word configuration of "X 1 6", the highest order bit system of the column address signal is RA < 1 1 >, / RA < II > and the column address signal RA < 12 >, / RA < 12 > becomes unused, so even within the semiconductor memory device 10 A, the column address signal RA is rewritten < 1 2 >, / RA < 12 > Corresponding signal RADCO>, / RAD < 0 >, there is no problem in specifying the address. Since the overall configuration of the semiconductor memory device 10A of the second embodiment is the same as that of the semiconductor memory device 10 of the first embodiment shown in FIG. 1, description thereof will not be repeated. FIG. 5 is a schematic view showing the unintended composition of the memory region in each group of the memory cell array 3 4 of the semiconductor memory device 100A. Referring to FIG. 5, in each group of the memory cell array 34 in the semiconductor memory device 10A, compared with the group of the memory cell array 34 in the semiconductor memory device 10 shown in FIG. 53 more by signal / RAD < 12 > is selected by the logic level, and the areas 54 to 56 are further selected by the signal RAD < 12 > 23 326 Chuanli Instruction Manual (Supplement) 92-02 \ 91133601 .doc 579519 is selected. Here, in the semiconductor memory device 10 A, the < 0: 12 >, / RA < 0: 12 > and generate a signal RAD < 0: 12 >, / R A D < 0: 1 2 > column address signal R A < 〇: 1 2 >, / R A < 0: 1 2 > the highest order bit and the lowest order bit will be replaced to generate a signal RAD < 0: 12 >, / RAD < 0: 12 >. That is, the highest order bit RA of the row address < 12 >, / RA < 12 > assigned to signal RAD separately < 0: 1 2 >, / RAD < 0: 12 > lowest bit RAD < 0 >, / RAD < 〇 >; the lowest-order bit RA of the column address < 0 >, / RA < 0 > are assigned to the signal RAD separately < 0: 1 2 >, / RAD < 0: 1 2 > highest order bit RAD < 12 > > / R AD < 1 2 >. Then, when the semiconductor memory device 10A has a function as a dual memory cell type semiconductor memory device with a memory capacity of 64M bits and a word configuration of "X 1 6", if the signal RAD is generated < 0: 12 >, / RAD < 0: 12〉, the lowest order bit RAD < 〇 >, / R AD < 〇 > Any one of them is often selected. Thereby, as shown in FIG. 5, the adjacent word lines 6 and 62 and the word lines 63 and 64 are selected at the same time, and the adjacent memory cells are selected at the same time to form a double memory cell. As described above, if the semiconductor memory device 10 A according to the second embodiment is used, since the highest order bit R A of the column address signal designed for 8 κ restoration is used < 1 2 >, / R A < 1 2 > can simultaneously activate adjacent word lines, so it can be switched from a single memory cell type semiconductor memory device to a memory capacity of 64M bits and the word structure is "x 1 6" double Memory cell type semiconductor memory device. 24 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 579519 (Embodiment 3) The semiconductor memory device of Embodiment 3 is provided with the semiconductor memory device 100A of Embodiment 2 and has a self-recovery function. Furthermore, it has a part of the memory area that can only be refreshed, so-called partial self-recovery function. · As mentioned above, during the refreshing operation, in each of the memory units to be the subject of the refreshing, data can be read out, enlarged, and rewritten periodically, and the stored data can be maintained. This refreshing action is performed on each word line. Then, in the self-renewal, the row address of the zigzag line for selecting the object to be renewed is internally generated, and then the renewal action is performed. In the partial self-recovery, the reset operation is performed only in the logical level of the upper 1 bit or the higher 2 bits of the column address, for example, in the memory area of the L level. Therefore, in the partial self-recovery, in order to properly restore a specified part of the area, it is necessary to have the semiconductor memory device function as a single memory cell type semiconductor memory device or have a dual memory cell type The function of the semiconductor memory device, or the highest order bit of the column address corresponding to the 8K restoration, corresponds to the restoration space in the partial self-recovery. Fig. 6 is a schematic block diagram showing the overall structure of a semiconductor memory device according to a third embodiment of the present invention. Referring to FIG. 6 ′, the semiconductor memory device 丨 丨 is provided with a refresh control circuit in addition to the conductor memory device 10 A of the second embodiment. 36. The restoration control circuit 36 includes a self-recovery control circuit 38 and a restoration address generation circuit 40. The restoration control circuit 36 is based on an instruction from the control circuit 24, and 25 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 579519 generates a column address (hereinafter, referred to as the restoration) New column address signal / QAD < 0: η >) and output to 歹 [J address decoder 2 6.歹 IJ address decoder 26 is based on an instruction from the control circuit 24, and during normal operation, it is based on the column address signal R A received by the address buffer 20. < 0: n >, / R A < 0: η > The selection of the memory cell array [J 3 4 is performed. On the other hand, in the self-recovery mode, the column address decoder 26 is based on the restored column address signal / QAD from the restoration control circuit 36. < 0: η > The selection of the zigzag lines in the memory cell array 34 is performed. The self-recovery control circuit 38 generates a refresh signal QCU based on a pulse wave signal generated by a signal sending circuit (not shown), and outputs the generated refresh signal QCU to the refresh address generation circuit 40. The refresh signal QCu is determined in each designated refresh cycle after considering the refresh interval that can ensure the retention of data in each memory cell in the memory cell array 34 and the number of word lines in the memory cell array 34. activation. The restoration address generating circuit 40 updates the restoration column address in accordance with the restoration signal QCu, and sequentially switches the memory cell φ row which is the object of the restoration operation. Specifically, the restoration column address signal / Q A D < 0: η > is counted up according to the refresh signal QCU. As described above, the semiconductor memory device 11 according to the third embodiment is not intended to further reduce the power consumption in the standby mode, but in the self-recovery mode'-type, the entire memory area is used as a target to perform the refresh operation. Instead, it takes a one-part memory area as the object to perform the renewal action, and has a so-called partial self-renewal function. In this part of the self-recovery, in each group 26 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 579519 of the memory cell array 34, the restoration cycle is only extended for the higher-order 2 bits. Then, in the use mode of the memory-cell-type memory cell-recovery function, FIG. 7 is a block diagram of the work function. Referring to FIG. 7, the counters 401 to 4 are counted from self-executing and upwards. The restored address will output the count data 11 > Refer to Figure 8 New column address signal / Q AD < 0: η > The upper level is 1-bit or is restored for the L-level memory area. This eliminates the need for time and reduces power consumption during standby mode. The semiconductor memory device 11 has the highest order bits of different column addresses in a case where it has a function as a normal single semiconductor memory device, a case where it has a function as a dual semiconductor memory device, and a case where it has 8K. According to this, it is appropriately allocated to the part of the self-renewal renewal space. The functional description of the restoration address generation circuit 40 shown in FIG. 6 and the restoration address generation circuit 40 includes the restoration address meter 12. The refresh address counter 40 1 corresponding to the lowest-order bit, and the refresh signal QCU output from the control circuit 3 8 are counted, and the count data is used as the refresh column address signal / QAD. < Each of the counters 40 1 to 4 1 2 is counted up in accordance with the count data output from the lower-order bit-side counter, and is used as a refresh column address signal / QAD, respectively. < 1 > ~ / QAD < 〇 During self-renewal, a renewal column address signal / Q AD for the memory cell column at each specified refresh cycle can be generated < 0: 1 1 >. Shows the circuit composed of the circuits of the renewal address counters 4 0 1 to 4 1 2. Each of the renewal address counters 401 to 412 includes: 27 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 579519 Inverters 8 2, 8 6 that invert the input signal; the logic level of the input signal is activated when the L level is activated, and the inverter 8 1 that inverts after receiving the output signal; constitutes the output of the inverter 8 1 Inverters 8 3, 84 to be latched by the latch circuit; the logic level of the input signal is activated on time and the inverter 8 5 which is inverted after receiving the output of the inverter 8 1; its input node N AND gate 8 7 connected to the power supply node and the output node of the inverter 85; and an inverter that constitutes a latch circuit that inverts the output of the inverter 85 together with the NAND gate 87 8 8. In each of the reset counters 401 to 412, when the logic level of the output signal is the L level, if the input signal is the L-bit criterion, the inverter 81 is activated, and the output of the inverter 81 becomes Η Level. On the other hand, at this stage, the inverter 85 is not activated, and the output of the inverter 81 is not transmitted to the output node of the inverter 85. Then, when the logic level of the input signal becomes the high level, although the inverter 81 is activated, the output of the inverter 81 is latched by the inverters 83 and 84. On the other hand, the inverter 85 is activated, and the inverter 85 outputs an L-level signal after inverting the input of the Η level. Therefore, the NAND gate 87 outputs a signal at a high level, and its output is latched by the NAND gate 87 and the inverter 88. Then, when the logic level of the input signal becomes the L level, the inverter 81 is activated, and the output of the inverter 81 becomes the L level. On the other hand, the inverter 85 is not activated, and the output of the inverter 81 is not passed to the output node of the inverter 85. Then, when the logic level of the input signal becomes the Η level, although the inverter 28 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 579519 inverter 81 is not activated, the output of inverter 81 will be Latched by inverters 8 3, 8 4. On the other hand, the inverter 85 is activated, and the inverter 85 outputs a signal of the Η level after inverting the input of the L level. Therefore, the NAND gate 87 outputs an L-level signal, and its output is latched by the NAND gate 87 and the inverter 88. ·

In this way, each of the renewal address counters 401 to 412 outputs an output signal with the period of the input signal set to 1/2, whereby the renewal column address signal / QAD &lt; 0: 11 &gt; will count up. I FIG. 9 is a circuit diagram showing a circuit configuration of an address selection circuit included in the column address decoder 26. The address selection circuit selects the column address signal RA &lt; 0: 1 1 &gt; and the restoration column position accepted by the address buffer 20 in accordance with the self-recovery mode signal QADSEL received by the control circuit 24. The address signal / Q AD &lt; 0: 1 1> is output as the signal RAD &lt; 0: 11 &gt;. In addition, in FIG. 9, in the description relationship, although the input signal and the output signal other than the self-recovery mode signal QADSEL are summarized, φ is shown to show metadata, and it is also summarized in the following description. Each meta-data signal is used for explanation, but actually each circuit has a circuit corresponding to each meta-data. Referring to FIG. 9, the address selection circuit includes an inverter 9 1 that receives a column address signal RA * &lt; 〇: 1 1 &gt; and inverts it; and receives a self-recovery mode signal QADSEL and inverts it. The inverted inverter 94 is activated when the self-recovery mode signal QADSEL is at a level, and reverses the inversion of the reset U address signal / QAD &lt; 0: 11 &gt; and then the inverse of the output signal RAD &lt; 0: 11 &gt; Phaser 93; and when 29 326 \ Patent Specification (Supplement) 92-〇2 \ 91133601.doc 579519 Self-recovery mode signal QADS EL is activated at L level, the output signal Rad & lt is output after inverting the output of inverter 91 ; 0: 11 &gt; The self-recovery mode signal QADSEL is a signal that becomes a high level during the self-recovery mode, and is generated according to the control circuit 24. · Address selection circuit, when the self-recovery mode signal QADSEL is set to the right position · The column address signal / QAD &lt; 0: 1 1 &gt; is reversed as the fg number RAD &lt; 0: 11 &gt; To output. On the other hand, the address selection circuit uses the column address signal $ RA &lt; 0: 1 1 &gt; as the signal rad &lt; 0: 1 when the self-recovery mode signal QADSEL is at L level 1 &gt; to output. The circuits shown in FIG. 10 to FIG. 12 are circuits included in the series of address decoders 26; and in accordance with the use mode of the semiconductor memory device i 1, the upper order bits of the column address correspond to a part Circuits in the space of self-renewal. Fig. 10 is a circuit diagram showing a circuit structure for selecting the upper order bit of the column address according to the usage mode and the next higher order bit. Fig. 11 is a circuit diagram showing a circuit for selecting the uppermost bit of a column address according to the usage mode. Fig. 12 is a circuit diagram showing a circuit configuration for generating a self-renewal stop signal for stopping the self-renewal action. Here, the use mode includes a normal mode in which the semiconductor memory device 11 has a function as a normal single-memory-type semiconductor memory device, and the semiconductor memory device 11 has a double-memory-type semiconductor · memory device. Functional dual unit mode; and semiconductor memory device 11-8K refresh mode when performing 8K refresh operation. Then, in the normal mode, the highest-order bit system of the refresh column address / QAD &lt; 1 1 &gt;; in the two-cell mode, the highest-order bit system of the refresh column address 30 326 \ Patent Specification ( Supplement) 92_02 \ 911336〇l.doc 579519 / QAD &lt; 10 &gt;; In the 8K restoration mode, the restoration [the uppermost bit system of the J address / QAD &lt; 12 &gt;. Referring to FIG. 10, the circuit includes: an inverter 102 receiving a dual-cell mode signal TWIN and inverting it; it is activated when the dual-cell mode signal TWIN is at a level, and it accepts a new column address signal / QAD &lt; 9 &gt; Inverted inverter 1 0 1; Receives 8 K refresh mode signal 8 K and inverts the inverter 104; Activates when 8K refresh mode signal 8K is at Η level, Inverter 103 that accepts the restored column address signal / QAD &lt; 11 &gt; and inverts it; | Inverter 106 that accepts the normal mode signal NORMAL and inverts it; When the normal mode signal NORMAL is a bit Inverter 1105 that is activated on time and that receives the renewed column address signal / QAD <10> and inverts it; Inverter 101 that accepts the output of inverters 101, 103, 105 and inverts it And an inverter 108 which receives the output of the inverter 107 and inverts it, and outputs a signal QAD &lt; 10 &gt;. This circuit is to reset the column address signal / qAD &lt; 9 &gt; when the semiconductor memory device 11 has a function as a semiconductor memory device of a dual memory cell type and the dual cell mode signal TWIN is at a Η φ level. The inverted signal is output as a signal QAD &lt; 10 &gt;. In addition, this circuit is when the semiconductor memory device 11 operates with 8K refresh, and the 8K refresh mode signal 8K is at the Η level, 'the column address signal / qAD &lt; 11: &gt; is inverted The signal is output as a signal QAD &lt; 10 &gt;. Furthermore, when the semiconductor memory device 11 has a function as a normal single memory cell type semiconductor device, and the normal mode signal NORMAL is at a level, the column address signal / QAD &lt; 1 is restored. 〇 &gt; The inverted signal is output as signal QAD &lt; 31 326 \ Patent Specification (Supplement) 92-〇2 \ 91133601.doc 579519 1 ο &gt;. Referring to FIG. 11, the circuit includes: an inverter 1 12 that receives the dual-cell mode signal TWIN and inverts it; it is activated when the dual-cell mode signal TWIN is at the Η level, and it receives a refresh column address signal / QAD & lt 1 0 &gt; Inverted inverter 1 1 1; Receives 8K refresh mode signal 8K and inverts inverter 1 1 4; Activates when 8K refresh mode signal 8K is Η level, and Inverter 113 that receives the restored column address signal / QAD &lt; 12 &gt; and inverts it; Inverter 116 that accepts the normal mode signal NORMAL and inverts it; Activates when the normal mode signal NORMAL is at the Η level, and accepts Invert the column address signal / QAD &lt; 1 1 &gt; and invert the inverter 1 1 5; Inverter 117 that receives the output of inverters 111, 113, 115 and inverts; and accept the inverter The output of the phase inverter 117 is inverted, and an inverter 1 1 8 of the signal QAD &lt; u &gt; is output. This circuit is to reset the column address signal / QAD &lt; 1 0 &gt; when the semiconductor memory device 11 has a function as a dual memory cell type semiconductor memory device and the dual cell mode signal TWIN is at the Η level. The inverted signal is output as a signal QAD &lt; 1 1 &gt;. In addition, when the semiconductor memory device 11 operates at 8K refresh and the 8K refresh mode signal 8K is at the η level, the circuit refreshes the column address signal / QAD &lt; 1 2 &gt; The signal is output as a signal QAD &lt; 11 &gt;. In addition, this circuit is to reset the column address signal / QAD &lt; 1 when the semiconductor memory device 11 has the function as a normal single memory cell type semiconductor memory device and the normal mode signal NORMAL is at a level. 1> The inverted signal is output as a signal qAd &lt; Π &gt;. 32 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc Referring to FIG. 12, the circuit system includes: a NAND gate 123 that accepts the signal SELF_1 MSB, a signal SELFREF, and a signal QAD &lt; 11 &gt;; a reception signal QAD &lt; 11 &gt;;, Q AD &lt; 1 0 &gt; NAND gate 121; Inverter 1 2 2 that accepts the output of NAND gate 1 2 1 and inverts it; Accepts the output of inverter 1 2 2, signal SELFREF and signal SELF -2MSB NAND gate 124; output gate connected to the power node and the output nodes of NAND gates 123, 124; NAND gate 1 25; and accept the output of NAND gate 1 25 and invert, and then output the self-recovery stop signal Inverter of SELF_S TOP 1 2 6. The signal SELF_1MSB is a mode signal corresponding to the mode of self-renewal in the partial self-renewal, and the self-renewal mode is performed only in the memory region where the uppermost bit of the signal of the renewal column is L level. The signal SELF_2MSB is in a partial self-renewal mode, which is in contrast to the mode of self-renewal only in the memory region where the uppermost bit and the next upper-order bit of the column address signal are all L-level. Corresponding mode signal. The signal SELFREF is a signal that becomes a level when performing a partial self-recovery. These signals are generated by the control circuit 24. The self-recovery stop signal SELF_STOP is output to the control circuit 24, and when the self-recovery stop signal SELF-STOP is at the high level, the control circuit 2 4 stops the refresh operation. On the other hand, if in the self-recovery action, and the self-recovery stop signal SELF_STOP is the L-bit criterion control circuit 24, it will instruct the execution of the refresh action. In this circuit, when both the signal SELFREF and the signal SELFJMSB are at the Η level (the signal SELF —2MSB becomes the L level), if the signal qad &lt; 33 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 579519

11 &gt; The output of Η {αι 准 ’ij NAND gate 123 will become L level, and the self-restore stop signal SELF__STOP will become L level. Therefore, in the memory region where the uppermost bit of the refresh column address signal / QAD is L level, the refresh operation is performed. On the other hand, when the signal Q AD &lt; 1 1 &gt; is L · level, the output of the N AND gate 1 2 3 will become the high level, and the self-reset · New stop signal SELF_S TOP will become the high level. Therefore, in the memory region where the uppermost bit of the restoration column address signal / QAD is at the level of a unit, the restoration operation is not performed. When the signals SELFREF and signal SELF-2MSB are both at the Η level (the signal SELF-1MSB becomes the L level), if the signals QAD &lt; 11 &gt; and QAD &lt; 1〇 &gt; are both the Η level, the NAND gate The output of 124 will become the L level, and the self-restore stop signal SELF_STOP will become the L level. Therefore, in the memory region where the uppermost bit of the refresh column address signal / QAD and its next upper bit are both L-level, the refresh operation is performed. On the other hand, when at least one of the signals QAD &lt; 11 &gt; and QAD &lt; 10 &gt; is at the L level, the output of the NAND gate 124 will become the level, and the self-renewal stop signal number SELF # STOP will become the level. quasi. Therefore, in a memory region where neither the uppermost bit of the restoration column address signal / QAD nor its next upper order bit is L level, the restoration operation is not performed. As described above, if the semiconductor memory device according to the third embodiment is · 1 1, even if the uppermost bit of the column address differs depending on the usage mode, it can be selected during partial self-recovery. A part of the refresh operation is performed in a designated memory area, and part of the self-recovery is appropriately performed. .— ~ \ 34 326 \ Patent Specification (Supplement) 92-02 \ 91133601 .doc 579519 The embodiments disclosed this time should be regarded as an example rather than a limitation. The scope of the present invention is not limited to the description of the above-mentioned embodiment, but is in accordance with the scope shown in the scope of patent application, and it covers all changes within the meaning and scope equivalent to the scope of patent application. [Brief Description of the Drawings] FIG. 1 is a schematic block diagram showing the overall configuration of a semiconductor memory device according to the first embodiment. FIG. 2 is a circuit diagram showing the structure of the memory cells arranged in a row and column shape on the billion cell array shown in FIG. 1. FIG. FIG. 3 is a schematic diagram illustrating the structure of a memory area in each group of the memory cell array shown in FIG. 1. FIG. FIG. 4 is a circuit diagram showing a circuit configuration of the RAD &lt; 〇> generating circuit included in the column address decoder shown in FIG. 1. FIG. Fig. 5 is a schematic view showing the structure of a memory region in each group of a memory cell array of a semiconductor memory device of Embodiment 2; Fig. 6 is a schematic block diagram showing the overall configuration of a semiconductor memory device according to a third embodiment. FIG. 7 is a functional block diagram illustrating the function of the reset address generating circuit shown in FIG. 6. FIG. FIG. 8 is a circuit diagram showing a circuit configuration of the refresh address counter shown in FIG. 7. FIG. FIG. 9 is a circuit diagram showing a circuit configuration of an address selection circuit included in the columnar address decoder shown in FIG. 6. FIG. Fig. 10 is a circuit diagram showing a circuit selected by the upper order bit according to the use mode. 35 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 579519 The upper order bit is used. FIG. 11 is a circuit diagram showing a circuit configuration for selecting the uppermost bit according to a use mode. Fig. 12 is a circuit diagram showing a circuit configuration for generating a self-recovery stop signal for stopping the self-recovery action. Fig. 13 is a circuit diagram showing a configuration of memory cells arranged in rows and columns on a memory cell array in a single memory cell type DRAM. Figure I4 is a circuit diagram showing the configuration of memory cells arranged in rows on a memory cell array in a dual memory cell type DRAM. [Description of component symbols] 10, 1 0A '] ί 1 semiconductor memory device 12 control signal terminal 14 address terminal 16 data input / output terminal 18 control signal buffer 20 address buffer 22 output buffer 24 control circuit 26 rank Address decoder 28 Row address decoder 30 I / O control circuit 32 Sense amplifier 34 Memory cell array 36 Restoration control circuit 3 8 Self-recovery control circuit 40 Restoration address generation circuit 5 1 ~ 56 Memory 1¾ Domain 6 1 ~ 6 4,, WL0 ~ WL3 WLn, WLn + 1 word line 7 1 '73 87 12 1, • 1 23 ~ 1 25 NAND 72, 7 4 inverter 77 '11 0 cell board 8 1 ~ 8 6, 88, '9 1 ~ 94 101 ~ 108, 1 1 1 ~ 118, 122% 126 Reverse phase 326 \ Patent specification (Supplement) 92-02 \ 91133601.doc 36 579519 100, 100A, 100B, 340 ~ 343 memory unit 4 0 1 ～ 4 1 2 Reset address counters NO ～ N3, N 1 0 1 ～ N1 03 Ν channel MOS CO ～ C3 、 C101 to C 1 03 capacitor BL, / BL bit line pair / CS chip selection signal / RAS column address strobe signal / CAS row address strobe signal / WE write enable signal A 0 to A n address signal BAO, BA1 group address signals DQO to DQi data IDQ internal data RAD &lt; 0: n &gt;, / R AD &lt; 0: η &gt; signal CA &lt; 0: n &gt;, / CA &lt; 0: η &gt; Row address signal RA &lt; 0: n &gt;, / RA &lt; 0: η> Column address signal TWIN, / TWIN dual unit mode signal / QAD &lt; 0: n &gt; Restore column address signal QCU Recovery signal QADSEL Self-recovery mode signal SELF__STOP Self-recovery stop signal NORMAL Normal mode signal

326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 37

Claims (1)

Pick up and apply for a patent to give up: 1. A semiconductor memory device comprising: an array of billions of cells, including a plurality of memory cells arranged in rows and columns; a plurality of word lines arranged in a column direction; a plurality of word lines arranged in a row direction A bit line pair; and a decoder, respectively, according to the address signal specified by each of the plurality of memory cells, selecting a word line and a special word line from the plurality of word lines and the bit line pairs. The specified bit line pair; where, when two 'memory units are used to store the dual unit mode signal for 1 bit of memory information represented by the binary information, the decoder will choose to use The word line and bit line pair for activation of the two memory cells, and the two memory cells store the memory data and the inverted data of the memory data, respectively. 2. For example, the semiconductor memory device in the scope of patent application, wherein the decoder generates an internal column address signal for selecting the specially designated word line according to the address signal. When the dual cell mode signal is activated, , At the same time, the first word line at which the logical level of the designated bit of the internal column address signal corresponds to the first logical level and the second word at the logical level of the designated bit corresponding to the second logical level are selected at the same time. line. 3. For the semiconductor memory device in the second scope of the patent application, the above-mentioned designated bit is the lowest-order bit of the above-mentioned internal column address signal, and the above-mentioned decoder will become The highest-order bit of the above-mentioned address signal that is not used is allocated to the above-mentioned internal rank 38 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 579519 The lowest-order bit of the address signal, and the above-mentioned address signal The lowest order bit is allocated to the highest order bit of the internal column address signal. 4. The semiconductor memory device according to item 3 of the scope of patent application, wherein when in the above-mentioned normal operation mode in which the dual-cell mode signal is not activated, the memory capacity is 2xn (n is a natural number) bits, and the word structure is 2xm (m is a natural number) bits. 5 · If the semiconductor memory device in the second item of the patent application scope, it is further equipped with a refresh control circuit for regularly performing a refresh operation in order to maintain the above-mentioned billion-information information; the aforementioned refresh control circuit uses the first refresh mode And a second restoration mode to perform the above-mentioned restoration action, wherein the first restoration mode uses k (k is a natural number) times of restoration action to complete all of the above-mentioned billion-cell array The memory cell is renewed, and the second renewal mode is to perform the renewal of 2 X k times to complete the renewal of all the memory cells included in the memory cell array; the address signal is to select the first The restoration mode selection bits for the first and second restoration modes are included in the uppermost bits; the above-mentioned designated bits are the lowest-order bits of the internal column address signals; and the decoder is the above-mentioned restoration bits. The new mode selection bit is allocated to the lowest order bit of the internal column address signal, and the lowest order bit of the address signal is allocated to the highest order bit of the internal column address signal. 6. The semiconductor memory device according to item 5 of the scope of patent application, wherein, when in the above-mentioned normal operation mode in which the dual-cell mode signal is not activated, the memory of the word memory is 2χη (η is a natural number), and the word It is composed of 2xm (m is from 39 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc 579519 Natural number) bits; and when the above dual unit mode signal is activated, the memory capacity is n bits and the word It is composed of m bits. 7. The semiconductor memory device according to item 丨 of the patent application range, wherein the above-mentioned dual-unit mode signal is input from outside via a designated terminal. 8. If the semiconductor memory device according to item No. of the patent application scope, it further includes a fuse circuit for switching the logic level of the above-mentioned dual-cell mode signal. 9 · If the semiconductor memory device under the scope of the patent application, it is further equipped with a refresh control circuit for periodically performing a refresh operation in order to maintain the above-mentioned memory information; the above-mentioned refresh control circuit is generated to be designated as the above The refresh row address of the memory cell row of the refresh action object; The above refresh row address includes a part of the self-recovery address bit of at least 1 bit, which is based on a part of the area of the memory cell array. The object is used to specify the execution of the refresh operation; the decoder includes a selection circuit that selects at least one of the refresh column addresses from the refresh column address that varies depending on whether the dual-unit Lu mode signal is activated. Part of the self-renewal address bit. 1 · If the semiconductor memory device of item 9 of the patent application scope, wherein the above-mentioned restoration control circuit uses one of the first restoration mode and the second restoration mode · One mode to perform the above-mentioned restoration action, wherein the The first refresh mode uses -k (k is a natural number) refresh operations to complete the refresh of all the memory cells included in the memory cell array, and the second refresh mode uses 2 X k times Renewal action to complete the renewal of all the 40 326 \ patent specifications (supplements) 92-02 \ 91133601.doc 577951.9 billion units contained in the above memory cell array; the above selection circuit is used as the above dual unit mode signal When not activated, once the above-mentioned restoration control circuit executes the above-mentioned restoration operation in the above-mentioned second restoration mode, from the above-mentioned restoration column address corresponding to the above-mentioned second restoration mode, the at least one bit is selected. Partial self-recovery address bit. 41 326 \ Patent Specification (Supplement) 92-02 \ 91133601.doc