JPH05290573A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To increase the function of a memory consisting of a dynamic RAM, etc., and to enhance the performance of a computer, etc., containing the memory. CONSTITUTION:Write enable signals UWEB and LWEB and output enable signals UOEB and LOEB are provided on the dynamic RAM, etc., provided with the data input/output terminals IOO-IOF of the number corresponding to 2 byte of storage data corresponding to each byte of the storage data. Further, Y address buffers YBU and YBL are provided respectively corresponding to each byte of the storage data and column address strobe signals UCASB and LCASB are provided respectively. Thus, the operation mode of the dynamic RAM, etc., is set at every byte and a pipe line mode executing write operation or read operation at every byte by specifying different address successively is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique which is particularly effective when used for a dynamic RAM (random access memory) having a multi-bit structure having a byte control function.

[0002]

2. Description of the Related Art There is a so-called multi-bit dynamic RAM having a number of data input / output terminals corresponding to a plurality of bytes of stored data. These dynamic RA
Some of M have a plurality of write enable signals provided corresponding to each byte, and have a so-called byte control function of controlling each byte by a write enable signal corresponding to a write operation of stored data.

For a dynamic RAM having a byte control function, see, for example, November 1991,
"HM514190, HM5" issued by Hitachi, Ltd.
14190L series data sheet ”.

[0004]

As the performance of computers and the like has increased, and the functions required for storage devices such as dynamic RAMs have diversified, the conventional dynamic RAMs described above have been replaced. It has been clarified by the present inventors that the following problems occur. That is, in the conventional dynamic RAM having the byte control function, the storage data write control can be performed in byte units, but the operation mode as the dynamic RAM is unified to either the write mode or the read mode. It is not possible to set the operation mode independently for each. For this reason, it is not possible to construct a storage device that can meet various needs, and this limits the high performance of computers and the like.

An object of the present invention is to provide a semiconductor memory device such as a dynamic RAM having a new function. Another object of the present invention is a dynamic RAM.
It is intended to increase the functionality of a storage device including a storage device and to improve the performance of a computer including the storage device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a dynamic type R having a number of data input / output terminals corresponding to a plurality of bytes of stored data
A write enable signal and an output enable signal are provided to the AM and the like, corresponding to each byte of stored data that can be simultaneously input and output. Further, for example, a Y address buffer is provided corresponding to each byte of storage data that can be input and output at the same time, and a column address strobe signal is provided corresponding to these Y address buffers.

[0008]

According to the above means, the operation mode of the dynamic RAM or the like can be set for each byte of stored data which can be input and output at the same time, and the dynamic RA can be set.
It is possible to realize a so-called pipeline mode in which the write or read operation of M or the like is sequentially designated by specifying different addresses and proceeds in byte units. As a result, the storage device including the dynamic RAM is made to have multiple functions,
It is possible to promote high performance of a computer including a storage device.

[0009]

FIG. 1 is a block diagram of a first embodiment of a dynamic RAM to which the present invention is applied. Based on the figure, first, the dynamic type R of this embodiment
An outline of the configuration and operation of the AM and its features will be described. The dynamic RAM of this embodiment constitutes a storage device of a computer. The circuit elements forming each block in FIG. 1 are made of single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique.
It is formed on each semiconductor substrate.

In FIG. 1, the dynamic RAM of this embodiment is not particularly limited, but two memory arrays MARYU arranged so as to occupy most of the semiconductor substrate surface.
And MARYL. These memory arrays are arranged in a grid pattern at a plurality of word lines arranged in the vertical direction in the figure and a plurality of sets of complementary bit lines arranged in the horizontal direction and at intersections of these word lines and complementary bit lines. And a large number of dynamic memory cells.

The word lines forming the memory arrays MARYU and MARYL are the corresponding X address decoder XD.
It is coupled to U and XDL, and is selectively placed in the selected state. X address decoders XDU and XDL have X
Internal address signals X0 to Xi of i + 1 bits are commonly supplied from the address buffer XB. Further, X address signals AX0 to AXi are time-divisionally supplied to one input terminal of the X address buffer XB via address input terminals A0 to Ai, and the other input terminal is supplied from the refresh address counter RFC. Refresh address signals RX0 to RXi are supplied. The X address buffer XB is further supplied with the internal control signal XL from the timing generation circuit TG, and the refresh address counter R
An internal control signal RC is supplied to FC.

The X address decoders XDU and XDL are
An internal control signal XDG (not shown) is selectively activated to decode the internal address signals X0 to Xi and selectively set the corresponding word lines of the memory arrays MARYU and MARYL to the high level selected state. Further, in the normal operation mode, the X address buffer XB fetches and holds the X address signals AX0 to AXi supplied via the address input terminals A0 to Ai in accordance with the internal control signal XL, and at the same time, stores these X address signals. Based on the internal address signals X0 to Xi,
The X address decoders XDU and XDL are supplied. When the dynamic RAM is in the refresh mode, the X address buffer XB takes in the refresh address signals RX0 to RXi supplied from the refresh address counter RFC, and based on these refresh address signals, the internal address signals X0 to Xi. Are formed and supplied to the X address decoders XDU and XDL. The refresh address counter RFC has refresh address signals RX0 to RX according to the internal control signal RC.
Xi is sequentially formed and supplied to the X address buffer XB.

That is, the dynamic RA of this embodiment
In M, the same internal address signal is always supplied to the X address decoders XDU and XDL, and in the memory arrays MARYU and MARYL, the word lines always arranged at the same row address are alternatively selected. Will be things.

Next, the memory arrays MARYU and MAR
The complementary bit lines forming YL are coupled to the corresponding unit circuits of the sense amplifier SAU or SAL, and further, eight pairs of complementary common data lines CD8 * to CDF are selectively formed.
* (Here, for example, the non-inverted common data line CD8 and the inverted common data line CD8B are collectively referred to as the complementary common data line CD.
It is expressed by adding * like 8 *. Also, so-called inverted signals or inverted signal lines that are selectively brought to a low level when they are enabled are indicated by adding B to the end of their names. Further, in this specification, the complementary common data lines and the serial numbers of the data input / output terminals to be described later are represented by hexadecimal numbers, and CDA * to CDF * and IOA to IOF are
CD10 * to CD15 * and IO10 to I respectively
(Corresponding to O15) or CD0 * to CD7 *.

The sense amplifiers SAU and SAL each include a plurality of unit circuits provided corresponding to each complementary bit line of the memory array MARYU or MARYL. Each of these unit circuits includes a unit amplifier circuit formed by cross-coupling a pair of CMOS inverters, and a pair of N-channel type switch MOSFETs (metal oxide semiconductor field effect transistors. In this specification, MOSFETs).
And collectively referred to as an insulated gate field effect transistor). Of these, each unit amplifier circuit is selectively and simultaneously operated in accordance with an internal control signal PA (not shown), and bit lines are connected from a plurality of memory cells coupled to the selected word line of the memory array MARYU or MARYL. The minute read signal output via the amplifier is amplified to be a high level or low level binary read signal.

On the other hand, one of the switch MOSFETs forming each unit circuit of the sense amplifiers SAU and SAL is coupled to the corresponding complementary bit line of the memory array MARYU or MARYL, and the other one is a complementary common data line CD.
8 * to CDF * or CD0 * to CD7 * are sequentially commonly coupled every 8 pairs. These switch MOS
Eight pairs of gates of the FETs are sequentially and commonly connected, and corresponding bit line selection signals are commonly supplied from the Y address decoder YDU or YDL. As a result, each switch MO
The SFETs are selectively turned on by eight pairs when the corresponding bit line selection signals are selectively set to the high level, and the corresponding eight pairs of complementary bit lines of the memory array MARYU or MARYL and the complementary common data. Line CD8 * ~ CD
F * or CD0 * to CD7 * are selectively connected.

The Y address decoders YDU and YDL are commonly supplied with i + 1-bit internal address signals Y0 to Yi from the Y address buffer YB. The Y address buffer YB has the address input terminals A0 to A0.
The Y address signals AY0 to AYi are time-divisionally supplied via Ai, and the internal control signal YL is supplied from the timing generation circuit TG.

The Y address decoders YDU and YDL are
The internal address signals Y0 to Yi supplied from the Y address buffer YB are decoded by selectively operating in accordance with an internal control signal YDG (not shown), and the corresponding bit line selection signal is alternatively set to the high level. .. The Y address buffer YB fetches and holds the Y address signals AY0 to AYi supplied via the address input terminals A0 to Ai in accordance with the internal control signal YL and holds the internal address signals Y0 to Y0 based on these Y address signals.
Yi is formed and supplied to the Y address decoders YDU and YDL.

Complementary common data lines CD8 * to which eight complementary bit lines of the memory array MARYU are selectively connected.
The CDF * is coupled to the output terminal of each unit circuit of the write amplifier WAU corresponding to each data line and to the input terminal of each corresponding unit circuit of the main amplifier MAU. The write amplifier WAU includes eight unit circuits provided corresponding to the complementary common data lines CD8 * to CDF *. The output terminals of these unit circuits are coupled to the corresponding complementary common data lines CD8 * to CDF *,
The input terminal is coupled to the output terminal of each unit circuit of the corresponding data input buffer DIBU. The input terminal of each unit circuit of the data input buffer DIBU is coupled to the corresponding data input / output terminal IO8-IOF.
An internal control signal WPU is commonly supplied from the timing generation circuit TG to each unit circuit of the write amplifier WAU.

Each unit circuit of the data input buffer DIBU takes in and holds write data supplied via the data input / output terminals IO8 to IOF according to an internal control signal DLU (not shown), and each unit of each write amplifier WAU. Signal to the circuit. Light amplifier W
The respective unit circuits of the AU are selectively and simultaneously activated by the internal control signal WPU being set to the high level, and predetermined based on the write data transmitted from the corresponding unit circuits of the data input buffer DIBU. Of the complementary common data lines CD8 * to CDF
It supplies to the selected eight memory cells of the memory array MARYU via *.

On the other hand, the main amplifier MAU has eight unit circuits provided corresponding to the complementary common data lines CD8 * to CDF *. The input terminals of these unit circuits are coupled to the corresponding complementary common data lines CD8 * to CDF *, and the output terminals thereof are coupled to the input terminals of the respective unit circuits of the corresponding data output buffer DOBU.
The output terminal of each unit circuit of the data output buffer DOBU is coupled to the corresponding data input / output terminal IO8-IOF. In each unit circuit of the data output buffer DOBU,
The internal control signal OCU is commonly supplied from the timing generation circuit TG.

Each unit circuit of the main amplifier MAU further amplifies a binary read signal output from the selected eight memory cells of the memory array MARYU via the corresponding complementary common data lines CD8 * to CDF *. , To the respective unit circuits of the respective data output buffers DOBU. Each unit circuit of the data output buffer DOBU is brought into an active state selectively and simultaneously by setting the internal control signal OCU to a high level, and corresponds to read data transmitted from each unit circuit of each main amplifier MAU. The data is output via the data input / output terminals IO8 to IOF.

Similarly, a complementary common data line C to which eight pairs of complementary bit lines of the memory array MARYL are selectively connected.
D0 * to CD7 * are coupled to the output terminals of the respective unit circuits of the write amplifier WAL corresponding to the respective data lines and also to the input terminals of the respective corresponding unit circuits of the main amplifier MAL. The write amplifier WAL includes eight unit circuits provided corresponding to the complementary common data lines CD0 * to CD7 *. The output terminals of these unit circuits are
It is coupled to the corresponding complementary common data lines CD0 * to CD7 *, and its input terminal is connected to each data input buffer DIB.
It is coupled to the output terminal of each L unit circuit. The input terminals of each unit circuit of the data input buffer DIBL are coupled to the corresponding data input / output terminals IO0 to IO7. Each unit circuit of the write amplifier WAL has a timing generation circuit TG.
The internal control signal WPL is supplied in common.

Each unit circuit of the data input buffer DIBL fetches and holds the write data supplied via the data input / output terminals IO0 to IO7 in accordance with an internal control signal DLL (not shown), and each unit of each write amplifier WAL. Signal to the circuit. Light amplifier W
The AL unit circuits are selectively and simultaneously activated by the internal control signal WPL being set to the high level, and based on the write data transmitted from the unit circuits of the respective data input buffers DIBL. Forming a predetermined complementary write signal, and corresponding complementary common data lines CD0 * to CD7
The data is supplied to the selected eight memory cells of the memory array MARYL via *.

On the other hand, the main amplifier MAL has eight unit circuits provided corresponding to the complementary common data lines CD0 * to CD7 *. The input terminals of these unit circuits are coupled to the corresponding complementary common data lines CD0 * to CD7 *, and the output terminals thereof are coupled to the input terminals of each unit circuit of each data output buffer DOBL. The output terminals of each unit circuit of the data output buffer DOBL are coupled to the corresponding data input / output terminals IO0 to IO7. An internal control signal OCL is commonly supplied from the timing generation circuit TG to each unit circuit of the data output buffer DOBL.

Each unit circuit of the main amplifier MAL further amplifies a binary read signal output from the selected eight memory cells of the memory array MARYL via the corresponding complementary common data lines CD0 * to CD7 *. , To the respective unit circuits of the respective data output buffers DOBL. Each unit circuit of the data output buffer DOBL is selectively and simultaneously operated by the internal control signal OCL being at a high level, and corresponds to the read data transmitted from each unit circuit of each main amplifier MAL. It is transmitted via the data input / output terminals IO0 to IO7.

The timing generation circuit TG is provided with a row address strobe signal RASB, a column address strobe signal CASB, write enable signals (write control signals) UWEB and LWEB and an output enable signal (output control signal) which are externally supplied as activation control signals.
Based on UOEB and LOEB, the above various internal control signals are selectively formed and supplied to each circuit of the dynamic RAM. In this embodiment, the write enable signal UWEB and the output enable signal UOEB are provided corresponding to the upper 8-bit data input / output terminals IO8 to IOF, and the write enable signal LWEB and the output enable signal LOEB are the lower 8-bit data. I / O terminal I
It is provided corresponding to O0 to IO7. Therefore, the timing generation circuit TG sets the internal control signal WPU or OCU to the high level at a predetermined timing when the write enable signal UWEB or the output enable signal UOEB is set to the low level, and the write enable signal LW.
When the EB or the output enable signal LOEB is set to the low level, the internal control signal WPL or OCL is set to the high level at a predetermined timing.

FIGS. 2 and 3 are timing charts of an embodiment of the dynamic RAM of FIG. 1 in the read mode and the write mode, respectively, and FIGS. 4 and 5 show the read / write mode and the write mode, respectively. / A timing diagram of one embodiment in read mode is shown, respectively. Various operation modes of the dynamic RAM of this embodiment will be described in detail with reference to these drawings. Here, all the data input / output terminals IO0 to IO
A mode in which a read operation of stored data is performed via F is called a read mode, and all data IO0 to IOF
The mode in which the stored data is written via the memory is called a write mode. Further, the read operation of the stored data is performed through the data input / output terminals IO8 to IOF of the upper 8 bits, and the data input / output terminals IO0 to IO0 of the lower 8 bits are performed.
The mode in which the storage data write operation is performed via IO7 is referred to as a read / write mode. Conversely, the storage data write operation is performed via the upper 8-bit data input / output terminals IO8 to IOF and the lower 8-bit data is written. A mode in which a read operation of stored data is performed via the input / output terminals IO0 to IO7 is called a write / read mode.

In FIG. 2, the dynamic RAM is
When the row address strobe signal RASB is changed from the high level to the low level, it is brought into the selected state and the word line selecting operation is started. Further, the column address strobe signal CASB is changed from the high level to the low level to start the operation of selecting the complementary bit lines, and the substantial write operation or read operation is executed. When the dynamic RAM is set to the read mode, the write enable signals UWEB and LWEB are both kept at the high level, and the output enable signals UOEB and LOEB are set.
Both are changed from the high level to the low level prior to the change of the column address strobe signal CASB to the low level. The X address signals AX0 to AXi, that is, the internal address signals X0 to Xi are supplied to the address input terminals A0 to Ai so as to include the falling edges of the row address strobe signal RASB, and the falling edges of the column address strobe signal CASB are supplied. Inclusive form Y
Address signals AY0 to AYi, that is, internal address signal Y
0 to Yi are supplied.

In the dynamic RAM, the internal control signal XL is set to the high level in response to the low level change of the row address strobe signal RASB, and the address input terminal A
0 to Ai supplied X address signals AX0 to AX
Xi is taken into the X address buffer XB and becomes internal address signals X0 to Xi. In addition, the internal control signal XDG (not shown) is set to the high level with a slight delay, and the operation of selecting the word line by the X address decoders XDU and XDL is started. Then, the memory arrays MARYU and M
The minute read signals of the plurality of memory cells coupled to the selected word line of ARYL are read onto the corresponding complementary bit lines. Then, an internal control signal PA (not shown)
Is set to a high level, and the sense amplifiers SAU and SAL amplify the minute read signals.

When the column address strobe signal CASB is changed from the high level to the low level, in the dynamic RAM, the internal control signal YL is set to the high level and is supplied through the address input terminals A0 to Ai.
Address signals AY0 to AYi are Y address buffers YB
Are taken into the internal address signals Y0 to Yi.
The internal control signal YDG (not shown) is set to the high level with a slight delay, and the Y address decoders YDU and YDL
The complementary bit line selecting operation is started by. And
The binary read signal of the selected memory cell is sufficiently amplified by the main amplifiers MAU and MAL. afterwards,
The internal control signals OCU and OCL are set to a high level at a predetermined timing, and the data output buffers DOBU and DOBU
Data input / output terminals IO8 to IOF and IO from BL
Read data DO8 to DOF and DO0 to DO7 are simultaneously output via 0 to IO7.

The dynamic RAM of this embodiment
Then, as shown in FIG. 2 by adding (a) or (b), the output enable signal UOEB or LOEB is kept at the high level to specify the read operation of only the lower 8 bits or the upper 8 bits. can do.

On the other hand, when the dynamic RAM is in the write mode, the write enable signals UWEB and L
As shown in FIG. 3, WEB is changed from the high level to the low level before the column address strobe signal CASB is changed to the low level, and the output enable signals UOEB and LOEB are both kept at the high level. Data input / output terminals IO8 to IOF and I
The column address strobe signal CA is supplied to O0 to IO7.
Before the SB low level change, the write data DI
8 to DIF and DI0 to DI7 are supplied respectively.

In the dynamic RAM, the X address signals AX0 to AXi are taken into the X address buffer XB in response to the low level change of the row address strobe signal RASB, and the word line selecting operation is started. Also,
In response to the low level change of the column address strobe signal CASB, the Y address signals AY0 to AYi are taken into the Y address buffer YB, the complementary bit line selecting operation is started, and the internal control signal DLU (not shown) is also supplied.
And DLL are set to high level, and write data DI8
.About.DIF and DI0 to DI7 are loaded into the data input buffers DIBU and DIBL, respectively. Then, the complementary bit line selecting operation is completed. After that, the internal control signals WPU and WPL are set to the high level at a predetermined timing, and the write amplifiers WAU and WAL are brought into the operating state. This allows the memory arrays MARYU and M
Write data DI8 to DIF and DI0 to D are written to a total of 16 memory cells selected in ARYL.
I7 is written all at once.

The dynamic RAM of this embodiment
Then, as shown in FIG. 3 with (c) or (d), the write enable signal UWEB or LWEB is kept at the high level to specify the write operation of only the lower 8 bits or the upper 8 bits. can do.

Next, when the dynamic RAM is set to the read / write mode, as shown in FIG. 4, the write enable signal UWEB and the output enable signal LO are set.
Both EB are kept at the high level, and the write enable signal LWEB and the output enable signal UOEB are
The column address strobe signal CASB is changed from the high level to the low level prior to the change of the low level.
Write data DI1 to DI7 are supplied to the data input / output terminals IO0 to IO7 so as to include the falling edges of the column address strobe signal CASB.

In the dynamic RAM, the X address signals AX0 to AXi are taken into the X address buffer XB in response to the low level change of the row address strobe signal RASB, and the word line selecting operation is started. Also,
In response to the low level change of the column address strobe signal CASB, the Y address signals AY0 to AYi are fetched into the Y address buffer YB, the complementary bit line selecting operation is started, and an internal control signal DLL (not shown) is supplied.
Is set to a high level, and the write data DI0 to DI7 are taken into the data input buffer DIBL. And
Completion of complementary bit line selection operation and main amplifier MA
The internal control signals OCU and WPL are set to the high level at a predetermined timing when the amplifying operation of U ends. As a result, the data output buffer DOBU is activated in response to the high level of the internal control signal OCU, and the memory array M
The read data DO8 to DOF of the eight selected memory cells of ARYU are sent from the data output buffer DOBU via the data input / output terminals IO8 to IOF.
Further, the write amplifier WAL is activated in response to the high level of the internal control signal WPL, and the data input / output terminal IO
Write data DI0 input through 0 to IO7
DI7 is connected to the memory array M via the write amplifier WAL.
It is written into the selected eight memory cells of ARYL.

On the other hand, when the dynamic RAM is set to the write / read mode, as shown in FIG. 5, the write enable signal LWEB and the output enable signal UO.
Both EB are kept at the high level, and the write enable signal UWEB and the output enable signal LOEB are
The column address strobe signal CASB is changed from the high level to the low level prior to the change of the low level.
Write data DI8 to DIF are supplied to the data input / output terminals IO8 to IOF in such a manner as to include the falling edge of the column address strobe signal CASB.

In the dynamic RAM, the X address signals AX0 to AXi are taken into the X address buffer XB in response to the low level change of the row address strobe signal RASB, and the word line selecting operation is started. Also,
In response to the low level change of the column address strobe signal CASB, the Y address signals AY0 to AYi are taken into the Y address buffer YB, the complementary bit line selecting operation is started, and the internal control signal DLU (not shown) is also supplied.
Is set to a high level, and the write data DI8 to DIF are fetched in the data input buffer DIBU. And
Completion of complementary bit line selection operation and main amplifier MA
The internal control signals WPU and OCL are set to the high level at a predetermined timing when the L amplifying operation ends. As a result, the write amplifier WAU is activated in response to the high level of the internal control signal WPU, and the data input / output terminal IO8
~ Write data DI8 ~ D input via IOF
The IF transfers the memory array MA via the write amplifier WAU.
It is written into the selected eight memory cells of RYU.
Further, the data output buffer DOBL is activated in response to the high level of the internal control signal OCL, and the read data DO0 to DO7 of the selected eight memory cells of the memory array MARYL are input / output from the data output buffer DOBL. It is sent out via the terminals IO0 to IO7.

As described above, the dynamic RAM of this embodiment has a total of 16 bytes corresponding to 2 bytes of stored data.
Data input / output terminals IO0 to IOF are provided, data input buffers DIBU and DIBL, data output buffers DOBU and DOBL, write amplifiers WAU and WAL.
In addition, main amplifiers MAU and MAL each include a total of 16 unit circuits provided corresponding to these data input / output terminals. The dynamic RAM is provided with write enable signals UWEB and LWEB and outputs corresponding to each byte of storage data supplied simultaneously through the data input / output terminals IO8 to IOF and IO0 to IO7, that is, these data input / output terminals. It comprises enable signals UOEB and LOEB. However, the operation mode of the dynamic RAM of this embodiment is independently set for each byte by these start control signals, and the write operation of the stored data by the write amplifiers WAU and WAL and the data output buffer DOBU.
, And the output operation of the stored data by DOBL can be selectively executed simultaneously for each byte. as a result,
It is possible to increase the functionality of a storage device including a dynamic RAM and promote high performance of a computer or the like.

FIG. 6 shows a block diagram of a second embodiment of a dynamic RAM to which the present invention is applied. 7 to 12 show the same address read mode, the pipeline read mode, the same address write mode, the pipeline write mode, the pipeline read modify write mode, and the pipeline read write mode of the dynamic RAM of FIG. Timing diagrams for one embodiment are shown respectively. Based on these figures, the outline and characteristics of the configuration and operation of the dynamic RAM of this embodiment will be described. Since the dynamic RAM of this embodiment basically follows the embodiment of FIGS. 1 to 5,
The description will be added only to the different parts.

In FIG. 6, the dynamic RAM of this embodiment corresponds to the Y address decoder YDU, that is, the Y address buffer YBU provided corresponding to the memory array MARYU, and the Y address decoder YDL, that is, the memory array MARYL. The Y address buffer YBL is provided. Among them, the Y address buffer YBU supplies the Y address signals AYU0 to AYUi, which are time-divisionally supplied via the address input terminals A0 to Ai, with the internal control signal Y supplied from the timing generation circuit TG.
Take in and hold according to LU,
Internal address signals YU0 to YUi based on the address signal
Are formed and supplied to the Y address decoder YDU. The Y address buffer YBL has an address input terminal A
The Y address signals AYL0 to AYLi, which are time-divisionally supplied via 0 to Ai, are fetched and held in accordance with the internal control signal YLL supplied from the timing generation circuit TG, and the internal address is based on these Y address signals. The signals YL0 to YLi are formed and supplied to the Y address decoder YDL.

In this embodiment, the column address strobe signal serving as the activation control signal is the column address strobe signal UCASB provided corresponding to the upper data input / output terminals IO8 to IOF and the lower data input / output terminals IO0 to IO7. Column address strobe signal LCASB provided corresponding to The timing generation circuit TG uses the column address strobe signal UCASB.
To generate the internal control signal YLU, and to receive the low level change of the column address strobe signal LCASB to form the internal control signal YLL.
As a result, in the dynamic RAM of this embodiment, the Y address signal supplied via the address input terminals A0 to Ai can be selectively fetched into the two address holding means, that is, the Y address buffers YBU and YBL. Memory cells of different column addresses can be selected from the memory arrays MARYU and MARYL. Further, by intentionally shifting the timings at which the column address strobe signals UCASB and LCASB are changed to the low level, the input or output operation of the storage data in each byte can be executed in a pipeline manner.

When the dynamic RAM is set to the same address read mode, the column address strobe signals UCASB and LCASB are as shown in FIG.
Almost at the same time, the high level is changed to the low level. Further, the write enable signals UWEB and LWEB are both kept at the high level, and the output enable signal UO
Both EB and LOEB are changed from the high level to the low level prior to the low level changes of the column address strobe signals UCASB and LCASB. The address input terminals A0 to Ai include the X address signals AX0 to AXi, that is, the internal address signals X0 to X in a form including the falling edge of the row address strobe signal RASB.
i is supplied to the column address strobe signal UCAS
Y including the falling edges of B and LCASB
Address signals AY0 to AYi, that is, internal address signals Y0 to Yi are supplied.

In the dynamic RAM, the X address signals AX0 to AXi are taken into the X address buffer XB in response to the low level change of the row address strobe signal RASB, and the word line selecting operation is started. Also,
Column address strobe signals UCASB and LCAS
In response to the low level change of B, the internal control signals YLU and Y
LL is set to a high level, and Y address signals AY0 to AY
i is simultaneously fetched into the Y address buffers YBU and YBL. Then, after a little delay, the internal control signals OCU and OCL are set to the high level, and the data output buffer DOB
U and DOBL are activated. As a result, FIG.
The read operation similar to that of the read mode is performed, and the read data DO8 to DOF and DO0 to DO7 of a total of 16 memory cells arranged at the same column address of the memory arrays MARYU and MARYL are used as the data output buffers DOBU and DOBL. From the data input / output terminals IO8 to IOF and IO0 to IO7.

On the other hand, when the dynamic RAM is in the pipeline read mode, the column address strobe signal LCASB changes from the high level to the low level with a delay of a predetermined time from the column address strobe signal UCASB, as shown in FIG. To be done. Further, the address input terminals A0 to Ai include the Y address signal AYU corresponding to the storage data of the upper 8 bits in a form including the falling edge of the column address strobe signal UCASB.
0 to AYUi, that is, internal address signals YU0 to YUi
Is supplied to the column address strobe signal LCASB.
The Y address signals AYL0 to AYLi corresponding to the storage data of the lower 8 bits, that is, the internal address signals YL0 to YLi are supplied so as to include the falling edge of

In the dynamic RAM, the X address signals AX0 to AXi are taken into the X address buffer XB in response to the low level change of the row address strobe signal RASB, and the word line selecting operation is started. Also,
The Y address signals AYU0 to AYUi are taken into the Y address buffer YBU in response to the low level change of the column address strobe signal UCASB, and the Y address signals AYL0 to AYLi are changed into the Y address buffer Y in response to the low level change of the column address strobe signal LCASB.
It is taken into BL. Then, the internal control signal OCU is set to a high level at a predetermined timing when the amplification operation of the read signal by the main amplifier MAU ends, and the internal control signal OCL goes high at a predetermined timing when the amplification operation of the read signal performed by the main amplifier MAL ends. It is a level. Accordingly, the data output buffers DOBU and DO
BL is sequentially operated with a predetermined time lag, and the data input / output terminals IO8 to IOF and IO0 to IO7 have read data DO8 to DOF and DO0 to DO7 of the selected eight memory cells of the memory arrays MARYU and MARYL. Are sequentially sent in a pipeline manner.

Next, when the dynamic RAM is set to the same address write mode, the column address strobe signals UCASB and LCASB are changed from the high level to the low level almost at the same time as shown in FIG. The write enable signals UWEB and LWEB are changed from the high level to the low level prior to the change of the column address strobe signals UCASB and LCASB to the low level, and the output enable signals UOEB and L
OEB remains high level. The row address strobe signal RASB is applied to the address input terminals A0 to Ai.
X address signal AX including the falling edge of
0 to AXi, that is, the internal address signals X0 to Xi are supplied, and the column address strobe signals UCASB and L are supplied.
The Y address signals AY0 to AYi, that is, the internal address signals Y0 to Y including the falling edge of CASB.
i is supplied. Further, the data input / output terminals IO8 to IO
Write data DI8 to DIF and DI0 to DI7 are supplied to F and IO0 to IO7 in a form including the falling edges of the column address strobe signals UCASB and LCASB, respectively.

In the dynamic RAM, the X address signals AX0 to AXi are taken into the X address buffer XB in response to the low level change of the row address strobe signal RASB, and the word line selecting operation is started. Also,
Column address strobe signals UCASB and LCAS
In response to the low level change of B, the internal control signals YLU and Y
LL is set to a high level, and Y address signals AY0 to AY
i is fetched into the Y address buffers YBU and YBL. The internal control signals WPU and WPL are then slightly delayed.
Are simultaneously set to the high level, and the write amplifiers WAU and W are
AL is activated. As a result, the same write operation as in the write mode of FIG. 3 is performed, and the memory array MA
Write data DI8 to DIF and DI0 to DI7 are simultaneously written to a total of 16 memory cells arranged at the same column address of RYU and MARYL.

On the other hand, when the dynamic RAM is set to the pipeline write mode, the column address strobe signal LCASB changes from the high level to the low level with a delay of the column address strobe signal UCASB by a predetermined time as shown in FIG. To be done. Further, the address input terminals A0 to Ai include the Y address signal AY corresponding to the 8-bit storage data in a form including the falling edge of the column address strobe signal UCASB.
U0 to AYUi are supplied, and the Y address signal AYL corresponding to the storage data of the lower 8 bits in a form including the falling edge of the column address strobe signal LCASB.
0 to AYLi is supplied. Data input / output terminal IO8 ~
The column address strobe signal UCASB is included in the IOF.
The upper 8-bit write data DI8 to DIF is supplied in a form including the falling edge of the column address, and the lower 8-bit write data DI0 to DI7 is supplied in the form including the falling edge of the column address strobe signal LCASB.

In the dynamic RAM, the X address signals AX0 to AXi are taken into the X address buffer XB in response to the low level change of the row address strobe signal RASB, and the word line selecting operation is started. Also,
The Y address signals AYU0 to AYUi are taken into the Y address buffer YBU in response to the low level change of the column address strobe signal UCASB, and the Y address signals AYL0 to AYLi are changed into the Y address buffer Y in response to the low level change of the column address strobe signal LCASB.
It is taken into BL. Then, the Y address decoder YD
The internal control signal WPU is set to a high level at the timing when the complementary bit line selecting operation by U is completed, and the internal control signal WPL is set at a high level at the timing when the complementary bit line selecting operation by the Y address decoder YDL is completed. As a result, the write amplifiers WAU and WAL are sequentially operated with a predetermined time difference, and the memory array MA
Write data DI8 to DIF and DI0 to DI are stored in the selected eight memory cells of RYU and MARYL.
7 are sequentially written in a pipeline.

Further, the dynamic RA of this embodiment
As shown in FIG. 11, M changes the column address strobe signals UCASB and LCASB to a low level with a predetermined time difference, and the write enable signal UW.
Output enable signal UOE corresponding to EB and LWEB
The read data DO8 to DOF and DO0 to DO7 of the specified address are set to the low level by delaying the low level changes of B and LOEB by a predetermined time.
New read data DI8 to DIF after reading
In addition, the so-called read-modify-write for writing DI0 to DI7 can be executed in a pipeline.
As shown in 2, it is possible to execute the write mode and the read mode for each byte in an arbitrary combination, and to perform pipeline access at a different address for each byte. As a result, in the computer whose memory device is configured by the dynamic RAM of this embodiment, various access methods can be adopted according to the instruction form being executed, which promotes further high performance of the computer. It will be possible.

As shown in the above embodiment, the present invention constitutes a memory device of a computer and has a multi-bit dynamic RA having a byte control function.
By applying it to M or the like, the following operational effects can be obtained. That is, (1) A write enable signal and an output enable signal corresponding to each byte of stored data that can be simultaneously input or output are provided to a dynamic RAM having a number of data input / output terminals corresponding to a plurality of bytes of stored data. By providing each, the operation mode of dynamic RAM etc.
The effect is that each byte of stored data that can be input or output at the same time can be set independently. (2) In the above item (1), a Y address buffer is provided corresponding to each byte of stored data that can be input or output at the same time, and a column address strobe signal is provided corresponding to these Y address buffers. It is possible to realize a pipeline mode in which different addresses are sequentially designated for writing or reading operations of a type RAM or the like to proceed in byte units. (3) According to the above items (1) and (2), it is possible to obtain the effect that the storage device including the dynamic RAM can be made multifunctional. (4) According to the above item (3), it is possible to obtain the effect that it is possible to promote high performance of a computer including a storage device.

The invention made by the present inventor has been specifically described above based on the embodiments. However, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the memory array is not required to be divided into a plurality of pieces, and may be divided into four or more pieces. If the memory array is not divided, 16 sets of complementary bit lines are simultaneously selected from one memory array and complementary common data lines CD8 * to CDF * and CD0 * to CD are selected.
7 * and write amplifiers WAU and WAL and MAU provided corresponding to these complementary common data lines
And MAL to write enable signals UWEB and LWE
It is sufficient to selectively operate in accordance with B and the output enable signals UOEB and LOEB. In the embodiment of FIG. 6, the Y address buffer serving as the address holding unit is independently
These Y address buffers are provided in FIG.
Share the input buffer IB, as illustrated in FIG.
Address latch circuits LU and LL and drivers DU and D
By providing only L individually, they can be equivalently separated. The write operation and the read operation of the dynamic RAM are performed by, for example, 4 bits or 16 bits of stored data.
The control may be performed for each bit, or when a parity bit is provided, for example, it is possible to control in units of 9 bits. Further, the block configuration of the dynamic RAM is not restricted by these embodiments, and various combinations of the activation control signal and the internal control signal in each operation mode can be adopted.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic type RAM which is the field of application as the background has been described.
The present invention is not limited to this, and can be applied to various memory integrated circuit devices such as static RAMs, single-chip microcomputers incorporating such memory integrated circuit devices, and the like. The present invention can be widely applied to semiconductor memory devices having a multi-bit structure having at least a byte control function.

[0056]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a write enable signal and an output enable signal are provided corresponding to each byte of stored data that can be input or output at the same time in a dynamic RAM or the like having a number of data input / output terminals corresponding to a plurality of bytes of stored data. Further, for example, a Y address buffer is provided corresponding to each byte of stored data that can be input or output at the same time, and a column address strobe signal is provided corresponding to each of these Y address buffers. As a result, the operation mode of the dynamic RAM or the like can be set for each byte of the storage data that can be input or output at the same time, and the write or read operation of the dynamic RAM or the like is advanced in byte units while sequentially specifying different addresses. Pipeline mode can be realized. As a result, dynamic type R
It is possible to increase the functionality of a storage device such as an AM and to improve the performance of a computer including the storage device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a timing diagram showing an example of a read mode of the dynamic RAM of FIG.

FIG. 3 is a timing diagram showing an example of a write mode of the dynamic RAM of FIG.

4 is a timing diagram showing an embodiment of a read / write mode of the dynamic RAM of FIG.

5 is a timing diagram showing an example of a write / read mode of the dynamic RAM of FIG.

FIG. 6 is a block diagram showing a second embodiment of a dynamic RAM to which the present invention is applied.

7 is a timing diagram showing an embodiment of the same address read mode of the dynamic RAM of FIG.

8 is a timing diagram showing an example of a pipeline read mode of the dynamic RAM of FIG.

9 is a timing diagram showing an embodiment of the same address write mode of the dynamic RAM of FIG.

10 is a timing diagram showing an example of a pipeline write mode of the dynamic RAM of FIG.

11 is a timing diagram showing an example of a pipeline read modify write mode of the dynamic RAM of FIG.

12 is a timing diagram showing an example of a pipeline read / write mode of the dynamic RAM of FIG.

FIG. 13 is a dynamic RAM to which the present invention is applied.
It is a partial block diagram which shows the 3rd Example of this.

[Explanation of symbols]

DRAM: Dynamic RAM, MARYU, M
ARYL ... memory array, SAU, SAL ... sense amplifier, XDU, XDL ... X address decoder, YDU, YDL ... Y address decoder, XB.
..X address buffers, YB, YBU, YBL ...
Y address buffer, RFC ... Refresh address counter, WAU, WAL ... Write amplifier, MA
U, MAL ... Main amplifier, DIBU, DIBL ...
Data input buffer, DOBU, DOBL ... Data output buffer, TG ... Timing generation circuit. IB ... Input buffer, LU, LL ... Address latch circuit, DU, DL ... Driver.

Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location 6741-5L G11C 11/34 371 K

Claims (6)

[Claims] 1. A plurality of data input / output terminals for inputting / outputting stored data are provided, and a write mode and a read mode can be simultaneously set independently in units of a predetermined number of the data input / output terminals. A characteristic semiconductor memory device. 2. The predetermined number of the data input / output terminals corresponds to one byte of stored data, and the semiconductor memory device has a number of data input / output terminals corresponding to a plurality of bytes of stored data. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises: 3. The semiconductor memory device is provided with a plurality of write control signals and output control signals provided corresponding to each byte of storage data that can be input or output at the same time. Semiconductor memory device. 4. The semiconductor memory device comprises a plurality of address holding means provided corresponding to each byte of storage data that can be input or output at the same time, and a pipeline mode in which a different address can be designated for each byte. 4. The semiconductor memory device according to claim 2, further comprising: 5. The address held by the address holding means is a column address, and the semiconductor memory device provides a column address strobe signal provided corresponding to each byte of storage data that can be input or output at the same time. The semiconductor memory device according to claim 4, comprising: 6. The semiconductor memory device is a dynamic RAM, and the dynamic RAM includes a plurality of memory arrays provided corresponding to respective bytes of storage data that can be input or output at the same time. Claim 1, Claim 2, Claim 3, Claim 4
Alternatively, the semiconductor memory device according to claim 5.