JPH0241106B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device that serially reads or writes a plurality of bits of data bit by bit.

[Technical background of the invention]

In the field of dynamic memory, since Inmos announced a 64K-bit dynamic random access memory with a nibble mode function in 1981, there has been a growing trend toward adopting new serial mode functions. In this mode, by specifying a set of arbitrary addresses, data can be read or written to 2 ^l (l is a natural number) memory cells at high speed.
When l=2, it is called nibble mode, and when l=3, it is called byte mode.

Currently, the circuit system adopted in many dynamic random access memories is that when reading data, when a set of addresses is specified, information from 2 ^l memory cells is led in parallel to the input/output buffer. Then, only the data corresponding to the designated address is outputted through the output buffer. On the other hand, in the case of data writing, data is input through an input buffer to a data line corresponding to a designated address. Serial mode functionality reaches up to these input/output buffers2 ^l
Out of 2 l data, all or part of 2 ^{l data can be converted to serial data and read out without discarding 2 l -1} data as before, or all or part of 2 ^l data can be read out serially. It is a function that rewrites data, and is based on the idea that it is efficient in terms of speed and practicality. Also, as a method to serially read or write the 2 ^l data that has reached the input/output buffer,
A method is adopted in which an l-stage shift register is used, and the output of each stage controls switching transistors inserted between 2 ^l data lines and a data output line or a data input line. That is,
A switching circuit that uses, for example, a column address strobe signal as a synchronizing clock to operate the shift registers in each stage, and is provided between the data line corresponding to a specified address and the data output line and data input line. By sequentially delaying and propagating pulse signals from the shift register outputs input to the transistors, the 2 ^l data lines are successively connected to the data output line and the data input line. In addition, the last stage of the shift register mentioned above is connected to the first stage shift register, forming a loop circuit as a whole, so when the 2 ^l+1st signal is input, it will again correspond to the first specified address. A data line, a data output line, and a data input line are connected.

[Problems with background technology]

By the way, the data read/write mode functions of conventional dynamic random access memories are classified as follows.

(1) Memory that can be used in both normal mode and page mode (2) Memory that can be used in both normal mode and nibble mode (3) Memory that can be used in both normal mode and byte mode What is normal mode? This is the original random access mode, in which data is written or read in units of one memory cell each time a set of column and row addresses is specified. Page mode is a mode in which one memory cell is initially accessed using the same operation as in normal mode, and thereafter memory cells within the same row address can be sequentially accessed by simply specifying a column address.

Conventionally, when integrating such a memory, the selectable mode functions were set by preparing several types of manufacturing masks for forming metal wiring during manufacturing, corresponding to each mode function, and then setting these selectable mode functions. This is achieved by selecting and using masks to make different circuit connections. However, this method has the following drawbacks. First of all, the completed chip has extra circuits that are not actually used after the mode selection, which increases the chip size.
This will become a major obstacle to the effective use of chip area in the future. Furthermore, as the number of mode options increases and various mode selections become possible, the number of unnecessary circuits increases, the chip size increases, and the production cost increases. The second drawback is that from the perspective of wanting to make changes to the chip manufacturing process as far as possible towards the end of the entire process, the process using a mask for forming metal wiring is very late in the process. No, it's not the final process. Therefore, there is still room for shortening production time.

[Purpose of the invention]

This invention was made in consideration of the above circumstances, and its purpose is to significantly reduce production cost and production time when configuring a random access type semiconductor memory device with different data read and write modes. An object of the present invention is to provide a semiconductor memory device that can reduce the amount of energy used.

[Summary of the invention]

According to this invention, switching transistors are inserted between a data line and each of an output buffer and an input buffer, and a plurality of shift registers are connected in cascade in order to control these switching transistors to form a loop circuit. In addition, fuses are provided between the shift registers in each stage to change the data shift path and adjust the overall number of data shifts, and these fuses are selectively blown after the manufacturing process is completed. Accordingly, a semiconductor memory device has been provided that constitutes a random access memory with different data read and write modes.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration when the present invention is implemented in a dynamic random access memory. In the figure, 10 is a memory circuit capable of writing and reading data, which includes a memory cell array 11 having a plurality of dynamic memory cells, a column decoder 12, and a row decoder 13 including a sense amplifier used for reading data. The row decoder 13 in the memory circuit 10 receives data read out from memory cells in the memory cell array 11 and data output from an input buffer (described later).
(2 ^l × 2) data lines I/O ₁ , ₁ , ... to which data to be written to memory cells within are transmitted.
I/O ₂ ^l and ₂ ^l are connected.

20 is an input buffer. This input buffer 20 forms a pair of data Di to be written into the memory cells in the memory cell array 11 from the input data Din, and this write data Di,
Di is supplied to a pair of data input lines 21 and 22.

30 is an output buffer. This output buffer 30 forms output data Dout from read data Do and data read from the memory cell array 11 and transmitted to a pair of data output lines 31 and 32.

The above-mentioned pair of data input lines 21, 22 and the above-mentioned 2 ^l pairs of data lines I/O ₁ , ₁ ,...I/O ₂ ^l , ₂ ^l
There are two MOSFETs 23 between each
Similarly, ^two MOSFETs 33 are inserted between the pair of data output lines ₃₁ , _{32 and} each of the ^2L pairs _of data lines ^.
₁ , 34 ₁ , ...33 ₂ ^l , 34 ₂ ^l are inserted.

Further, in FIG. 1, reference numeral 40 denotes a data shift circuit in which 2 ^l shift registers are connected in cascade to form a loop circuit. This data shift circuit 40
A column address strobe signal CAS is input as a synchronization signal for data shifting, and 2l column address signals A _1c , _1c , ...
A _lc and _lc are input. Further, each shift register in the data shift circuit 40 is provided with a decoder to which l combinations of the 2l column address signals are input. Of these decoders, only the output of the shift register provided with the decoder to which a specific combination of address signals is input is activated, and thereafter, each time the column address strobe signal CAS is input, the output is activated. are sequentially shifted to the subsequent shift register. The output signals φ ₁ to φ ₂ ^l of the shift registers in each stage of the data shift circuit 40 are output from each of the four shift registers.
MOSFET23 ₁ , 24 ₁ , 33 ₁ , 34 ₁ ,...23
₂ ^l , 24 ₂ ^l , 33 ₂ ^l , and 34 ₂ ^l gates are input in parallel, respectively.

FIG. 2 is a circuit diagram specifically showing the data shift circuit 40 in FIG. 1. This data shift circuit 40 receives a column address strobe signal CAS and a signal CAS' whose phase is slightly delayed with respect to this signal CAS in parallel, and
2l column address signals A _1c , _1c , ...A _lc , _lc
It is provided with 21 shift registers 41 ₁ to 41 ₂ ^l to which each of ^l combinations is input. Between these shift registers 41 ₁ - 41 ₂ ^l , fuses 51 ₁ - 51 ^l _2-1 , fuses 52 ₁ - 52 ^l _2-1 , fuses 53 ₁ -
53 ^l _2-1 and fuses 54 ₁ to 54 ^l _2-1
Fuses 50 ₁ to 50 ^l _2-1 each consisting of the following are provided. Among the fuses 50 described above, the fuse 51 is inserted between each shift register 41, and the fuses 52 of all the fuse circuits 50 are inserted in series between the last stage shift register 41 ₂ ^l and the first stage shift register 41 ₁ . There is. Of each of the fuse circuits 50, the fuse 53 is inserted between one end of the fuses 51 and 52, and the fuse 54 is inserted between the other ends of the fuses 51 and 52. Incidentally, these fuses 51 to 54 are made of, for example, polycrystalline noricon.

FIG. 3 is a circuit diagram showing in detail the first stage and the next stage of the shift register 41 in FIG. 2. As shown in the figure, in the first stage shift register 41 ₁ , a precharge pulse φ _PR is input to the gate between the output terminal 61 of the signal φ ₁ and the positive polarity power supply voltage V _DD application point. MOSFET
62 has been inserted. Between the output terminal 61 and the ground voltage application point, l column address signals _A1c to _Alc are respectively input to the gates.
MOSFETs 63 ₁ to 63 _l are inserted in parallel.
These MOSFET62 and 63 are MOSFET63
A decoder 64 is configured in which the MOSFET 62 is a drive MOS and the MOSFET 62 is a load MOS.

Furthermore, in the first stage shift register 41 ₁ ,
The column address strobe signal CAS is input to the drain of the output terminal 61.
The gate of MOSFET65 is connected. In addition, in the first stage shift register 41 ₁ , there are two wires between the V _DD application point and the ground voltage application point.
MOSFETs 66 and 67, 69 and 70, 7
2 and 73, 75 and 76 are connected in series to form a series circuit 6.
8, 71, 74, and 77 are configured. the above
The gates of MOSFETs 66 and 70 are connected to the fuse 5
Connected to the connection point of 2 ₁ and 53 ₁ , and the above MOSFET
The gates of 67 and 69 are connected to the source of the MOSFET 65. Further, the series circuit 68,
MOSFET 8 is connected to the series connection points 78 and 79 of 71.
Gates 0 and 81 are connected to each other. The drains of the MOSFETs 80 and 81 are supplied with the column address strobe signal CAS, and a signal whose phase is slightly delayed from this signal CAS is supplied to each drain of the MOSFETs 80 and 81.
It is connected in parallel to the output terminal of a signal generating circuit 42, which is made up of, for example, a delay circuit and generates CAS'.
In addition, the source of the MOSFET 80 is the MOSFET 80 source.
Connected in parallel to gates 72 and 76, and the above
The source of MOSFET 81 is connected to the gate of MOSFET 75. Furthermore, the above series circuit 7
The series connection point 82 of 7 is connected to the gate of the MOSFET 73, and the series connection point of the series circuit 74 is connected to the output terminal 61.

Also, in the next stage shift register 41 ₁ ,
All the structures are the same except that the gates of the MOSFETs 66 and 70 are connected to the output terminal 61 of the preceding stage shift register 41 ₁ via a fuse 51 ₁ . Note that the MOSFET in Figure 3 is the first MOSFET.
It is assumed that all of the devices shown in the figure are N-channel and enhancement type.

Next, in the apparatus configured as described above, the fuses 51 to 54 of each fuse circuit 50 provided in the data shift circuit 40 are selectively blown out using a laser beam generating means or the like after the apparatus is manufactured. In particular, the data shift paths in the shift registers 41 ₁ to 41 ₂ ^l are changed to adjust the number of data shifts as a whole. For example, the operation when two fuses 53 and 54 of each fuse circuit 50 are blown will be described. At this time, in the data shift circuit 40, the 2 ^l shift registers 41 ₁ to 41 ₂ ^l are connected to the fuse 51,
52, and the data shift circuit forms a 2 ^l- stage loop circuit as a whole.

First, when reading data from memory cells in the memory cell array 11, one column of memory cells in the memory cell array 11 is selected by the decoded output of the column decoder 12 according to the row address signal, and the memory cells are read out in parallel from these memory cells. data is read out. These read data are sensed by a sense amplifier in the row decoder 13 and latched there. The data latched by the sense amplifier is then transferred to the column address signal given to the data shift circuit 40.
_{( 2 l ×} ^_
2) Data lines I/O ₁ , ₁ ,...I/O ₂ ^l ,
Output to I/O ₂ ^l .

Next, for example, if l column address signals input to the first stage shift register 41 ₁ in the data shift circuit 40 are all set to L level, the MOSFET 63 ₁ in the first stage shift register 41 ₁ in FIG. ~63 _l are all turned off. Before this, the MOSFET 62 is turned on for a predetermined period by the precharge pulse φ _PR , and the output terminal 61 is set to H level. Therefore, the column address strobe signal
In the state before CAS is input, only the output _φ1 of this shift register ₄₁₁ is set to H level.
By this output φ ₁ , MOSFET 23 ₁ in FIG.
24 ₁ , 33 ₁ , and 34 ₁ are all turned on.
As a result, the pair of data output lines 31, 32 are connected to the pair of data lines I/O ₁ , ₁ , and the read data outputted in advance to the pair of data lines I/O ₁ , ₁ becomes the pair of data. Output line 3
1 and 32 are transmitted as data Do. Therefore, after this, the data latched in advance in the sense amplifier in the row decoder 13 corresponding to the column address signal input to the shift register ₄₁₁ is output from the output buffer 30.
Output as Dout.

Next, the column address strobe signal CAS is sequentially input to the data shift circuit 40. First, the first signal CAS is input. At this time, the output _φ1 of the first stage shift register ₄₁₁ is at H level,
Since MOSFET65 is on, this signal
CAS is input via this MOSFET 65 to the gates of MOSFETs 67 and 69 in the first stage shift register ₄₁₁ . As a result, both MOSFET6 above
7 and 69 are both turned on. MOSFET
67 is turned on, the series circuit 68
The series connection point 78 of is set to L level, thereby turning off the MOSFET 80. Further, since the MOSFET 80 is turned off, neither of the MOSFETs 72 and 76 are turned on. On the other hand, at this time MOSFET6
Assuming that the output φ ₂ ^l of the final stage shift register 41 ₂ ^l , which is input to the gates of MOSFETs 66 and 70, is at L level, both MOSFETs 66 and 70 are turned off.

As a result, the signal CAS is input and MOSFET69
is turned on, the series connection point 79 of the series circuit 71 is set to H level, and thereby
MOSFET 81 is turned on. After inputting the signal CAS, the signal CAS' is outputted from the signal generating circuit 42 with a slight delay. This signal CAS' is then passed through the MOSFET 81 to the MOSFET
It is input to the gate of MOSFET 75, and after this, it is input to the gate of MOSFET 7.
5 is turned on. When the MOSFET 75 is turned on, the series connection point 82 of the series circuit 77 is set to H level, thereby
MOSFET 73 is set to the on state. Then, the output terminal 61 which had been set to H level until now becomes
It is set to L level by MOSFET 73. That is, the output φ ₁ of the first stage shift register 41 ₁ is initially set to the H level, and after the signal CAS is inputted, the output φ 1 is set to the L level.

On the other hand, before the signal CAS is input to the next stage shift register ₄₁₂ , at least one of the l column address signals is at H level, and any of the MOSFETs ₆₃₁ to _63l is in the on state. has been done. Therefore, even if the MOSFET 62 is previously turned on for a predetermined period by the precharge pulse φ _PR , the signal φ ₂ at the output terminal 61 is held at the L level. This also applies to other shift registers other than the first stage.

Therefore, the MOSFET 65 is turned off, and neither of the MOSFETs 67 and 69 are turned on. Further, since the fuse ₅₁₁ is not blown, the output φ1 of the first stage shift register ₄₁₁ , which is set to H level, is the output _φ1 of the fuse 511.
1 ₁ to the next stage shift register 41 ₂
Input to MOSFET66,70. This turns MOSFET 66 on and the series circuit 6
8 series connection point 78 is set to H level, which further turns on MOSFET 80.
Furthermore, MOSFET 70 is also turned on, and as a result, MOSFET 81 is turned off. In this state, the first signal CAS is input, and after that, when the first signal CAS' is output from the signal generation circuit 42,
This signal CAS′ is turned on.
It is input to the gates of MOSFETs 72 and 76 via MOSFET 80. As a result, in the series circuit 74, the MOSFET 72 is turned on, and the MOSFET 72 is turned on.
73 is turned off, thereby causing the L
The signal φ ₂ at the output terminal 61, which had been held at the level, is brought to the H level.

After the first column address strobe signal CAS is input to the data shift circuit 40, φ ₁ is set to L level as described above, and φ ₂ is then set to H level. As a result, in Figure 1,
Instead of MOSFET23 ₁ , 24 ₁ , 33 ₁ , 34 ₁
Both MOSFETs 23 ₂ , 24 ₂ , 33 ₂ , and 34 ₂ are turned on, and a pair of data input/output lines I/O
The read data outputted in advance to O ₂ , ₂ is outputted to the pair of data output lines 31 , 32 as data Do, 2 .
Communicated as Do. Therefore, after this, the output buffer 30 outputs the data previously latched in the sense amplifier in the row decoder 13 corresponding to the column address signal input to the shift register ₄₁₂ as Dout.

Also the first column address strobe signal
After CAS inputs, the next stage shift register 41 ₂
Then, the MOSFET 65 is turned on, and the output φ ₁ of the first stage shift register 41 ₁ turns off both the MOSFETs 66 and 70 in the next stage shift register 41 ₂ . This state is the first signal
First stage shift register 41 ₁ before CAS input
is equivalent to Therefore, when the signal CAS is input next time, the output _φ2 of the next stage shift register ₄₁₂ becomes L.
be leveled. Here, shift registers 41 ₁ to 41 ₂ ^l in the data shift circuit 40 are connected to each fuse 51.
Since the outputs φ ₁ to φ ₂ ^l in each stage are cascade-connected in multiple stages, the H level state of the outputs φ 1 to φ 2 l in each stage is sequentially shifted toward the final stage in synchronization with the input operation of the signal CAS. As a result, by inputting 2 ^l signals CAS, 2 ^l pairs of data lines I/O ₁ , ₁ ,...
Data outputted in advance to I/O _2l , _2l is sequentially transmitted to a pair of data output lines 31 ^{, 32} ,
As a result, the ^21- bit data latched by the sense amplifier in the row decoder 13 is serially output from the output buffer 30.

By the way, in the data shift circuit 40, the final stage shift register 41 ₂ ^l is coupled to the first stage shift register 41 ₁ via (2 ^l -1) fuses 52 in series, and the whole constitutes a loop circuit. Therefore, when the (2 ^l +1)th signal is input, the output φ ₁ of the first stage shift register 41 ₁ is changed again.
is set to H level and the first data is output again.

In this way, when all the fuses 53 and 54 of the fuse circuit 50 in the data shift circuit 40 are blown, the shift registers 41 ₁ to 41 ₂ ^l of each stage are serially connected, and after this, the signal
By sequentially inputting data to CAS, all ^2l bits of data can be read out cyclically.

By the way, fuse circuit 5 located in the center
When the fuses 51 _{1 l} ^{- 1} and 52 2 l-1 of 0 ₂ ^l-1 and the fuses 53 and 54 of the fuse circuit 50 other than these are blown, the shift registers 41 ₁ to 41 ₂ ^l-1 individually Similarly, a single loop circuit is constructed by shift registers 41 ₂ ^l-1 + ₁ to 41 ₂ ^l . At this time, only one of the loop circuits can shift data according to the specified l column address signals, and 2 ^l-1 data can be shifted by the 2 ^l-1 outputs in the same manner as above. They are read out sequentially by operation. As described above, by selectively blowing out the fuses 51 to 54 in the fuse circuit 50, the data shift path in the data shift circuit 40 is changed, thereby increasing the number of data shifts to 2 ^l and 2 ^l-1. , ...2, 1 and so on.

This changes the number of bits of data that can be serially read out. However, when reading only one bit of data, that is, when reading in normal mode, each fuse 51 to 52 in each fuse circuit 50 is blown, but the same effect can be achieved without blowing any fuses. can bring.

The device of this embodiment can also write data. In this case, the output of the data shift circuit 40 is used in the same way as when reading data.
The MOSFETs 23 ₁ to 23 _l and 24 ₁ to 24 _l are sequentially turned on, and the data input lines 21 and 22 are sequentially connected to the data lines I/O ₁ , ₁ , and I/O ₂ ^l , ₂ ^l , and the input Data for writing from buffer 20
This is done by latching Di, to the sense amplifier in the row decoder 13. Also in this case, the fuses 51 to 54 in the fuse circuit 50
By selectively blowing out the data, the number of data bits that can be serially written can be freely changed.

In this way, according to the above embodiment, by selectively blowing out the fuses 51 to 54 in the fuse circuit 50 using a laser beam generating means or the like after manufacturing the device, the serial mode at the time of reading or writing data can be controlled. That is, the number of bits can be varied over a wide range. Therefore, since there is no need to change the manufacturing process depending on the serial mode, the production time can be significantly reduced.

Further, according to the above embodiment, one data shift circuit 40 is provided without providing a dedicated circuit for each mode such as the normal mode, page mode, nibble mode, etc., and the data shift path within this circuit is changed. Since each mode is realized by doing this, the generation of unused extra circuits can be sufficiently reduced compared to the conventional method. Therefore, the chip size can be reduced and the production cost can be reduced.

Furthermore, the laser beam generating means for selectively blowing out the fuses 51 to 54 in the data shift circuit 40 is applicable in the field of memories having a so-called redundant function in which defective memory cells are replaced with spare memory cells. The existing laser device can be used as is.

Note that this invention is not limited to the above embodiments, and various modifications are possible. For example, in the above embodiment, the case where the present invention is implemented in a dynamic type random access memory has been described, but it is also possible to implement this invention in a static type random access memory having static type memory cells. Needless to say.

〔Effect of the invention〕

As described above, the present invention provides a semiconductor memory device that can significantly reduce production costs and production time when configuring a random access type semiconductor memory device with different data read and write modes. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a dynamic random access memory according to an embodiment of the present invention, and FIG.
This figure is a circuit diagram specifically showing the data shift circuit in FIG. 1, and FIG. 3 is a circuit diagram showing a part of FIG. 2 in detail. 10...Memory circuit, 20...Input buffer,
30...Output buffer, 40...Data shift circuit, I/O...Data input/output line, 21, 22...
Data input line, 31, 33...Data output line, 2
3, 24, 33, 34...MOSFET (data selection means), 41...shift register, 50...fuse circuit, 51-54...fuse.

Claims (1)

[Scope of Claims] 1. A memory circuit for writing and reading data, a plurality of data lines coupled to this memory circuit, and a plurality of data lines for outputting data to be written into the memory circuit to the data lines and from the memory circuit. A data input/output means into which data to be read is input via the data line, a data shift circuit in which a plurality of data shift means are connected in series in multiple stages to form a loop circuit, and each data shift means of the data shift circuit. Depending on the output data,
When reading data, the data appearing on each of the plurality of data lines is sequentially selected and supplied to the data input/output means, and when writing data, the data output from the data input/output means is sequentially selected and each of the plurality of data lines is sequentially selected. A semiconductor memory device comprising: data selection means for supplying data to a data line; and adjustment means for adjusting the number of data shifts in the data shift circuit. 2. The semiconductor memory device according to claim 1, wherein the adjustment means is a fuse circuit provided between each data shift means of the data shift circuit. 3. Each data shift means of the data shift circuit is provided with a decoder to which a combination of multiple bit address signals is input, and each data shift means is input with a column address strobe signal and a signal synchronized therewith as a synchronization signal. According to claim 1, the data shift circuit is configured to sequentially shift the output data of the data shift means to which a specific combination of address signals is input in synchronization with the column address strobe signal. semiconductor storage device.