JPS61217995A - Memory device - Google Patents

Abstract

PURPOSE:To improve a throughput by providing a means for outputting word addresses of a word to be the object of an operation at the same time when writing a data irrespective of a word address of the word storing the data. CONSTITUTION:The writing of a data without using a word address produces a drive signal corresponding to a word performing the writing of the data through an association operation or an operation determining the word for writing the data from the words in which an effective data is not stored. Based on the driving signal, by driving a word line of the word writing the data by the use of a word line driving circuit, the data writing is realized. During writing the data, the word line of the word in which the data is written is without fail driven, so that the word lines of the respective words are connected to terminals designating a generation and the output of the address of an address encoder, thereby the word address of the word in which the data is written is produced and outputted by the address encoder.

Description

[Detailed Description of the Invention] [Summary] In a storage device in which data can be written regardless of the word address of the word storing data, when writing data, the address of the word that is the target of the operation is A means for simultaneously outputting word addresses is provided to improve the input speed.

[Industrial application field]

The present invention does not use a word address (in a storage device that writes and reads two data), when writing data, the word address of the word that is the target of the operation is
This invention relates to a storage device that can output addresses simultaneously.

[Conventional technology]

A storage device that can write data without using word addresses determines the word to be written or read based on the relationship between the stored data and the supplied search data, and then writes or reads the word. There is an associative memory. In this kind of associative memory device,
94525, the associative memory device 1; the data associated with the stored data (index) is stored in a normal RAM (Random Acc
(Ess Memory) Device C: Generally, the RAM device is accessed using the word address of the word in which the index outputted from the associative memory device is stored.

FIG. 6 schematically shows an example of an associative memory device configured using a CAM (content retrieval memory) and a RAM, in which 40 is Oy and an ID (index) section 4 represents the conventional example.
1 and address encoder section 42, 43 is RA
M consists of an address decoder 44 and a data section 45.

In search mode 12, enter the ID in %CAM40, search the ID section 41 in the CAM40, and select the corresponding ID.
(for example, word Φ1), a search result match signal +1 is output, which is input to the address generation/output terminal of the address encoder ÷ 1 of the address encoder section 42, and the output is used as the address of the RAM 43. do. R
In the AM 45, the input address is decoded by the address decoder 44 to select the data section 45, and the selected data section 62 is accessed such as reading and rewriting.

However, none of the conventional content addressable memory devices of this type is equipped with means for outputting the word address of the word to which data is written in the write mode 42 at the same time as the data writing operation. To output a word address, the operation had to be repeated two or more times after the write operation.

Another conventional example of a storage device that can write data without using word addresses is Japanese Patent Application No. 55-1.
51195 (Japanese Unexamined Patent Publication No. 57-74889) As shown in FIG. There are storage devices that include means for writing data into determined words.

The general usage pattern of this type of storage device is also similar to that of the content addressable storage device described above. An example of its configuration is shown in FIG. 4, and the illustrated circuit is for one word, and in reality, the circuit is provided corresponding to each word. In the figure, 1 is a signal line representing a search result from an associative memory cell unit (not shown), and when a corresponding word is selected by a search operation, a ring ``'1# signal is sent to this signal line 1. Given.

A memory circuit 2 has a first set terminal 3, a second set terminal 4, and a reset terminal 5.

An output line 6 of the memory circuit 2 is applied to a selector 7.

The selector 7 selects the signal on the signal line 1 indicating the search result during a search operation of the associative memory device, and selects the signal on the memory circuit output line 6 during a write operation. Reference numeral 8 denotes a multiple selection separation circuit, which selects and specifies one word when one or more words are selected during a search operation and a write operation.

9 is a word line drive circuit, 10 is a word line of an associative memory cell, 11 is a first AND gate, 12 is a second AND gate, 13 is a first control line common to all words, and 14 is a word line for all words. A common second control line 15 is an all-word common set signal line for setting the memory circuit 2 for all words at the same time. In the following description, it is assumed that the word line 10 takes a ring shape 11# during a read operation and a write operation.

The operation is as follows. During the search operation, the selector 7 selects the signal line 1 indicating the search result, and if there are 1 words selected by the search 62, the signal line 1 is connected to a logic line.
1" signal is given, and this signal is sent to the CC multiple selection/separation circuit 8 via the selector 7. When multiple words are selected, the multiple selection separation circuit 8 is connected to the multiple selection separation circuit for other words. In connection 12, one word is selected and instructed, and the word line 10 is driven through the word line drive circuit 9 corresponding to that word, and the word is read out, etc., thereby functioning as an associative memory device. .

Next, an explanation will be given of the operation when initially writing storage information into the associative memory device. First, all word common set signal 15
Logic @1'' is applied to set the memory circuit 2 of all words.At this time, if the selector 7 is set to select the memory circuit output line 6, the multiple selection separation circuit 8 is set for all words. The logic "1" of the memory circuit output line 6 is supplied, and the multiple selection separation circuit 8d2 selects one word from among all the words.In this state, the first control line 13 common to all the words is Logic @1'' is applied to perform a write operation. At this time, only the word line 10 of one word selected by the multiple selection separation circuit 8 takes the logic @1m, and the storage information is written.

In the word to which this writing is performed, the two inputs of the first AND gate 110 both take the logic "1", so the output of the first AND gate also takes the logic "1", and the memory circuit 2
will be reset. As is clear from the above description of the operation, this means that no write operation will be performed on this word from now on unless the storage counter 12 is set. For words that are not written, the first control line 13 is at logic @1#, but the word line 10 is at logic “
01, and the output of the first AND gate 11 is also logic '''
0#, and the state of the memory circuit 2 does not change.

In the above explanation, all the memory circuits for all words at the time of initial writing are set. However, in addition to the initial writing, this also applies to the memory circuits 21 of each word that have been initialized and reset. It is clear that the write operation is performed in exactly the same way even in a mixed state.

However, none of the conventional storage devices of this type is equipped with means for outputting the word address of the word to which data has been written at the same time as the data writing operation; , After the write operation ζ;, the operation had to be repeated multiple times.

[Problem that the invention seeks to solve]

In a conventional storage device as described above, that is, a storage device in which data can be written regardless of the physical location (word address) of a word storing data, write mode 1:'s is used to write data. There is no device that is equipped with a means to output the word address of the written word at the same time as the data is written, and in order to output the word address, the operation must be repeated multiple times after writing the data. There was a need. That is, after the write mode, it was necessary to output the word address of the word in which the data was written in the read mode and access the RAM using that address.

In this way, in the above-mentioned conventional storage devices, the word address of the word to which data has been written must be repeated multiple times after the write operation, and therefore the overall The drawback was that it was not possible to improve throughput.

[Means for Solving the Problems] The present invention provides a storage device 1 in which data can be stored regardless of the word address (@physical position) of a word storing data. The above-mentioned problem is solved by providing means for simultaneously outputting the word address of the word that is the object of the operation when writing data regardless of the word address of the word storing the data. .

[Effect]

In the present invention, when data is written without using a word address, the word address of the word targeted for the operation can be simultaneously outputted as 1:. The output word address can be sent to, for example, a RAM section and accessed in its data section for reading or writing. C: There is no need to repeat the operation multiple times.

〔Example〕

FIG. 1 is a block diagram of a storage device according to a first embodiment of the present invention, which can output a word address at the same time as data is written. Although FIG. 1 shows the case of a two-word configuration, it goes without saying that the present invention can be applied regardless of the number of words.

In FIG. 1, 101 and 102 are storage circuit groups that store data, respectively, and 101 is a word line Φ0.
102 is word line +1. 103, 104 are word+0. These are word lines that are driven when writing data to word +1, and 103 is word line +0 and 104 is word line ◆1.

105 is a word line drive circuit Φ0, and 107 is a word line drive circuit Φ1. 108 is a drive signal 0 that instructs the word line drive circuit +0 to drive the word line +a, and 109 is a drive signal φ1 that instructs the word line drive circuit +1 to drive the word line ÷1. be. In the associative memory device shown in FIG. 3 described in the prior art section, drive signals 108 and 109 are generated based on the relationship between stored data and applied search data.

In FIG. 1, 8, 110 and 111 are address encoders for generating word addresses, and 1
12 indicates the address output generated by the address encoder. 113 and 114 are address encoders Φ0. This is a terminal for instructing address generation and output from encoder Φ1, and word line 10 for each.
3 and word line 104i are knee connected. address·
The encoder implementation means is ROM (Read
0nly Memory ) format is common, but
In the case of a ROM format, terminals 113 and 114 are respectively connected to each word line of the ROM.

What is shown in FIG. 2 is an embodiment in which the present invention is applied to the storage device shown in FIG. 4, which is capable of writing data to a word in which no valid data is stored, as described in the prior art section. . The circuit itself in FIG. 4 is as shown above and will not be described here, but the means (2, 2,
6, 7, 8)≦2 Therefore, a drive signal is generated and the word line 10 of the determined word is driven. word line 1o
is connected to a terminal 115 for instructing the address encoder (indicated as 100 here) to generate and output an address, as in the case of FIG.

The operation of the storage devices of these embodiments will be explained below.

Writing data without using a word address is done through an associative operation or an operation that determines a word to write data from among words that do not store valid data.
Generate a drive signal that is paired with the word to write data,
(2) This can be realized by driving the word line of the word in which data is to be written using a word line driving circuit based on the chain driving signal. Here, the word line drive circuit is an amplifier circuit for driving a large load, and logically, in this case, the drive signal and the word line may be directly connected.

When writing data, the word line of the word to which the data is written is always driven, so as shown in Figure 1 or 2, the word line of each word is used to generate and output the address of the address encoder. It can be seen that the word address of the word in which data is written is generated and output from the address encoder 62 by connecting the specified terminal≦2 and Cs<. Since the word address is generated and output as the word line is driven, the word address of the word into which data is written is output simultaneously with data writing. Although detailed explanation will be omitted here, each block shown in FIGS. 1 and 2 can be realized extremely easily by using current integrated circuit technology.

Although the embodiments have been described above, the present invention is not limited to these examples, and it is clear that various changes can be made within the scope of the claims.

〔Effect of the invention〕

As explained above, the present invention provides the following advantages.

(1) Since the word address of the word in which the data is written is output at the same time as data is written, high throughput can be achieved when using this type of storage device.

(2) As information processing becomes more sophisticated, the range of applications of this type of memory device, associative memory device, is expanding, and the achievement of high throughput is extremely significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of another embodiment, and FIGS. 3 and 4 are diagrams showing the structure of a conventional storage device. 101...Word Φ0 102...Word◆1 103, 104...Word line 105.107...Word line drive circuit 108.109
...Drive signal 110.111...Address encoder 0. Φ1
141...ID section 142...Address encoder section Patent applicant Representative of Nippon Telegraph and Telephone Public Corporation Patent attorney Gobe Tamamushi (2 others)

Claims (1)

[Claims] 1. In a storage device in which data can be written regardless of the word address (physical location of the word) of the word that stores data, the word address of the word that stores data 1. A storage device characterized by comprising means for simultaneously outputting a word address of a word to be subjected to an operation when data is written regardless of whether the data is written. 2. The storage device according to claim 1, wherein the storage device is an associative storage device that determines a word to be written based on the relationship between stored data and search data. Device. 3. The storage device is equipped with means for determining a word in which data is to be written from among words in which no valid data is stored, and writing data in the determined word when writing data. A storage device according to claim 1, characterized in that: 4. The means for simultaneously outputting the word address,
4. A storage device according to claim 1, wherein the word line of each word is connected to a terminal for instructing address generation and output of an address encoder.