JPS63293785A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To simultaneously operate the optional number of semiconductor memories from plural ports without generating a large time delay by driving a competition resolving circuit for selected memories to resolve competition even when only unselected memories are driven. CONSTITUTION:Two dual port memories 10, 20 to be simultaneously driven are respectively provided with MM terminals for selecting a certain memory and a function for inputting/outputting competition resolving signals CONL, CONR in respective memories and a chip selecting signal from the memory not selected by the MM terminal is inputted to the terminals, the inverse of CS1L, the inverse of CS1R, of the selected memory to drive the competition resolving circuit 50. Consequently, data can be simultaneously read out/written from/in two or an optional memory through both ports 30, 40.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that reads and writes to a semiconductor memory having a plurality of ports and a contention resolution circuit.

[Conventional technology]

Conventionally, this type of semiconductor memory device has caused a significant time delay when simultaneously operating any plurality of semiconductor memories having a plurality of ports and a contention resolution circuit for reading and writing.

[Problem that the invention seeks to solve]

In the conventional semiconductor memory device described above, when multiple semiconductor memories having multiple ports and conflict resolution circuits are operated at the same time, each semiconductor memory device independently resolves conflicts using its own conflict resolution circuit. Since the results of contention resolution for semiconductor memories do not always match, there is a drawback that multiple ports cannot operate multiple semiconductor memories at the same time without a significant time delay.

[Means for solving problems]

The semiconductor memory device of the present invention has a plurality of ports and a conflict resolution circuit, and operates an arbitrary number of semiconductor memories that read or write to a storage part simultaneously and irregularly, and a plurality of semiconductor memories at the same time. Therefore, means for selecting a certain semiconductor memory among a plurality of semiconductor memories, means for transmitting the conflict resolution result of the selected semiconductor memory to other semiconductor memories, and only other semiconductor memories that are not selected operate. and means for activating the contention resolution circuit of the selected semiconductor memory.

Furthermore, in order to simultaneously operate a plurality of memories each having a plurality of ports and a conflict resolution circuit, the present invention operates the conflict resolution circuit for one of the memories that operate simultaneously, and operates the conflict resolution circuit for the other memories. The conflict resolution circuit inputs the conflict resolution result of the memory in which it is operating, and resolves the conflict accordingly. For this reason, it has a means for switching between a function that allows the conflict resolution circuit to operate and output its results, and a function that disables the conflict resolution circuit and allows input of other conflict resolution results. In particular, even if only a memory in which the conflict resolution circuit is prohibited is operated, a means is provided for operating the conflict resolution circuit of a memory in which the conflict resolution circuit is enabled.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention, and FIG. 2 shows a port section of a semiconductor memory and a contention resolution circuit in the first embodiment.

In FIG. 1, the first embodiment of the present invention has a semiconductor memory (hereinafter referred to as a dual-port memory) 10°20 having two ports and a conflict resolution circuit; To explain the case of parallel connection, each dual port memory 10.20
is R port 30. CS, C3I, CON, Ilo respectively for the two ports referred to as L ports 40.

It has an Add terminal. Furthermore, each of the dual port memories 10 and 20 has one MM terminal. MM
The terminal is a terminal for selecting the dual port memory in which the conflict resolution circuit 50 operates from among the dual port memories that operate simultaneously, and when the MM terminal is connected to the power supply (Vc c ), the conflict resolution circuit 50 (shown in FIG. 2) operates. Then, conflict resolution result signals C0NR, C0NL f) CONR, CON+1 terminal are output. Further, when this MM terminal is grounded (GND), the operation of the conflict resolution circuit 50 is prohibited and the conflict resolution circuit 50 operates by inputting the conflict resolution result signals CONR and C0NL. In this embodiment, two signals φ are input to the first dual port memory 10, and an inverted signal 4sx between the signals φ is input to the second dual port memory 20.
The conflict resolution circuit 50 selects the dual port memory 10 of
operates to output the CONR signal and C0NL signal. The MM terminal of the second dual port memory 20 is GN.
D, and operates by inputting the C0NL signal and CONR signal. In the R port 30, the C8R terminal for the first dual port memory 10 receives the chip select signal φ.
Enter υ5R. The CS IRR terminal inputs the chip select signal φL5R of the second dual port memory 20, and the CON R terminal outputs the result of the conflict resolution circuit 50. The I/OR terminal is a terminal for inputting and outputting 8-bit data, and the AddR terminal is a terminal for inputting a memory address. CS for the second dual port memory
The R terminal inputs the chip select signal φLSR, and the C3l
R is not connected to anything. The CONR terminal inputs the CONR signal of the first dual port memory 10.

The I/OR terminal performs 8-bit input/output and outputs 8 bits of the first dual port memory 10 to the R port 3.
Allows simultaneous input and output of 0 to 16 bits. A d
dR terminal is a terminal for inputting memory address,
The same address signal as the first dual port memory 10 is input.

In the same way for the L port 40, for the first dual port memory 10, the C', terminal is connected to the chip select signal φ.
The C3IL terminal inputs the chip select signal φLSR of the second dual port memory 20, and the C3IL terminal inputs the chip select signal φLSR of the second dual port memory 20.
The 0NL terminal outputs the result of the conflict resolution circuit 50. I
, /OL terminal inputs and outputs 8-bit data, and
The dL terminal is a terminal for inputting a memory address. As for the second dual port memory 20, the chip select signal φLSR is input to one terminal, and]! ]-1 terminal is not connected to anything, and the C0NL terminal inputs the C0NL signal of the first dual port memory 10.

The l10L terminal performs 8-bit input/output, including the 8-bit data from the first dual port memory 10.
Allows bits to be input and output simultaneously.

The Adat terminal is a terminal for inputting a memory address, and inputs the same signal as the first dual port memory 10.

In the above configuration, the first dual port memory 10
The conflict resolution circuit 50 receives the signal CSL.

C3R, C3IL, C5IR, Addt,, Add8
As a result of conflict resolution, the signal C0NL,
Second dual port memo generating C0NR') 20
G! Operation is enabled by signals C3t, C3R, Addt, AddR, and the first dual port memory 10
The C0NL signal and the C0NR signal are input to give permission for reading and writing to the same port as the conflict resolution result of the first dual port memory 10, and the first dual port memory 10 also reads and writes to the second dual port memory 20. According to the result of the conflict resolution circuit 50 of the first dual port memory 10, reading and writing are also possible through the l10L and l10R terminals.

Further, when reading and writing operations are performed only on the second dual port memory 20 from both ports 30 and 40, specifically, the signal φUsL signal/signal φυ8R is at a high level, and the signal φLSL + signal φLSR is at a low level. This is the case when the following signal is input. The signal φLSL and the signal φLSR are respectively connected to the C3ILL terminal and C3l of the first dual port memory 10.
This input causes the conflict resolution circuit 50 of the first dual port memory 10 to operate and resolve the conflict between the two ports, resulting in a signal C0NL and a signal C0.
The second dual port memory 20 is controlled by outputting NR.

Regarding the two dual-port memories that can operate simultaneously in this way, there is an MM terminal that selects a certain memory, a function that inputs and outputs conflict resolution signals C0NL and C0NR for that memory, and a memory that is not selected by the MM terminal. The chip select signal of the selected memory is
By inputting it to the L and CS IR terminals and operating the conflict resolution circuit 50, it is possible to read and write to two ports or any one port at the same time from both ports 30 and 40.

FIG. 2 shows the specific configuration of this first embodiment.

In FIG. 2, the r5 terminal is input to the memory control (not shown in this figure) of the port 40 and the first AND circuit A1. [The completion IL terminal is connected to the first AND circuit A1
It is connected to the. The output signal of the first AND circuit A1 becomes an operation request signal of the conflict resolution circuit 50. The first 3-state buffer T1 inputs the signal of the CON L terminal,
The output signal is input to the second AND circuit A2. The output control terminal of this buffer T1 is connected to be supplied with an inverted signal of the MM terminal. The second 3-state buffer T2 inputs the output signal of the third 3-state buffer T3 and outputs it to the CON terminal, and its output control terminal is connected so that the signal from the MM terminal is supplied. ing. The third three-state buffer T3 inputs the resultant port output signal of the conflict resolution circuit 50, and its output control terminal is connected so as to be supplied with the signal of the MM terminal. The second AND circuit A2 also inputs the inverted signal of the MM terminal, and also inputs the signal φ, and its output signal is input to the first OR circuit o1. Third AND circuit A3
is connected to input the permission signal for the L port 40 of the conflict resolution circuit 50 and the signal of the MM terminal, and its output is input to the first OR circuit 01. 1st OR
The output signal of the circuit 01 is the permission signal φLE for the memory port.The fourth AND circuit A4 inputs the permission signal for the R port 30 of the conflict resolution circuit 50 and the signal of the MM terminal, and outputs the same. The signal is connected to be input to the second OR circuit 02.The second OR circuit 02 inputs the 5 output signals of the fourth AND circuit A4 and the fifth AND circuit, and outputs the output signal. is used as the enable signal φRE of the port 40 for the memory.The fourth 3-state buffer T4 inputs the output signal of the R port 30 resulting from the conflict resolution circuit 50, and its output signal is input to the fifth 3-state buffer T4. It is connected to be supplied to the input terminal of the state buffer T5, and its output control terminal is connected to the MM terminal.No.
The output signal of the 3-state buffer T6 is input.

The fifth three-state buffer T5 has its output terminal C0N.
It is connected to the R terminal, and its output control terminal is connected to the MM terminal. The sixth 3-state buffer T6 is C0NR
The terminal is connected so that a signal is input thereto, and an inverted signal from the MM terminal is supplied to its output control terminal. 6th AN
The D circuit A6 inputs the signal of the terminal C hole and the terminal ff, and its output signal becomes the operation request signal of the conflict resolution circuit 50.The signal of the CSR terminal is input to the memory control (main function) of the R port. (not shown).

In addition, the conflict resolution circuit 50 includes a report 40 and an R port 30.
A signal φL and a signal φR are respectively input from the input terminals.

Next, the operation of the first embodiment will be explained. In the first embodiment, when the MM terminal is set to Vcc, the first
The 3-state buffer Tl and the sixth 3-state buffer T6 output a high impedance state, and the second AND
Circuit A2. A 5-level signal is output on the fifth AND circuit. As a result, the C0NL and C0NR terminals have
The result of the conflict resolution circuit 50 is output. Further, the permission signal φLETφRE for the memory is output from the conflict resolution circuit 50. When the MM terminal is set to Vcc, the conflict resolution circuit 50 operates according to the input signals of the [5 signal and the CSL signal to execute a memory operation. Furthermore, when the MM terminal is at Vcc and the C1 signal and C3lL signal are input, the memory operation is not executed, but the conflict resolution circuit 50 operates and the C0NL signal and C0N signal are input according to the results.
Outputs R signal. Also, if the MM terminal is GND,
Second 3-state buffer T2. Third 3-state buffer T3. Fifth 3-state buffer T5. The fourth 3-state buffer T4 makes the output high impedance,
The third AND circuit A3 and the fourth AND circuit A4 output low voltage.This causes the CON L terminal, C0
Both NR terminals serve as input terminals and are permission signals for the memory.

The report signal φLE is output by AND logic of the signal input to the C0NL terminal and the signal φL.

Further, the signal φRE of the R port is outputted by AND logic of the signal input to the CON R terminal and the signal φR. As a result, the dual port memory whose MM terminal is connected to GND can perform conflict resolution using the input signals of the C0NL and C0NR terminals.

FIG. 3 shows a second embodiment of the present invention, and FIG. 4 shows a port section of a semiconductor memory and a contention resolution circuit in the second embodiment. In FIG. 3, in this embodiment, the dual port memory 60.70 has terminals CrV, OUT terminal and ff1L OUT terminal which output the conflict resolution result, and a C-NRIN terminal and C0NL which input the signal.
It has an IN terminal. This dual port memory is M
The functions of the input/output terminals are the same as in the first embodiment except for the case where there is no M terminal. The cs, , cst terminals input the chip select signals of the respective ports, and the CS I L.

The C3lR terminal is an input terminal for operating the conflict resolution port 100, and is an input terminal for I/OFL and I10.
The L terminal executes data input/output, and AddR, AddL
The terminal is a terminal for inputting a memory address.

The first dual port memory 60 has both the C0NL IN terminal and the C0NRIN terminal connected to the power supply (V cC). C0NROUT terminal and C0NLOUT
The terminal outputs the conflict resolution result of the first dual port memory. This signal is a low level signal when access is not permitted. The second dual port memory 70 is C0NL of the first dual port memory 60.
The OUT signal is input to the C0NRIN terminal, the OUT signal is input to the C0NLIN terminal, and nothing is connected to the C, OUT, and C0NL OUT terminals.

The operation in the second embodiment is based on the C0NRIN signal and the C0
When both NLIN signals are high, the memories operate according to the conflict resolution results of the respective dual port memories 60, 70.

Thus, in this second embodiment, the first dual port memory 60 always operates according to the conflict resolution result and the resulting C0NROUT signal.

and outputs a low level C0NL OUT signal to ports to which access is not permitted. Further, in the second dual port memory 70, when both the C0NRIN signal input and the C0Nt, IN signal input are at high level,
In other words, when there is no conflict, it operates normally.

When a conflict occurs, the C0NRIN signal input or C0NLI
'When any of the N signal inputs becomes a low level, the output of the enable signal of the conflict resolution circuit 100 is prohibited and the C0NR
IN, C0NL Access to the selected port becomes possible according to the input of IN. The other operations are the same as in the first embodiment, and will therefore be omitted.

Next, the second embodiment will be explained in detail. In FIG. 4, the result output signal of the conflict resolution circuit 100 is sent directly to each port from the C0NROUT terminal,
It is output through the T terminal. The C0Nt, IN input signal is sent to the second AND circuit A2, and the C0NRIN input signal is sent to the fifth AND circuit A2.
is input to the AND circuit A5. The C0NRIN signal, CON, and IN signals are input to the seventh AND circuit A7, and the output thereof is input to the third AND circuit A as in the first embodiment.
3. The inverted signal is input to the fourth AND circuit A4, and the inverted signal is input to the second AND circuit A2. The signal is input to the fifth AND circuit A5. If both the C0NRIN signal and the C0NLIN signal are at high level, the seventh AND circuit A7 outputs a high level, and the second AND circuit A2. Fifth AND circuit A
With the output of 5 set at a low level, the enable signal of the conflict resolution circuit 100 becomes the memory enable signal φLEIφRE. C0NR
When either the IN signal or the C0NLIN signal becomes low level, the output of the seventh AND circuit A7 outputs a low level, and the output of the third AND circuit A3. The output of the fourth AND circuit A4 is set to a low level to inhibit the contention resolution circuit 100 from outputting the permission signal, and it is possible to operate on ports to which access is permitted according to the C0NLIN signal and the C0NRIN signal. Other operations are similar to the first embodiment, but the second embodiment has the advantage that signal input/output is easier than the first embodiment.

In this way, this embodiment selects one of the semiconductor memories that operate simultaneously in a semiconductor memory having a plurality of ports and a conflict resolution circuit, and transmits the conflict resolution result of the selected memory to other memories. The present invention has an original content in which even if only the unselected memory is activated, the operation is performed based on the conflict resolution result of the selected memory.

〔Effect of the invention〕

As explained above, the present invention selects one of the memories that operate simultaneously in a semiconductor memory having a plurality of ports and a conflict resolution circuit, and transmits the conflict resolution result output of the selected memory to the other memory. input to the memory and perform conflict resolution according to the judgment, and even if only the unselected memory operates, conflict resolution is performed by operating the conflict resolution circuit of the selected memory. This has the effect that a semiconductor memory having a port and a contention resolution circuit can be operated simultaneously from an arbitrary number of ports without significant time delay.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a semiconductor memory device according to a first embodiment of the present invention, FIG. 2 is a diagram depicting a port section and a contention resolution circuit in the first embodiment, and FIG. 3 is a diagram showing a semiconductor memory device according to a second embodiment of the present invention. FIG. 4 is a diagram showing a port section and a conflict resolution circuit in the second embodiment. 10.20.60.70...Dual port memory,
30.80...R port, 40.90...S port, 50,100-...Conflict resolution circuit, φUSL+φL+
SR1φLSL+φLSR...Memory chip select signal, 10L, l10R...Data input/output signal, address address...Memory address input signal, C
ON C0Na, lower LotJT', c? 5TROUT
, -・Conflict resolution result output signal, φm + <f'
M...Input signal, Al. A2. A3. A4. A5. A6. A7...AND logic circuit, 01,02/OR logic circuit, Tl, T2°T3.
T4. T5. T6...3 stage buffer circuit, φL
, φR...Conflict resolution circuit input signal, φLE+Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] Semiconductor memory has multiple ports and conflict resolution circuits, and reads or writes to the memory portion at the same time irregularly. Among them, a means for selecting a certain semiconductor memory, a means for transmitting the conflict resolution result of the selected semiconductor memory to other semiconductor memories, and a means for selecting a semiconductor memory even when only other semiconductor memories not selected operate. and means for activating a conflict resolution circuit.