JPH02137194A - Contents address attachable memory - Google Patents

Abstract

PURPOSE:To attain high-speed operation by composing a contents address attachable memory of a memory cell to have the couple of an access transistor, which is connected to a bit line in a column direction, and an access transistor, which is connected to a data line in a row direction, and an exclusive OR circuit to obtain exclusive OR between data on the bit line and the contents of the memory cell. CONSTITUTION:The contents address attachable memory is composed of the memory cell to have the couple of two access transistors of the access transistor 12, which is connected to a bit line 1, and the access transistor 12, which is connected to a data line 11 in the row direction, and an exclusive OR circuit 4 to obtain the exclusive OR between the data on the bit line 1 and the contents of a memory cell 14. Accordingly, an access can be executed from the both bit line 1 and row direction data line 11 to the memory cell. Thus, data to correspond to the retrieving data of respective rows can be easily written and the high-speed operation can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to content addressable memory (hereinafter referred to as rCAM).

[Conventional technology]

A typical conventional CAM cell is shown in FIG. In the figure, 1 is a bit line, 2 is a word line, 3 is a memory cell latch, 4 is an exclusive OR circuit for coincidence detection, and 5 is a coincidence detection line.

FIG. 4 is a block diagram of a CAM using the CAM cell shown in FIG. 3. In the figure, 6 is an external data input terminal, 7 is a CAM cell shown in FIG. 3, 8 is a search data processing circuit,
9 is a write data creation circuit.

Next, the operation will be explained. CAM can be used in various applications including content retrieval; for example, consider an application in which numerical operations are performed in bit series and word parallel. In such applications, data corresponding to the search data of a given row may be written in the same row. In this case, as shown in FIG. 4, it is necessary to send write data from the search data processing circuit 8 to the data input circuit 10 via the write data creation circuit 9.

[Problem to be solved by the invention]

Conventional CAMs are configured in this way, and the processing system for writing data in the same row according to the content of the search data in each row is complex, and it takes time to put the data on bit line 1. , it was difficult to operate at high speed.

The present invention has been made in view of these points, and its purpose is to provide a content addressing system that facilitates the process of writing data corresponding to the search data of each line in the same line and enables high-speed operation. It is possible to obtain memory.

[Means to solve the problem]

In order to solve these problems, the present invention makes the conventional addressable memory cells into dual ports so that data can be written to and read from the bit lines, and the data can be written and read from the bit lines according to the result of the coincidence detection line of each row. In this structure, a data line and an access transistor are added for writing the data.

[Operation] In the content addressable memory according to the present invention, each row -
Data corresponding to the output results of several output lines can be written from the row-direction data line to the memory cells in the same row via the row-direction data line access transistor.

[Embodiment] FIG. 1 is a circuit diagram showing a memory cell constituting an embodiment of a CAM according to the present invention. In the figure, l is a bit line, 2 is a first word line for writing data on bit line l, 3 is a latch for a memory cell, 4 is an exclusive OR circuit for a plurality of configurations, 5 is a coincidence detection line,
11 is a row-direction data line, 12 is an access transistor for the row-direction data line, and 13 is a second word line for writing data on the row-direction data line 11.

FIG. 2 is a block diagram showing an embodiment of a CAM according to the present invention, and shows a CAM to which the memory cell of FIG. 1 is applied. In the figure, 14 is a memory cell shown in FIG. 1, 15 is a search data processing circuit and a write circuit, and the same or corresponding parts as in FIG. 4 are given the same reference numerals.

Next, the operation will be explained. The memory cell in Figure 1 is
In addition to the normal bit line 1, it has a data line 11 extending in the row direction. Therefore, in the configuration shown in FIG. 2, if a search data processing circuit and a write circuit 15 are provided in which a data write circuit corresponding to the search data result is added to the search data processing circuit, the data corresponding to the search result of each row can be written. can be quickly written into memory cells in the same row via the row data line 11 and row data line access transistor 12 without sending the data to the bit line 1.

〔Effect of the invention〕

As explained above, the content-addressable memory according to the present invention includes a set of two access transistors, an access transistor connected to a focus line and an access transistor connected to a row direction data line, data on a bit line, and a memory. By configuring memory cells with an exclusive OR circuit that performs an exclusive OR with the contents of the cell, addressable memory cells can be accessed from both the bit line and the row data line, resulting in high speed performance. This has the effect of providing an addressable memory capable of performing parallel numerical operations.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a memory cell constituting an embodiment of a CAM according to the present invention, FIG. 2 is a block diagram showing an embodiment of a CAM according to the present invention, and FIG. 3 is a circuit diagram showing a memory cell of a conventional CAM. The circuit diagram shown in FIG. 4 is a configuration diagram showing a conventional CAM. 1... Bit line, 2... First word line, 3...
Memory cell latch, 4... Exclusive OR circuit, 5... - number line, 6... Data input terminal,
10... Data input circuit, 11... Row direction data line, 12... Access transistor for row direction data line,
13... Second word line, 14... Memory cell, 1
5... Search data processing circuit and writing circuit.

Claims (1)

[Claims] A set of two access transistors, an access transistor connected to a bit line in the column direction and an access transistor connected to the data line in the row direction, and the data on the bit line and the contents of the memory cell are exclusive ORed. Content addressable memory consisting of memory cells having an exclusive OR circuit.