KR100278283B1 - Content addressable memory device - Google Patents

Abstract

In the present invention, when the normal data is stored using two bit lines, data complementary to each other is used, and when masking, a cell is configured so that the same data can be written. The present invention provides a content addressable memory device that is easy to connect to a memory driven in a configuration. To this end, the present invention provides a data storage unit for storing data input from the outside, and address data input from the outside. A content addressable memory device arranged with a plurality of content addressable cells, each of which has a comparison unit consisting of a plurality of transistors for performing an exclusive OR operation to compare stored data and determine a match. The data of each cell Book, the one side being connected to a first bit line for writing, the first switching transistor gate connected to the word line; A second switching transistor having one side connected to a first read bit line and a gate connected to the word line; A first latch unit connected between the other side of the first switching transistor and the other side of the second switching transistor; A third switching transistor having one side connected to a second read bit line and a gate connected to a word line; A fourth switching transistor having one side connected to a second write bit line and a gate connected to the word line; And a third latch unit connected between the other side of the third switching transistor and the other side of the fourth switching transistor, wherein the comparing unit is connected in series between a matching line and a ground power source, and a gate of the first switching transistor is connected to the first writing transistor. First and second enMOS transistors respectively connected to a storage bit line and a storage node of the first latch unit; And third and fourth enMOS transistors connected in series between the matching line and the ground power source, each having a gate thereof connected to the second writing bit line and a storage node of the second latch unit, respectively.

Description

Content addressable memory device {CONTENT ADDRESSABLE MEMORY DEVICE}

TECHNICAL FIELD The present invention relates to memory devices, and more particularly, to a maskable content addressable memory (hereinafter referred to as CAM) using fixed memory cells.

Such a CAM can be used for applications such as pattern recognition variable length coders. CAM, which is a memory of a conventional content addressing method, is widely used in cache memory, neural networks, coding, and the like.

In this CAM function, since the CAM cell is generally used to find a matched address in comparison with the contents in the data memory to be processed, the CAM cell generally includes a data storage unit 10 for storing data input from the outside, and from the outside. Comparing unit 12 is composed of a plurality of transistors to compare the input address data and the stored data to determine whether a match, and performs an exclusive OR function.

However, such a match operation needs to mask (or don't care) a specific bit depending on the application, and the mask operation can significantly reduce the size of the CAM block. For example, pattern matching is used for a mask of an edge portion or a mask of code redundancy bits shorter than input data in a variable length.

Several maskable CAM cells have been proposed for this function. US patent 5,051,948 uses dynamic cells. However, in this case, there is a disadvantage in that data refresh is required compared to the advantage of small cell size. In contrast, US patent 5,051,949, which uses a fixed cell, uses two cells to store information about a mask in one cell. In such a case, two steps of writing mask data and data to be stored for masking are required, and two word lines cause problems in cell configuration. That is, in order to drive an address of another memory due to the function of the CAM, the height of the memory cell to be driven and the height of the CAM cell in the configuration must be the same. In this case, the cell configuration is difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and when the normal data is stored using two bit lines, the cells are configured so that the same data can be written in the case of masking. Therefore, it is an object of the present invention to provide a content addressable memory device that does not require a step for mask data and is easy to configure a connection with a memory to be driven.

1 is a circuit diagram of a conventional fixed CAM cell.

2 is a circuit diagram of a fixed maskable CAM cell according to an embodiment of the present invention.

The present invention for achieving the above object is composed of a data storage unit for storing the data input from the outside and a plurality of transistors to determine whether a match by comparing the address data and the stored data input from the outside to perform an exclusive logical OR function In the content addressable memory device arrayed with a plurality of content addressable cells each having a comparison unit to perform, wherein the data storage of each of the content addressable cells, one side is connected to the first write bit line A first switching transistor having a gate connected to the word line; A second switching transistor having one side connected to a first read bit line and a gate connected to the word line; A first latch unit connected between the other side of the first switching transistor and the other side of the second switching transistor; A third switching transistor having one side connected to a second read bit line and a gate connected to a word line; A fourth switching transistor having one side connected to a second write bit line and a gate connected to the word line; And a third latch unit connected between the other side of the third switching transistor and the other side of the fourth switching transistor, wherein the comparing unit is connected in series between a matching line and a ground power source, and a gate of the third switching transistor is connected in series. First and second enMOS transistors respectively connected to a first write bit line and a storage node of the first latch unit; A third and fourth enMOS transistor connected in series between the matching line and a ground power source, each of which has its gate connected to the second write bit line and the storage node of the second latch unit, respectively. do.

Referring to the embodiment of the present invention in detail with reference to the accompanying drawings, the proposed mask-enabled fixed CAM cell as shown in Figure 2 is composed of two bit lines, that is, d bit line and r bit line, In the case of d, a d bit line is used, data is read through the r bit line at the read time, and data during the match operation is input through the d bit line.

Because the r-bit line consists of only junction capacitance and parasitic capacitance, it operates at "high" speed, rather than reading using the d-bit line with the gate capacitance present. In this case, the r bit line is an option. When using a single-ended SRAM, the r bit line may be written and read through the dbit line. Using r-bit lines allows writes and reads to run at speeds comparable to normal SRAM speeds.

There are four functions by writing four things. The value "high" is stored when dbit0 is "high" and dbit1 is "low", and the value is low when dbit0 is "low" and dbit1 is "high". When dbit0 is "high" and dbit1 is "high", the inmatch is stored when both the bit mask and dbit are written low, so the address can be unmatched. At this time, the r bit line has a value complementary to the d bit line. In FIG. 2, when a and d, c and b are connected at the intersection, the operation is performed with the inverse data compared to the original method.

When reading a maskable CAM cell, if it has a value of 1 or 0, 1 or 0 is read through an r-bit line as in a normal SRAM read, and when using a single-ended SRAM, a sense amplifier or a logical processing is performed. It is also possible to read mask (or don't care) data to be either 1 or 0.

This fixed mask-enabled CAM cell can be configured in a size similar to that of a typical SRAM cell because nmos are connected in parallel, and can function in conjunction with a typical SRAM cell, providing an effective configuration (i.e. adjusting cell height). Is easy). Alternatively, the range can be reduced by using resistive SRAM, single-ended SRAM, or the like instead of the complimentary SRAM of A.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention as described above, the bit mask function can be performed by storing the maskable data having a static characteristic and can unmagnify a specific address.

In addition, it can read and write at a speed equivalent to that of a general SRAM, and can be efficiently connected to other memories even in a configuration, and the operation can almost use a general CAM structure.

Therefore, these characteristics can be used for applications such as variable length corners, pattern recognition, and the like.

Claims (1)

A plurality of contents each having a data storage unit for storing data input from the outside, and a comparison unit consisting of a plurality of transistors to compare the address data and the stored data input from the outside to determine a match, and performs an exclusive OR function. In a content addressable memory device arrayed with addressable cells, the data storage of each of the content addressable cells includes: a first side having one side connected to a first write bit line and a gate connected to a word line; Switching transistors; A second switching transistor having one side connected to a first read bit line and a gate connected to the word line; A first latch unit connected between the other side of the first switching transistor and the other side of the second switching transistor; A third switching transistor having one side connected to a second read bit line and a gate connected to a word line; A fourth switching transistor having one side connected to a second write bit line and a gate connected to the word line; And a third latch unit connected between the other side of the third switching transistor and the other side of the fourth switching transistor, wherein the comparing unit is connected in series between a matching line and a ground power source, and a gate of the third switching transistor is connected in series. First and second enMOS transistors respectively connected to a first write bit line and a storage node of the first latch unit; A third and fourth enMOS transistor connected in series between the matching line and a ground power source, each of which has its gate connected to the second write bit line and the storage node of the second latch unit, respectively. A content addressable memory device.