JP3185278B2 - Orthogonal memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an orthogonal memory for storing data such as images.

2. Description of the Related Art A memory for storing data such as images is required to have a function of inputting and outputting a large amount of data at high speed. Therefore, there is a memory called a video memory or a field memory as shown in FIG. In this method, a serial access memory 102 which can be accessed at high speed is juxtaposed beside a normal memory cell 101. For example, at the time of data output, a row address is designated from the outside and data of one row is transferred from the memory cell 101 to the serial access memory 10
2 and then transfer from the serial access memory 102 to 1
This is a technique for outputting data in rows sequentially and at high speed sequentially from the end. At the time of data input, one row of data is successively input from the end to the serial access memory 102 at high speed sequentially, and then a row address is specified from the outside, and one row of data is transferred from the serial access memory 102 to the memory cell 1 at a time.
Transfer to 01. This method is described in, for example, the 1985 I Triple E International Solid State Circuits Conference, Digest of Technical Papers (1985).
IEEE International Solid-
State Circuits Conference
e, Digest of Technical Pap
ers), Article No. WAM 3.1, pp. 38-39. Further, when processing two-dimensional data, there are processes that require high-speed data input / output in the row direction and processes that require high-speed data input / output in the column direction. Therefore, there is a memory called an orthogonal memory as shown in FIG. This is the external and orthogonal memory cell 1
This is a technique that can perform data input / output with the H.11 at the same time in both the row direction and the column direction. This method is described in, for example, IEICE Electron Devices Workshop Material, EDD-85, 36-
No. 40, pages 13-20.

In the conventional method, FIG.
In the case of a memory such as 0, there is a problem that continuous input / output of image row data can be performed at high speed sequentially from the end, but high-speed input / output of column data cannot be performed. Also,
The memory shown in FIG. 11 has a feature that data corresponding to the width of a memory cell can be input / output at high speed in parallel in the row direction and the column direction of an image, but the memory cell capacity of the memory cell is increased. However, the number of input / output signal lines increases, and it is difficult to fit them on one chip due to the limitation of the number of pins.
An object of the present invention is to solve such a problem and to provide a memory which can input and output data at high speed in both the row direction and the column direction.

An orthogonal memory according to a first aspect of the present invention is an orthogonal memory capable of reading data in a memory in a row direction and a column direction. An orthogonal memory cell capable of transferring data corresponding to the bit width, a row memory capable of storing data of one row of the orthogonal memory cell, a row memory which decodes an externally input row address, and Means for selecting one row on the cell; transferring one row of data on the orthogonal memory cell to the row memory at a time; and transferring one row of data on the row memory on the orthogonal memory cell at a time. A means for transferring data on the row memory continuously from the end, a means for continuously inputting data on the row memory from the end, and one column of the orthogonal memory cell. Minute And column memory capable of holding data, a column address input from the outside is decoded,
Means for selecting one column on the orthogonal memory cell, transferring data of the selected one column on the orthogonal memory cell to the column memory at a time, and transferring data of one column on the column memory at a time It is characterized by having means for transferring data to a selected column on a cell, and means for continuously outputting data on a column memory sequentially from an end, and for continuously inputting data on a column memory sequentially from an end. And The orthogonal memory according to a second aspect of the present invention is the orthogonal memory according to the first aspect, wherein data on the row memory is continuously transferred to the column memory sequentially from the end, or data on the column memory is continuously transferred to the row memory sequentially from the end. It is characterized by having a means for transferring data in a specific manner. A quadrature memory according to a third invention is the quadrature memory according to the first invention, wherein the quadrature memory has a plurality of row memories and column memories, and sequentially transfers data on an arbitrary row memory to an arbitrary column memory from an end, It is characterized by having means for transferring data in an arbitrary column memory to an arbitrary row memory sequentially from the end in parallel between a plurality of row memories and column memories. A quadrature memory according to a fourth aspect of the present invention is the quadrature memory according to the first aspect, wherein data of one selected row in the quadrature memory cell is transferred to the column memory at a time, or data of one column in the column memory is stored. At a time to the selected row on the orthogonal memory cell, transfer the data for one selected column on the orthogonal memory cell to the row memory at a time, or transfer the data for one row on the row memory It is characterized by having means for transferring to a selected column on the orthogonal memory cell at a time. A quadrature memory according to a fifth aspect of the present invention is an orthogonal memory capable of reading data in a memory in a row direction and a column direction, holding the data, and transferring data of the bit width at a time in the column direction and the row direction. A quadrature memory cell that can store data of a plurality of rows of the quadrature memory cell;
Means for decoding a row address output from the outside and selecting one row on an orthogonal memory cell; transferring data of the selected one row on the orthogonal memory to the word row memory at a time; Means for transferring the data of the above one row at a time to a selected row on the orthogonal memory cell; and outputting data on the word row memory continuously in word units from the end, or on the word row memory. Means for continuously inputting data in order from the end in word units, a word string memory capable of holding data for a plurality of columns of orthogonal memory cells, and decoding an externally input column address,
Means for selecting one column on the orthogonal memory cell, transferring data of the selected one column on the orthogonal memory cell to the word column memory at a time, and transferring one column of data on the word column memory at a time. A means for transferring data to a selected column on the orthogonal memory cell, and continuously outputting data on the word column memory in word units from the end, or continuously outputting data on the word column memory in word units from the edge. And means for inputting to the A quadrature memory according to a sixth aspect of the present invention is the orthogonal memory according to the fifth aspect.
In the orthogonal memory according to the invention, the data in the word row memory is continuously transferred to the word row memory in word units sequentially from the end, or the data in the word row memory is continuously transferred to the word row memory in word units from the edge sequentially. Characterized by having means for transferring to An orthogonal memory according to a seventh aspect of the present invention is the orthogonal memory according to the fifth aspect of the present invention, wherein the orthogonal memory has a plurality of word row memories and word string memories, and sequentially stores data on an arbitrary word row memory in an arbitrary word string memory in word units from the end. It has means for performing a parallel transfer between a plurality of word row memories and a word column memory to continuously transfer or sequentially transfer data on an arbitrary word row memory to an arbitrary word row memory from an end. It is characterized by the following. An orthogonal memory according to an eighth aspect of the present invention is the orthogonal memory according to the fifth aspect of the present invention, wherein data of one selected row in the orthogonal memory cell is transferred to the word column memory at a time, or data of one row in the word column memory is provided. At a time to a selected row on an orthogonal memory cell, transfer data for one selected column on an orthogonal memory cell to a word row memory at a time, or transfer one row on a word row memory And means for transferring the data for one minute to a selected column on the orthogonal memory cell at a time. The orthogonal memory according to the ninth aspect is the orthogonal memory according to the first, second, third, fourth, fifth, sixth, seventh or eighth aspect, wherein the memory element and the data specified by an externally applied row address and column address are provided. Characterized in that it has means for inputting and outputting data.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of the orthogonal memory according to the first invention. The orthogonal memory includes an orthogonal memory cell 11 for holding data and one or more row memories 12 for holding data for one row of the orthogonal memory cell. , A row decoder 13 for selecting one row, transferring data of one selected row on the orthogonal memory cell to the row memory at a time, or transferring one row of data on the row memory at a time on the orthogonal memory cell. A row transfer circuit 14 for transferring data to a selected row; a row memory input / output circuit 15 for continuously outputting data on a row memory sequentially from an end; One or more column memories 16 that can hold data for one column of memory cells, a column decoder 17 that decodes an externally input column address and selects one column on an orthogonal memory cell, A column transfer circuit 18 for transferring data of one selected column on a memory cell to a column memory at a time, or transferring data of one column on a column memory at a time to a selected column on an orthogonal memory cell. , A column memory input / output circuit 19 for continuously outputting data on the column memory sequentially from the end, or continuously inputting data on the column memory sequentially from the end. In the orthogonal memory having such a configuration, when data of a certain row on the orthogonal memory cell 11 is continuously output in order from the end,
First, the row address given from the outside is stored in the row decoder 13.
Decodes and selects one row on the orthogonal memory cell 11. Next, the selected row data is transferred to the row transfer circuit 14.
Transfer to one of the row memories 12. And row memory 1
2, the row memory input / output circuit 15 outputs the data sequentially from the end. When data of one row is continuously input from the outside in order from the end and stored in a certain row on the orthogonal memory cell 11, first, the row memory input / output circuit 15 inputs data from the outside, and One to store. Next,
The row decoder 13 decodes an externally applied row address, selects one row on the orthogonal memory cell 11, and transfers the data on the row memory 12 to the selected one row. When sequentially outputting data of a certain column on the orthogonal memory cell 11 in order from the end, first, the column decoder 17 decodes an externally applied column address, and selects one column on the orthogonal memory cell 11. Next, the column transfer circuit 18 transfers the selected one column of data to one of the column memories 16. Then, the column memory input / output circuit 19 continuously outputs data on the column memory 16 in order from the end. When one column of data is continuously input from the outside in order from the end and stored in a certain column on the orthogonal memory cell 11, first, the column memory input / output circuit 19 inputs data from the outside and the column memory 1
6 is stored. Then, the column decoder 17 decodes an externally applied column address, selects one row on the orthogonal memory cell 11, and transfers it to the selected one column by the column data transfer circuit 18 on the column memory 16. Data input / output of the row memory 12 by the row memory input / output circuit 15 and data input / output of the column memory 16 by the column memory input / output circuit 19 can be performed completely independently of the operation state of other parts on the orthogonal memory chip. , The plurality of row memories 12 and the plurality of column memories 1 unless the access to the orthogonal memory cells 11 conflicts.
6 can all be performed in parallel. FIG. 2 is a block diagram showing the configuration of an embodiment of the orthogonal memory according to the second invention. This orthogonal memory includes, in addition to the configuration shown in FIG. 1, an inter-matrix data transfer circuit 21 for sequentially transferring data between a row memory 12 and a column memory 16 in order from the end. In the orthogonal memory having such a configuration, one column of data is transferred from the orthogonal memory cell 11 to the column memory 16, then transferred to the row memory 12 by the inter-matrix data transfer circuit 21, and then the data is transferred to the orthogonal memory cell 11. In the orthogonal memory cell 11
Column data of the above two-dimensional data can be converted to row data.
Further, after transferring one row of data from the orthogonal memory cell 11 to the row memory 12, the data is transferred to the column memory 16 by the inter-matrix data transfer circuit 21, and then the data is stored in the orthogonal memory cell 11. Row data of two-dimensional data on the memory cell 11 can be converted to column data. The row memory 12 and the column memory 16 to which data is transferred by the inter-matrix data transfer circuit 21 are prohibited from inputting and outputting data by the row memory input / output circuit 15 and the column memory input / output circuit 19. However, the data being transferred can be output to the row memory input / output circuit 15 and the column memory input / output circuit 19 simultaneously with the transfer. At the same time as data is input to the row memory 12 and the column memory 16 by the row memory input / output circuit 15 and the column memory input / output circuit 19, the data is transferred to the column memory 16 by the inter-matrix data transfer circuit 21.
Alternatively, the data can be transferred to the row memory 12. FIG.
FIG. 11 is a block diagram showing a configuration of an embodiment of an orthogonal memory cell according to the third invention. This orthogonal memory has a plurality of row memories 12 and a plurality of column memories 16. In addition to the configuration of FIG. 1, a matrix for sequentially transferring data between the row memory 12 and the column memory 16 sequentially from the end is used. An inter-data transfer circuit 31 is provided. In the orthogonal memory having such a configuration, the inter-matrix data transfer circuit 31 is configured by a crossbar switch, and can transfer data between any row memory 12 and any column memory 16. After transferring one column of data from the orthogonal memory cell 11 to the column memory 16, the inter-matrix data transfer circuit 31 transfers data from the externally designated column memory 16 to the row memory 12,
Next, by storing the data in the orthogonal memory cell 11, the column data of the two-dimensional data on the orthogonal memory cell 11 can be converted into row data. Orthogonal memory cells 11 to 1
After the row data is transferred to the row memory 12, the row memory 12
Then, the data is transferred to the column memory 16 and then the data is stored in the orthogonal memory cell 11, whereby the row data of the two-dimensional data on the orthogonal memory cell 11 can be converted into the column data. FIG. 4 is a block diagram showing the configuration of an embodiment of the orthogonal memory according to the fourth invention. In addition to the configuration shown in FIG. 1, the orthogonal memory transfers data of one selected row in the orthogonal memory cell 11 to the column memory 16 or the column memory 1
6, the data of one row on the orthogonal memory cell 11 is transferred to the selected row, the data of the selected one column on the orthogonal memory cell 11 is transferred to the row memory 12, An inter-matrix parallel data transfer circuit 41 is provided for transferring the data of the above one row to a selected column on the orthogonal memory cell 11. In the orthogonal memory having such a configuration, the inter-matrix parallel data transfer circuit 41 has a signal line corresponding to the bit width of the orthogonal memory cell 11 and is realized by passing a wiring over the orthogonal memory cell 11. . While the orthogonal memory shown in FIGS. 2 and 3 sequentially transfers data to convert data between rows and columns,
The inter-matrix parallel data transfer circuit 41 can transfer data in parallel at a time. Further, since the inter-matrix parallel data transfer circuit 41 can perform high-speed data transfer between rows and columns, the functions of the column memory 16, the column data transfer circuit 18, and the column memory input / output circuit 19 are changed to the row memory 12, the row data This can be realized by the transfer circuit 14 and the row memory input / output circuit 15, and the number of pins and the chip size can be reduced. FIG. 5 is a block diagram showing the configuration of an embodiment of the orthogonal memory according to the fifth invention. The orthogonal memory decodes an externally input row address, including one or more orthogonal memory cells 11 for holding data, and one or more word row memories 51 for holding data for a plurality of rows of the orthogonal memory cells 11, A row decoder 13 for selecting one row on the orthogonal memory cell 11; transferring data of the selected one row on the orthogonal memory cell 11 to the word row memory 51 at a time; Row transfer circuit 5 for transferring the data at a time to a selected row on orthogonal memory cell 11
2. A word row memory input / output circuit 53 which continuously outputs data on the word row memory 51 in word units from the end, or continuously inputs data on the word row memory 51 in word units from the end. Word string memory 54 capable of holding data for a plurality of columns of orthogonal memory cells 11
A column decoder 17 that decodes one or more column addresses input from the outside and selects one column on the orthogonal memory cell 11; A column transfer circuit 55 for transferring data to the memory 54 or transferring one column of data on the word column memory 54 to a selected column on the orthogonal memory cell 11 at a time. It is composed of a word string memory input / output circuit 56 which continuously outputs data sequentially from the end or continuously inputs data into the word string memory 54 in word units sequentially from the end. FIG. 12 shows an example of bit correspondence between the orthogonal memory cell 11, the word row memory 51, and the word column memory 54 in the orthogonal memory having such a configuration. FIG. 12 is a diagram for explaining a bit configuration of an orthogonal memory cell 121 having a configuration of 16 bits × 16 bits, a word row memory 122 and a word column memory 123 having an 8-word configuration. However, one word is assumed to be 4 bits. As shown in FIG. 12, the orthogonal memory cell 121 is divided into 2 bits × 2 bits, and the 4 bits are assigned to one word. It is assumed that the order of the bits in the word is assigned in the order written on the orthogonal memory cell 121 in FIG. In the orthogonal memory having such a configuration, data externally input to the word row memory 122 is stored in the orthogonal memory cell 1.
The method of transferring the information to the server 21 will be described. First, the data of the bits of all the words on the word row memory 122 is
The data is transferred at a time to one row assigned to the data on the orthogonal memory cells 121. Next, the data with the bits of all the words on the word row memory 122 is transferred at a time to the next row of the row previously transferred on the orthogonal memory cell 121, that is, one row assigned to the data with the same. I do. In this manner, the data of all the words in the word row memory 122 can be transferred to the orthogonal memory cells 121 by transferring the rows twice. Next, the data stored in the orthogonal memory cell 121 is stored in the word row memory 1.
The method of transferring the data to the storage 22 will be described. First, of the two columns of the orthogonal memory cell 121 that hold data to be transferred to the word row memory 122 from now on, the data of the row holding the bit of “1” is transferred to the word row memory 122 at one time, 122. Next, the data of the row holding the bits and are transferred to the word row memory 122 at one time, and are stored at the position of and on the word row memory 122. Thus, 2
The data on the orthogonal memory cells 121 can be transferred to the word row memory 122 by transferring the rows twice. Next, a method of transferring data externally input to the word string memory 123 to the orthogonal memory cells 121 will be described. First, the data of all the bits of the word in the word string memory 123 are transferred to the one column assigned to the data in the orthogonal memory cell 121 at one time. Next, the data with the bits of all the words in the word string memory 123 is transferred at a time to the next column of the column previously transferred on the orthogonal memory cell 121, that is, one column assigned to the data with the same. I do. In this manner, the data of all the words in the word string memory 123 can be transferred to the orthogonal memory cells 121 by transferring the column twice. Next,
A method of transferring data stored in the orthogonal memory cells 121 to the word string memory 123 will be described. First, of the two columns of orthogonal memory cells 121 that hold data to be transferred to the word string memory 123, the data of the column holding the bits of the orthogonal memory cells 121 is transferred to the word string memory 123 at a time, and 123 is stored at the position of. Next, the data of the column holding the bits and are transferred to the word string memory 123 at a time, and stored at the position on the word string memory 123. In this manner, data in the orthogonal memory cell 121 can be transferred to the word string memory 123 by transferring the column twice. The word row memory input / output circuit 53 and the word column memory input / output circuit 56 continuously output data on the word row memory 122 and the word column memory 123 as shown in FIG. Data is input continuously from outside in word units from the end. FIG. 6 is a block diagram showing the configuration of an embodiment of the orthogonal memory according to the sixth invention. This orthogonal memory includes, in addition to the configuration shown in FIG. 5, an inter-matrix data transfer circuit 61 for sequentially transferring data between the word row memory 51 and the word column memory 54 in word units sequentially from the end. . In the orthogonal memory having such a configuration, data of a plurality of columns is transferred from the orthogonal memory cell 11 to the word column memory 54, and then transferred to the word row memory 51 by the inter-matrix data transfer circuit 61. By storing in cell 11,
Column data of word-structured two-dimensional data on the orthogonal memory cell 11 can be converted into row data. Further, after transferring a plurality of rows of data from the orthogonal memory cell 11 to the word row memory 51, the data is transferred to the word string memory 54 by the inter-matrix data transfer circuit 61, and then the data is transferred to the orthogonal memory cell 11.
, The row data of the word-structured two-dimensional data on the orthogonal memory cell 11 can be converted into column data. FIG. 7 is a block diagram showing the configuration of an embodiment of the orthogonal memory according to the seventh invention. This orthogonal memory has a plurality of word row memories 51 and a plurality of word column memories 54. In addition to the configuration shown in FIG. 5, data is successively stored in word units between the word row memory 51 and the word column memory 54 in order from the end. -To-matrix data transfer circuit 71 for efficient transfer
It has. In the orthogonal memory having such a configuration,
The inter-matrix data transfer circuit 71 is configured by a crossbar switch, and can transfer data between an arbitrary word row memory 51 and a word column memory 54. A plurality of columns of data from the orthogonal memory cell 11 are stored in the word column memory 5.
4, the data is transferred from the externally designated word column memory 54 to the word row memory 51 by the inter-matrix data transfer circuit 71, and then the data is stored in the orthogonal memory cell 11 to obtain the orthogonal memory. Cell 11
The column data of the two-dimensional data having the above word configuration can be converted into row data. After transferring a plurality of rows of data from the orthogonal memory cell 11 to the word row memory 51, the word row memory 51 specified from the outside by the inter-matrix data transfer circuit 71.
To the word row memory 54, and then storing the data in the orthogonal memory cell 11, the row data of word-structured two-dimensional data on the orthogonal memory cell 11 can be converted to column data. FIG. 8 is a block diagram showing the configuration of an embodiment of the orthogonal memory according to the eighth invention. This orthogonal memory stores data of one selected row in the orthogonal memory cell 11 in the word string memory 5 in addition to the configuration of FIG.
4, the data of one row on the word string memory 54 is transferred to the selected row on the orthogonal memory cell 11, and the data of one selected column on the orthogonal memory cell 11 is transferred to the word row. An inter-parallel parallel data transfer circuit 8 for transferring data to the memory 51 or transferring one row of data in the word row memory 51 to a selected column in the orthogonal memory cell 11
1 is provided. In the orthogonal memory having such a configuration, the inter-matrix parallel data transfer circuit 81 has a signal line corresponding to the bit width of the orthogonal memory cell 11 and is realized by passing a wiring over the orthogonal memory cell 11. . While the orthogonal memory shown in FIGS. 6 and 7 sequentially transfers data in word units to convert data between rows and columns, the inter-matrix parallel data transfer circuit 81 Can be transferred in parallel. Further, since data can be transferred at high speed between rows and columns by the inter-parallel parallel data transfer circuit 81, the functions of the word column memory 54, the column data transfer circuit 55, and the word column memory input / output circuit 56 are
This can be realized by the word row memory 51, the row data transfer circuit 52, and the word row memory input / output circuit 53, and the number of pins and the chip size can be reduced. FIG.
FIG. 29 is a block diagram showing a configuration of an embodiment of an orthogonal memory according to the ninth invention. This orthogonal memory has the structure of FIG.
A data input / output circuit 91 is provided for inputting / outputting data between bits on the orthogonal memory cell 11 designated by the row decoder 13 and the column decoder 17 and the outside.
In the orthogonal memory having such a configuration, when both the row memory 12 and the column memory 16 do not access the orthogonal memory cell 11, the orthogonal memory cell 11 can be randomly accessed through the data input / output circuit 91.

As described above, according to the present invention, the memory for continuous input / output of row data and the memory for continuous input / output of column data are added to the orthogonal memory cell to reduce the number of pins. A large-capacity orthogonal memory chip can be configured without being restricted, and data can be input / output at high speed in both the row direction and the column direction. There is also an effect that a function of converting between the row direction and the column direction can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an orthogonal memory according to the first invention.

FIG. 2 is a block diagram showing an embodiment of an orthogonal memory according to the second invention.

FIG. 3 is a block diagram showing an embodiment of an orthogonal memory according to the third invention;

FIG. 4 is a block diagram showing an embodiment of an orthogonal memory according to the fourth invention;

FIG. 5 is a block diagram showing an embodiment of an orthogonal memory according to the fifth invention.

FIG. 6 is a block diagram showing an embodiment of an orthogonal memory according to the sixth invention.

FIG. 7 is a block diagram showing an embodiment of an orthogonal memory according to the seventh invention;

FIG. 8 is a block diagram showing an embodiment of an orthogonal memory according to the fourth invention.

FIG. 9 is a block diagram showing an embodiment of an orthogonal memory according to the ninth invention;

FIG. 10 is a block diagram showing a configuration example of a conventional video memory.

FIG. 11 is a block diagram showing a configuration example of a conventional orthogonal memory.

FIG. 12 is a diagram for explaining a configuration of orthogonal memory cells of an orthogonal memory and bits of a word row memory and a word column memory according to an embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 11 orthogonal memory cell 12 row memory 13 row decoder 14 row transfer circuit 15 row memory input / output circuit 16 column memory 17 column decoder 18 column transfer circuit 19 column memory input / output circuit 21 inter-matrix data transfer circuit 31 inter-matrix data transfer circuit 41 matrix Inter-parallel data transfer circuit 51 word row memory 52 row transfer circuit 53 word row memory input / output circuit 54 word column memory 55 column transfer circuit 56 word column memory input / output circuit 61 inter-matrix data transfer circuit 71 inter-matrix data transfer circuit 81 inter-matrix Parallel data transfer circuit 91 Data input / output circuit 101 Memory cell 102 Serial access memory 111 Quadrature memory cell 121 Quadrature memory cell 122 Word row memory 123 Word column memory

Claims (5)

(57) [Claims] 1. An orthogonal memory capable of reading data in a memory in a row direction and a column direction. The orthogonal memory can store data and transfer data of the bit width at a time in the column direction and the row direction. A quadrature memory cell, a word row memory capable of storing data for a plurality of rows of the quadrature memory cell, a means for decoding a row address input from the outside and selecting one row on the quadrature memory cell, Means for transferring data of one selected row on the memory cell to the word row memory at a time, or transferring data of one row on the word row memory to the selected row on the orthogonal memory cell at a time; A means for continuously outputting data in the word row memory in word units from the end, a means for continuously inputting data in word units to the word row memory in order from the end, and a quadrature method. A word column memory capable of storing data for a plurality of columns of memory cells; a means for decoding a column address input from the outside and selecting one column on an orthogonal memory cell; Means for transferring one column of data to the word column memory at a time, or transferring one column of data on the word column memory to a selected column on the orthogonal memory cell at a time; And a means for continuously outputting data from the end in word units or inputting data sequentially from the end to the word string memory in word units. 2. The data on the word row memory is continuously transferred to the word row memory in word units from the end, and the data on the word row memory is transferred continuously to the word row memory in word units from the end. orthogonal memory according to claim 1, characterized in that it comprises means for. 3. A memory having a plurality of word row memories and word string memories, wherein data on an arbitrary word row memory is successively transferred from an end to an arbitrary word string memory in word units from an end, or on an arbitrary word string memory. orthogonal memory of claim 1 wherein the data from the end to the arbitrary word line memory to continuously transferred in sequence, and a means for performing a plurality of word lines memory, in parallel between word sequence memory. 4. A method for transferring data of one selected row on an orthogonal memory cell to a word column memory at a time, or transferring data of one column on a word column memory at a time on a selected column of an orthogonal memory cell. Transfer data to a row, transfer data of one selected column in an orthogonal memory cell to a word row memory at a time, or transfer data of one row in a word row memory to a selected memory cell in an orthogonal memory cell at a time. orthogonal memory according to claim 1, characterized in that it comprises means for transferring to the column was. 5. A device according to claim 1, further comprising means for inputting / outputting data from / to a memory element specified by an externally applied row address and column address.
An orthogonal memory as described.