JPS63138443A - Picture memory device - Google Patents

Abstract

PURPOSE:To easily change the number of planes and to realize accesses in both a plane unit and a picture element unit by securing such a mechanism for a picture memory that realizes accesses for each picture element in a plane unit structure. CONSTITUTION:In a write mode with access of picture unit, data are written by a pixel/plane converting circuit 50 into the corresponding bit position in a single word of a write register 30-i for each plane. At the same time, the mask data is produced to show only said bit position is valid. Then the data on the read address of a memory plane 10-i is read out and only the data on the effective bit position is replaced by an arithmetic circuit 40-i containing a mask. Then the replaced data is written into the plane 10-i. In a read mode, the data on the corresponding address is read out of each plane for each word. Then only the valid bits are selected out of each word data by a plane/pixel converting circuit 110, then read out after reconstitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image memory device, and particularly to an image memory device that is efficient for both pixel-by-pixel processing and plane-by-plane processing.

[Conventional technology]

A method for storing multivalued images in which each pixel consists of multiple bits in image memory is described in the IE Computer Graphics and Applications
March, 1984, pp. 48-65 (IEEE
CG&A, MAR, CH11984, pp48-6
As discussed in Section 5), there are two methods: one for storing in plane units and the other for storing in pixel units.

[Problem that the invention seeks to solve]

Among the above conventional techniques, the method of storing in units of planes is as follows:
While it is possible to easily change the number of planes in the image memory, the method of storing data in units of drawings requires changing the arrangement of pixels on the memory, which is difficult to change.

However, in a plane unit configuration, if you want to rewrite less than one pixel, for example, just one pixel, read out one word of data including the data of that pixel, and only the corresponding bit. After changing the plane, the so-called read-modify-write process of writing to the memory had to be repeated for the number of planes, which was inefficient.

Furthermore, in terms of processing to be executed, access in units of planes is efficient when handling one character or graphic data, but access in units of pixels is essential when handling one image.

An object of the present invention is to easily change the number of planes.

The object of the present invention is to provide a single image memory device that can be accessed both plane by plane and pixel by pixel.

[Means for solving problems]

The above purpose is to configure the image memory in a plane-by-plane configuration, and as a mechanism to realize pixel-by-pixel access, an arithmetic circuit with a mask is installed in each plane, and a plane For unit access.

In the case of 1 pixel unit access, 1 pixel data is 1
Pixels that are decomposed bit by bit, that is, plane by plane →
This is achieved by providing a plane conversion circuit and a plane-pixel conversion circuit that extracts bits of corresponding pixels from data in units of planes and converts them into pixel data.

[Effect]

Since the image memory device configured as described above is arranged in units of planes, it can easily accommodate changes in the number of planes.

For per-plane access, select a plane and click
Writing and reading can be performed as is.

For pixel unit access, when writing.

The pixel-to-plane converter circuit generates mask data that is written to the corresponding bit position in a word of the write register for each plane, indicating that only that position is valid. Next, the memory
The data at the write address of the plane is read, and only the data at valid bit positions is replaced by the masked arithmetic circuit and written to the memory plane.

At the time of reading, data at the corresponding address is read one word at a time from each plane, and only valid bits are selected and reconfigured from each word data by the plane-to-pixel conversion circuit and read out.

In the manner described above, access to the plane-configured memory can be realized in units of planes and units of pixels.

〔Example〕

An embodiment of the present invention will be described below.

FIG. 1 is a configuration diagram of an embodiment. The pixel memory has a plane unit configuration consisting of memory planes lO-θ to 1O-t-1, and the data of each pixel is stored as shown in FIG. Here, the pixel in the i-th row and j-column of the image data is expressed as p(i, j), and the bit-th (corresponding to plane k) pixel is expressed as p(i, j), k.

Therefore, if one word is n bits, the first word of memory plane O is p(0,0), op(0
, n x), and o.

Further, to simplify the explanation, it is assumed that n=a-1.

(a, l, , n are natural numbers) n\a/t can be considered in the same way.

The data structure of one word during pixel-by-pixel access and plane-by-plane access is shown in FIG. 3(a).

The result will be as shown in (b). That is, when accessing pixel by pixel, 1
Word data is p(i,j)~p(isJ-)-a
-1), and when accessing by plane, p("I J') to p(i').

Of the data for one pixel of j'+n-1), it is composed of only the data for the first bit, the edge, and the plane.

Writing to the image memory is performed by the multiplexer MPX20 in the case of plane-based access.

The specified memory plane 117) is written to the IF write register W 30-1, passes through the arithmetic circuit 40-i, and is written to the memory plane i.

In the case of pixel-by-pixel access, data is converted by the pixel-plane conversion circuit 50. The contents of the conversion at this time are shown in FIG. Data aXt for 3 pixels consisting of 1 pixel and t bits = n bits is a set of n-bit data in which only the i-th bit of each pixel is collected,
are reconfigured into pairs. The reconstructed data is inserted into a predetermined position among n bits according to one pixel address.

At the same time, it indicates that only that part is valid. Mask data is generated. The t-brane data converted and reconstructed in this way is written to the write register W 30-1 of each plane. Next, the data at the write address of each memory plane, one word each, a total of t words, is read into the read register 8 60-i. The data in the write register W 30-i and the read register 60-1 is operated on only valid bit positions according to the mask register 70-i in the arithmetic circuit 40-1, and then transferred to each memory plane. Get caught up in.

When reading the image memory, in the case of plane-based access, data for one word of the corresponding address is read out from each plane to the readout register R860-i, and the data of the specified plane is read out by the selector SEL, 9G. only selected and read.

In the case of pixel unit access, data for one word of the corresponding address is similarly read from each plane to the read register RR160-i.

Next, the t-word data is subjected to the conversion shown in FIG. 4 in the plane-pixel conversion circuit 110, and is reconfigured into one word of pixel unit data and read out.

Selectors 5o-i and selector 100 in FIG. 1 each have the ability to select between plane-by-plane access mode and pixel-by-pixel access mode during writing and reading.

Different logical addresses are given to a memory plane when accessing by plane and when accessing by pixel. These two types of logical addresses are translated into physical addresses of the memory plane in the address translation unit 1'20.

In Figure 5, 1 pixel is 8 bits, 1024 rows x 1024
An example of logical addresses is shown for a column image memory. Image 1 memory has a capacity of I FdByte, 0 to FF
Occupies address space of FFF(16). Here, the starting address of one image memory is set to 0, but the same effect can be applied even if a fixed offset is added. Addresses in the figure are hexadecimal numbers.

In the case of plane-by-plane access, there is a method of allocating the same address to each plane and distinguishing them by plane designation, but here we have adopted a method of allocating different addresses to each plane.

Here, the conversion from the pixel unit address ADDRp+g to the plane unit address ADDRm I--- can be expressed by the following equation.

ADD,! 11. =[ADDRp+yt-/8]+plane...N,

That is, the data of plane 1 at pixel unit address 123 (16) is 123 (16)/8 (16) = 24 (
16)...3 (16) Yoshi, Brain unit address 2
0024 (16) This is the third bit counting from M8B.

〔Effect of the invention〕

According to the present invention, there are the following effects.

α) Access to the same memory in units of planes
and can perform pixel-by-pixel access, so when handling a mixture of text, graphics, and image data, you can access one character, graphics data in plane units, and image data in pixel units, depending on the processing content. 9. Efficient memory usage can be achieved.

(2) The physical configuration is a plane configuration, and the number of planes of the image memory can be easily changed.

(3) If the number of planes in the image memory has been changed.

Plane unit access and modification of peripheral circuits.

is almost achievable. Pixel-by-pixel access can also be achieved simply by expanding the pixel nib lane conversion section, providing excellent expandability.

(4) Since each memory plane has an arithmetic circuit, writing can be performed while performing arithmetic processing. This makes it possible to easily implement random operations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing the allocation of pixel data to a memory plane, and FIG.
The figures are pixel by pixel and plane by plane. The figure which shows the structure of 1 word data in each case. FIG. 4 is an explanatory diagram of pixel->brane conversion, and FIG. 5 is a diagram showing an example of logical address assignment during pixel-by-pixel access and plane-by-plane access. 10-i...Memory plane, 30-i...Write register, 40-4...Arithmetic circuit% 50...
Pixel-plane conversion circuit, 6Q-i...readout register, 70-i...mask register, 110.
...Brain-pixel conversion circuit, 120...address conversion section.

Claims (1)

[Claims] In an image memory device consisting of l memory planes with 1, 1-bit x row and y column, each memory plane consisting of a word-based random access memory, selectively accessing any bit in the word. The first accessible
and a second means for reconfiguring the plurality of pixel data of l bits and one pixel into data sets for each bit position, l sets, and writing them into the memory plane by the first means. image memory device.