JPH02137040A - Picture processor - Google Patents

Abstract

PURPOSE:To facilitate the accesses to the picture data of various block sizes by performing the switch between an access means which defines a picture memory as a block dividing memory and another access means which defines the picture memory as a block assembling memory. CONSTITUTION:A memory control part 4 inputs a control signal 35 to a selector 31 of an address conversion part 2 to use a picture memory 3 as a 2-block dividing memory with an instruction given from a system bus 1. Thus the selector 31 selects the side of an address decoder 36 and gives the accesses to the 1st and 2nd blocks 5 and 6 as if they served as the independent memories. At the same time, the part 4 inputs the signal 35 to the selector 31 to use the memory 3 as a 2-block assembling memory with an instruction of the bus 1. Thus the selector 31 selects the side of an address decoder 37 and gives an access to cover both blocks 5 and 6. Thus it is possible to easily give the proper accesses to the picture data of various block sizes without giving the change to the host side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing apparatus, and particularly to an image processing apparatus that can easily and appropriately handle image data of various block sizes.

[Prior Art] FIGS. 2(A) and 2(CB) are diagrams showing an example of the structure of a conventional image memory. In Figure 2 (A), the memory space is (2
048x1024) It consists of one block of pixels, and the first line is accessed by addresses 0 to 2047, and the second line is accessed by addresses 2048 to 4055. In Figure 2 (B), the memory space is 1024 x 102
4) It consists of two blocks of pixels, the first block 2
In 1, the lth line is address 0-1023, and 2
The 1st line is accessed at addresses 1024 to 2047, and in the second block 22, the 1st line is accessed at addresses 1024 to 2047.
At addresses 048576 to 1049599, the second line is accessed at addresses 1049600 to l○50623.

[Problems to be Solved by the Invention] However, since the block size of original image data varies, for example, the block size of the original image data (1024×10
24) If you try to write image data in which each pixel is one block, the original image will be stretched horizontally.
It is virtually impossible to write image data of (1024×1024) pixels in the central part of the memory in B).

The present invention is intended to eliminate the drawbacks of the prior art described above, and its purpose is to provide an image processing device that has a simple configuration and can easily and properly access image data of various block sizes.

[Means for Solving the Problems] In order to achieve the above object, the image processing device of the present invention has the following features:
an image memory that stores image data according to a raster scanning method; a first access means that accesses the image memory as a block divided memory by changing a chip enable signal block by block; The present invention generally includes a second access means for accessing the image memory as a block set memory by changing the number of blocks, and a switching means for switching between the first and second access means.

[Operation] In this configuration, the image memory stores image data according to a raster scanning method. The first access means accesses the image memory as a block divided memory by changing the chip enable signal for each block. The second access means accesses the image memory as a block set memory by changing the chip enable signal in the middle of a line or column. The switching means switches between the first and second access means.

[Description of Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[First Embodiment] The first embodiment relates to an image processing apparatus equipped with a random access type image memory.

FIG. 1 is a conceptual diagram of an image memory section of an image processing apparatus according to a first embodiment. In the figure, 1 is a system bus that connects the image storage section of the embodiment to a CPU (not shown) or the like. Reference numeral 2 denotes an address conversion unit which converts general address information from the system bus 1 into address information of a plurality of types of address systems. 3 is an image memory, which is composed of, for example, a RAM.

The image memory 3 stores one pixel data in one byte, and has a total capacity of (X=2048) x (Y=1024) bytes. 5 is the logical first block of the image memory 3, and (X=1024) x (Y=10
24) Equivalent to bytes. 6 is also the second block and corresponds to (X=i024) x (Y=1024) bytes on the right side. A memory control section 4 generates various timing signals and control signals.

FIG. 3 is a circuit diagram of the address translation section 2 of the first embodiment. In the figure, 30 is an address signal line to which address information (for example, 21 bits) from the system bus 1 is input. 36 is a first address decoder, which receives address information from the system bus l as if the image memory 3 were
It is converted into an address signal that can be accessed as if it were a block divided memory. That is, the chip enable signal (CEl) 33 is the most significant bit (bit 20) of the address information.
0 and (CH2) 331 are generated, bits 0 to 9 are used as X address signals, and bits 10 to 19 are used as X address signals. A second address decoder 37 converts address information from the system bus 1 into an address signal for accessing the image memory 3 as if it were a 2-block set memory (ie, 1-block memory).

That is, bits 0 to 10 are set as the
CH2) 333 is generated, and bits 11 to 20 are used as an X address signal (FIG. 5). 31 is a selector which selects and outputs the signal of address decoder 36 or 37 according to control signal 35. The outputs of the selector 31 are a 20-bit address signal 32, a CEI signal 33, and a CE2 signal 34. When the CEI signal 33 is a logic level, only the first block 5 of the image memory 3 is activated;
When the CE2 signal 34 is a logic level, only the second block 6 is activated.

The CEI and CH2 signals are exclusive.

When using the image memory 3 as a 2-block divided memory> In response to a command from the system bus 1, the memory control section 4 inputs a control signal 35 to the selector 31 indicating that the image memory 3 is to be used as a 2-block divided memory. As a result, the selector 31 selects the first address decoder 36 side,
When the input address information is 0h-OFFFFFFh (h is hex), the first block 5 is accessed like an independent memory according to raster scanning, and the manual address information is 10.
0000. -IFFFFFh, the second block 6 is accessed like an independent memory according to raster scanning.

When using the image memory 3 as a 2-block set memory> In response to a command from the system bus 1, the memory control section 4 inputs a control signal 35 to the selector 31 indicating that the image memory 3 is to be used as a 2-block set memory. As a result, the selector 31 selects the second address decoder 37 side,
When bit 10 of the input address information changes from OFF to ON, the chip selection changes from CEI to CH2, the first block 5 is disabled, and the second block is enabled. In this way, the address system on the system bus l side is (
Even in the case of X=2048)X (Y=1024), it is possible to easily form image data spanning two blocks in the image memory 3 (FIG. 4).

[Second Embodiment] The second embodiment relates to an image processing apparatus including a sequential access type image memory. In this case, means for generating address information (21 bits) such as that input to the system bus 1 described above is required. That is, it is a means for generating address information that changes in a predetermined sequence after receiving the initial address setting from the system bus 1.

FIG. 7 is a conceptual diagram of the image memory section of the image processing apparatus of the second embodiment. In the figure, 7 is an address generator;
After the first address is set, an address signal 67 that changes in a predetermined sequence is generated. Address signal 67 is input to address converter 2 and used as address signal 30.

The chip enable (CH2) signal is ANDed with the CEI and CE2 signals output by the address converter 2, respectively, and the results are reused as the CEI and CE2 signals.

FIG. 6 is a block diagram of the address generator of the second embodiment. In the figure, 630 and 631 are Y and X length registers, respectively, which hold the number of transferred pixels in the Y and X directions. 640 is a Y counter, which is reset by the particle signal V and incremented by the horizontal signal H. 641 is an X counter, which is reset by the horizontal signal H and incremented by the clock signal CLK. 620 and 621 are comparators,
The values of the X and Y length registers and the X and Y counters are compared, and while the counter values are small, a logic level signal is output. As a result, the signal CE3 of the AND gate 65 outputs
outputs a logic level only to the extent that the scan signal does not exceed the contents of the X and Y length registers.

On the other hand, 600,601 is husband'? Y, X (7) L/register, holds the start address of image data to be sequentially accessed. 610 is a row counter, and the Y register 6 is controlled by the particle signal V.
The contents of 00 are loaded and incremented by horizontal signal H. 611 is a column (Co 1 umn)
This counter loads the contents of the X register 601 using the horizontal signal H, and increments it using the clock signal CLK. An address generator 68 converts the outputs of the row counter 610 and column counter 611 into addresses according to the control signal 75 and outputs the converted addresses. For example, when a control signal 75 indicating that the original image data fits into a two-block collective memory is given, the contents of the column counter 611 are output as address bits 0 to 10, and the contents of the row counter 610 as address bits 11 to 20. do.

Further, when a control signal 75 indicating that the original image data is compatible with the two-block divided memory is given, the column counter 611
The contents of the low counter 610 are output to bits 0 to 9, and the contents of the low counter 610 are output to bits 10 to 2o.

Note that the image memory size may be other than (2048×1024) pixels, and the number of blocks may be 3 or more. In this case, the blocks do not need to be physically adjacent. Can be logically divided or aggregated.

Further, although the case where the chip enable signal changes in the middle of a line has been shown, it may also change in the middle of a column.

[Effects of the Invention] As described above, according to the present invention, - image memory can be divided into a plurality of blocks and each block can be accessed independently without making any changes to the host side, and the entire image memory can be accessed independently as a unit. A set of image data can be accessed in any area of the image memory.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram of the image memory section of the image processing device of the first embodiment. FIGS. 2(A) and (B) are diagrams showing an example of the structure of a conventional image memory. FIG. 3 is the first embodiment. FIG. 4 is a diagram showing how the original image data 40 spans the first block 5 and the second block 6, and FIG. 5 is an example of the address structure of the first embodiment. 6 is a block diagram of the address generation section of the second embodiment, and FIG. 7 is a conceptual diagram of the image memory section of the image processing apparatus of the second embodiment. In the figure, ■...System bus, 2...Address conversion unit 3...Image memory, 4...Memory control unit,
5...first block, 6...second block. Patent applicant Canon Co., Ltd. Figure 2 (A) Figure 2 (B) Image [Sekina Figure 3

Claims (1)

[Scope of Claims] An image memory that stores image data in accordance with a raster scanning method; a first access means that accesses the image memory as a block divided memory by changing a chip enable signal for each block; and a chip enable signal. a second accessing the image memory as a block collective memory by changing the value in the middle of a line or column;
An image processing apparatus comprising: an access means; and a switching means for switching between the first and second access means.