JPH0553898A - Function memory - Google Patents

Abstract

PURPOSE:To execute calculation at high speed in an LSI by constituting memories and plural processors on the same LSI. CONSTITUTION:An orthogonal memory cell 11, row memory 13, row register group 12, row computing element 15, column memory 19, column register group 18 and column computing element 21 are integrated on the same LSI. The row computing element 15 and the column computing element 21 are composed of plural computing elements which are respectively one-dimensionally arranged. The row computing element 15 executes calculation to data on the row register group 12 and can store the result in the row register group 12 again or can transfer data between the adjacent computing elements in the row computing element 15. The column computing element 21 executes calculation to data on the column register group 18 and can store the result in the column register group 18 again or can transfer data between the adjacent computing elements in the column computing element 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a functional memory for processing data such as images at high speed.

[0002]

2. Description of the Related Art There is a part of data processing algorithm that performs the same processing on a large amount of data, but if the data amount is large, it takes a very long time to process with a single processor. In the case of such processing, for example, in the case of image processing, there is a parallel degree corresponding to the number of pixels, and if the parallel degree can be utilized, the processing can be performed at extremely high speed. Therefore, FIG.
, A memory unit 71, an arithmetic processing unit 72 composed of a large number of arithmetic units and a register group arranged one-dimensionally, and a row memory 73 for inputting / outputting row data at high speed on the same LSI. There is an integrated functional memory. In the functional memory, the arithmetic processing unit 72 can process the data held in the memory unit 71 at high speed row by row. Further, the arithmetic unit in the arithmetic processing unit 72 can transfer data with an adjacent arithmetic unit. Further, using the row memory 73, row data can be continuously input and output at high speed sequentially from the end. This system is described in Japanese Patent Application No. 3-119543.

On the other hand, in the case of processing two-dimensional data such as an image, it is necessary to input and output the data at a high speed in the row direction, and those that need to input and output the data at a high speed in the column direction. There is. Therefore, there is a memory called an orthogonal memory as shown in FIG. This is a technique in which data input / output between the outside and the memory cell 81 can be performed at once for the bit width of the memory cell in the row direction and the column direction. This method is described in, for example, the Institute of Electrical Engineers of Japan Electronic Device Study Group material, EDD-85, 36-40, 13
~ Page 20.

[0004]

According to the conventional method, as shown in FIG.
In the case of the functional memory as shown in (1), there is a problem that an operation for each row of an image can be performed at a high speed, but an operation for each column cannot be performed, and that input / output of column data cannot be performed at a high speed. Also, in the case of an orthogonal memory as shown in FIG.
Since there is a feature that data for the width of the memory cell can be input and output in parallel in the row direction and the column direction of the image at high speed,
As shown in FIG. 9, by arranging a large number of processors 92 that perform row-wise processing and a large number of processors 93 that perform column-wise processing outside the memory chip 91, both row-wise and column-wise operations are performed at high speed. Can be done. But,
Since it is necessary to connect a large number of processors to the outside of the memory chip 91, the scale of the device becomes large, and since the number of input / output signal lines increases as the capacity of the memory cell 94 increases, it is practical because of the limitation on the number of pins. There is a problem that it is difficult to realize a capacity orthogonal memory.

An object of the present invention is to solve the above problems, to perform high-speed row-wise processing and column-wise processing, and to perform high-speed input / output of row data and column data. It is to provide a functional memory capable of performing.

[0006]

A functional memory according to a first aspect of the present invention holds data in a functional memory having a memory section and an arithmetic processing section on the same LSI and stores the data in the column direction and the row direction at a time. An orthogonal memory cell capable of transferring data of a bit width, a row register group capable of holding data of a plurality of rows of the orthogonal memory cell, and a means for selecting one row register from the row register group , One or more row memories capable of holding data for one row of the orthogonal memory cells, continuously output data on the row memory from the end, or continuously output data to the row memory from the end. Input means and a plurality of arithmetic units connected in a one-dimensional manner, broadcast an instruction from the outside to all arithmetic units, and process the data held in the row register group in parallel. The result A row arithmetic unit capable of writing data to a group of clusters and transferring data between adjacent arithmetic units, a means for decoding a row address inputted from the outside and selecting one row on an orthogonal memory cell, and an orthogonal memory Transfers data for one selected row on a cell to a row register group or row memory at a time, or transfers one row of data on a row register group or row memory at a time for a selected row on an orthogonal memory cell To a column register group capable of holding data for a plurality of columns of orthogonal memory cells, a means for selecting one column register from the column register group, and data for one column of orthogonal memory cells. One or more column memories that can be held, a means for continuously outputting data on the column memory sequentially from the end, and a means for continuously inputting data on the column memory sequentially from the end, and one-dimensionally. Contact By a plurality of arithmetic units has, broadcast instruction from the outside to all of the arithmetic unit,
A column arithmetic unit that can process the data held in the column register group in parallel, write the result to the column register group, and transfer data between adjacent arithmetic units, and the column address input from the outside. For decoding one column on the orthogonal memory cell and transferring the data for one selected column on the orthogonal memory cell to the column register group or column memory at a time, or the column register group or column memory Means for transferring the data for one column above to a selected column on the orthogonal memory cells at one time.

In the functional memory of the second invention, in the functional memory of the first invention, the data on the row memory is continuously transferred to the column memory sequentially from the end, or the data on the column memory is transferred to the row memory. It is characterized in that it has a means for continuously transferring in order from.

A functional memory according to a third aspect of the present invention is the functional memory according to the first aspect of the present invention, which has a plurality of row memories and column memories and continuously transfers data on an arbitrary row memory to an arbitrary column memory from the end. Alternatively, it is characterized in that it has means for performing parallel transfer between a plurality of row memories and column memories in order to continuously transfer data on an arbitrary column memory to an arbitrary row memory sequentially from the end.

According to a fourth aspect of the present invention, there is provided a functional memory according to the first aspect of the present invention, wherein a selected memory cell on an orthogonal memory cell is selected.
Data for one row is transferred to the column memory at one time, data for one row on the column memory is transferred at one time to a selected row on the orthogonal memory cell, or one selected on the orthogonal memory cell is selected.
It is characterized in that it has means for transferring data for a column to the row memory at a time, or for transferring data for one row on the row memory at a time to a selected column on an orthogonal memory cell.

The functional memory according to the fifth aspect of the present invention is the first, second, and third aspects.
Alternatively, the functional memory according to the fourth aspect of the invention is characterized in that it has means for inputting / outputting data to / from an orthogonal memory element designated by a row address and a column address given from the outside.

A functional memory according to a sixth aspect of the invention is the first, second,
In the functional memory of 3, 4 or 5 invention, an instruction for instructing data transfer between the orthogonal memory cell and the row register group, the row memory, the column register group and the column memory, and the instruction between the row memory and the column memory. Instructions for instructing data transfer, instructions for instructing data transfer between adjacent arithmetic units in row arithmetic units or column arithmetic units, and instructions for instructing operations in row arithmetic units or column arithmetic units Such as a program memory for storing a series of instructions, a means for inputting a program into the bumgram memory, and one instruction stored in the bumgram memory in sequence, and the arithmetic unit operates. It is characterized by having means for instructing or instructing the data transfer circuit to transfer data, means for instructing to start the program from the outside, and means for notifying the end of execution of the program to the outside.

[0012]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the functional memory of the first invention. This functional memory is
An orthogonal memory cell 11 for holding data, a row register group 12 capable of holding data for a plurality of rows of the orthogonal memory cell 11, a row register selection circuit 24 for selecting one row register from the row register group 12, One or more row memories 13 capable of holding data for one row of the orthogonal memory cells 11 are provided, and the data on the row memory 13 are continuously output in order from the end, or the data on the row memory 13 is end. Row memory input / output circuit 14 for continuously inputting in order from 1 to 2, and a plurality of arithmetic units connected in a one-dimensional manner. An instruction from the outside is broadcast to all arithmetic units and held in the row register group 12. Data is processed in parallel and the result is written to the row register group 12 or the data can be transferred between the adjacent arithmetic units. Row decoder 16 for selecting one row on the orthogonal memory cell 11 and transferring data for the selected one row on the orthogonal memory cell 11 to the row register group 12 or the row memory 13 at a time, A row transfer circuit 1 for transferring one row of data in the register group 12 or the row memory 13 to a selected row in the orthogonal memory cell 11 at a time.
7, a column register group 18 capable of holding data for a plurality of columns of the orthogonal memory cell 11, and a column register group 18
Column register selection circuit 2 for selecting one column register from
5 and one or more column memories 19 capable of holding data for one column of the orthogonal memory cells 11, and the column memory 19
A column memory input / output circuit 20 for continuously outputting the above data sequentially from the end or sequentially inputting data to the column memory 19 sequentially from the end, and a plurality of one-dimensionally connected arithmetic units are provided. Then, an instruction from the outside is broadcast to all arithmetic units, the data held in the column register group 18 is arithmetically processed in parallel, the result is written to the column register group 18, and the data is transferred between adjacent arithmetic units. Column calculator 21 capable of performing
And a column decoder 22 for decoding a column address inputted from the outside and selecting one column on the orthogonal memory cell 11.
The selected one column of data on the orthogonal memory cell 11 is transferred to the column register group 18 or the column memory 19 at once, or the one column of data on the column register group 19 or the column memory 18 is orthogonal memory at once. It is composed of a column transfer circuit 23 for transferring to the selected column on the cell 11.

In the functional memory having such a configuration, when the same arithmetic processing is performed on each data on a row in the memory, the processing is performed in the following procedure. First, a row address is given to the row decoder 16 to select a row on the orthogonal memory cell 11, and the row transfer circuit 17 transfers from the orthogonal memory cell 11 to the row register selected by the row register selection circuit 24 in the row register group 12. , Transfer the data to be processed. When the data to be processed extends over a plurality of rows, this is repeated a plurality of times while changing the row register selected by the row register selection circuit 24. Next, the row arithmetic unit 15 executes the row register group 12 in accordance with the instruction sequence given from the outside.
The above data is processed in parallel. Finally, in the row in which the result on the orthogonal memory cell 11 selected by the row decoder 16 is to be stored, the row transfer circuit 17 causes the row transfer circuit 17 to select the operation result on the row register selected by the row register selection circuit 24. To transfer. Thus, the orthogonal memory cell 11
The above data can be processed in parallel on a row-by-row basis by the row calculator 15, and high-speed processing can be easily realized.

When the same arithmetic processing is performed on each data on a certain column in the memory, the processing is performed according to the following procedure. First, a column address is given to the column decoder 22 to select a column on the orthogonal memory cell 11, and the column transfer circuit 23 transfers from the orthogonal memory cell 11 to the column register selected by the column register selection circuit 25 in the column register group 18. , Transfer the data to be processed. When the data to be processed extends over a plurality of columns, this is repeated a plurality of times while changing the column register selected by the column register selection circuit 25. Next, the column calculator 21 operates in parallel on the data in the column register group 18 in accordance with an instruction sequence given from the outside. Finally, in the column where the result on the orthogonal memory cell 11 selected by the column decoder 22 is to be stored, the column transfer circuit 23 causes the operation result on the column register selected by the column register selection circuit 25 on the column register group 18 to be stored. To transfer. In this way, the data in the orthogonal memory cells 11 can be processed in parallel in column units by the column calculator 21, and high-speed processing can be easily realized.

Next, when the data of a certain row on the orthogonal memory cell 11 is continuously output to the outside sequentially from the end, first,
The row decoder 16 decodes the row address given from the outside, selects the row on the orthogonal memory cell 11, and the row transfer circuit 17 transfers the data of the selected row to one of the row memories 13. Then, the row memory input / output circuit 14 continuously outputs the data on the row memory 13 in order from the end.

When row data is continuously input from the outside from the end and is stored in a certain row on the orthogonal memory cell 11, first, the row memory input / output circuit 14 inputs the data from the outside and the row memory 13 is first input. Stored in one of the. Next, the row decoder 16 decodes the row address given from the outside, selects the row on the orthogonal memory cell 11, and the row memory 13
The row transfer circuit 17 transfers the above data to the selected row.

When data in a certain column on the orthogonal memory cell 11 is continuously output to the outside sequentially from the end, first, the column decoder 22 decodes the column address given from the outside, and the column on the orthogonal memory cell 11 is decoded. And the column transfer circuit 23 transfers the data of the selected column to one of the column memories 19. Then, the column memory input / output circuit 20 continuously outputs the data on the column memory 19 sequentially from the end.

When the column data is continuously input from the outside from the end and is stored in a certain column on the orthogonal memory cell 11, first, the column memory input / output circuit 20 inputs the data from the outside and the column memory 19 is inputted. Stored in one of the. Next, the column decoder 22 decodes the column address given from the outside, selects the column on the orthogonal memory cell 11, and the column memory 19
The column transfer circuit 23 transfers the above data to the selected column.

The row memory 13 and the column memory 19 are SR
It is composed of AM or shift register,
In the case of SRAM, the row memory input / output circuit 14 and the column memory input / output circuit 20 access the SRAM while increasing the address one by one. Further, in the case of a shift register, the row memory input / output circuit 14 and the column memory input / output circuit 20 perform data transfer between the shift register and the outside by applying a shift clock. When a shift register is used for the row memory 13 and the column memory 19, the data read from the orthogonal memory cell 11 is shifted by applying a shift clock a proper number of times, and then written to the orthogonal memory cell 11 again, so that adjacent data can be obtained. The same effect as the data transfer between the arithmetic units can be realized.

The above-mentioned arithmetic processing and data input / output processing are
As long as there is no competition for access to the orthogonal memory cells 11, they can all be done in parallel.

Further, a plurality of bits on the orthogonal memory cell 11 constitute one word, and the row register group 12 and the row memory 1
3, the row memory input / output circuit 14, the row arithmetic unit 15, the column register group 18, the column memory 19, the column memory input / output circuit 20, and the column arithmetic unit 21 all have a word configuration, so that processing in word units can be performed. A functional memory can be realized.
FIG. 10 shows an example of the correspondence between the bits of the orthogonal memory cells 11, the row memory 13, and the column memory 19 in the functional memory that performs such word unit processing. 16 bits ×
It is a figure for demonstrating the bit structure of the orthogonal memory cell 101 of a 16-bit structure, the row memory 102 of 8 word structures, and the column memory 103. However, one word has 4 bits. As shown in FIG. 10, the orthogonal memory cell 101 is divided into 2 bits × 2 bits, and the 4 bits are assigned to one word. It is assumed that the order of the bits in the word is assigned in the order of writing on the orthogonal memory cell 101 in FIG.

In the functional memory having such a configuration, the case where the data in the row memory 102 is transferred to the orthogonal memory cell 101 will be described. First, the bit data of all the words in the row memory 102 are transferred at a time to the row assigned to the data of the orthogonal memory cell 101. Next, the data of the bits of all the words on the row memory 102 are transferred to the orthogonal memory cell 1
On the line 01, the line next to the line previously transferred, that is, the line allocated to the data of and is transferred at one time. Thus, the data of all the words in the row memory 102 can be transferred to the orthogonal memory cell 101 by transferring the row twice.

Next, the case of transferring the data stored in the orthogonal memory cell 101 to the column memory 103 will be described. First, of the two columns of the orthogonal memory cell 101 which hold the data to be transferred to the column memory 103,
The column memory 10 which holds the bits of
3 at a time, and store them at the positions of and on the column memory 103. Next, the data of the column holding the bits and are transferred to the column memory 103 at one time, and the column memory 10
Store in the position of 3 and above. In this way, the data in the orthogonal memory cell 101 can be transferred to the column memory 103 by transferring the column twice.

Further, the transfer from the orthogonal memory cell 101 to the row memory 102 and the transfer from the column memory 103 to the orthogonal memory cell 101 are similarly performed. Further, the row register group 12 and the column register group 18 in FIG. 1 can be similarly formed into words.

FIG. 2 is a block diagram showing the configuration of an embodiment of the functional memory of the second invention. This functional memory is
In addition to the configuration of FIG. 1, an inter-matrix data transfer circuit 26 is provided for sequentially transferring data between the row memory 13 and the column memory 19 sequentially from the end.

In the functional memory having such a configuration, the data in the orthogonal memory cell 11 is transferred to the column memory 19,
The data is transferred to the row memory 13 by the matrix data transfer circuit 26.
The column data of the two-dimensional data on the orthogonal memory cell 11 can be converted into the row data by transferring the data to the orthogonal memory cell 11 and then to the orthogonal memory cell 11.

Further, the data in the orthogonal memory cell 11 is transferred to the row memory 13, and the data is transferred between the matrix 26.
To the column memory 19 and then to the orthogonal memory cell 11 to obtain the orthogonal memory cell 1
The row data of the two-dimensional data on 1 can be converted into column data.

In this way, if the column data is converted into row data or the row data is converted into column data, the row calculator 15
A matrix calculation can be performed on the column calculator 21.

The row memory 13 and the column memory 19 to which data is transferred by the inter-matrix data transfer circuit 26 are
Input / output of data by the row memory input / output circuit 14 and the column memory input / output circuit 20 is prohibited. However, the data being transferred is transferred to the row memory input / output circuit 14 or the column memory input / output circuit
It is possible to output to 0 simultaneously with transfer. Also,
The row memory input / output circuit 14 and the column memory input / output circuit 20 input data to the row memory 13 and the column memory 19, and at the same time, the data transfer circuit 26 transfers data to the column memory 19 and the row memory 13. It is also possible.

FIG. 3 is a block diagram showing the configuration of an embodiment of the functional memory of the third invention. This functional memory is
A plurality of row memories 13 and a plurality of column memories 19 are provided, and in addition to the configuration of FIG.
An inter-matrix data transfer circuit 31 for sequentially transferring data from the end to the end 9 is provided.

In the functional memory having such a structure, the inter-matrix data transfer circuit 31 is composed of a crossbar switch, and data can be transferred in parallel by an arbitrary combination of the row memory 13 and the column memory 19.

The data in the orthogonal memory cell 11 is transferred to the column memory 19, the inter-matrix data transfer circuit 31 transfers the data to the row memory 13, and then the data is transferred to the orthogonal memory cell 11. The column data of the two-dimensional data on 11 can be converted into row data.

Further, the data in the orthogonal memory cell 11 is transferred to the row memory 13, and the data is transferred between the matrixes 31.
To the column memory 19 and then to the orthogonal memory cell 11 to obtain the orthogonal memory cell 1
The row data of the two-dimensional data on 1 can be converted into column data.

In this way, if the column data is converted into row data or the row data is converted into column data, the row calculator 15
A matrix calculation can be performed on the column calculator 21.

FIG. 4 is a block diagram showing the configuration of an embodiment of the functional memory of the fourth invention. This functional memory is
In addition to the configuration of FIG. 1, the selected one row of data on the orthogonal memory cell 11 can be transferred to the column memory 19 at once,
The data for one row in the column memory 19 is transferred to the selected row in the orthogonal memory cell 11 at a time, or the data for one column in the orthogonal memory cell 11 is transferred to the row memory 1 at a time.
3 and a matrix parallel data transfer circuit 41 for transferring one row of data in the row memory 13 to a selected column in the orthogonal memory cell 11 at a time.

In the functional memory having such a configuration, the inter-matrix parallel data transfer circuit 41 has a signal line corresponding to the bit width of the orthogonal memory cell 11, and the orthogonal memory cell 11
It is realized by passing the wiring over. While the functional memories shown in FIGS. 2 and 3 transfer data sequentially in order to exchange data between rows and columns, the inter-major parallel data transfer circuit 41 operates in parallel at a time. Data can be transferred.

As described above, since the column data can be converted into the row data and the row data can be converted into the column data at high speed, the matrix operation can be performed at high speed on the row operation unit 15 and the column operation unit 21. be able to.

Further, since the matrix parallel data transfer circuit 41 can transfer data at high speed between rows and columns, the column register group 18, the column register selection circuit 25, and the column memory 1 are provided.
9, the column memory input / output circuit 20, the column calculator 21, and the column data transfer circuit 23 have the functions of the row register group 12, the row register selection circuit 24, the row memory 13, and the row memory input / output circuit 1.
4, the row arithmetic unit 15, and the row data transfer circuit 17 can be realized, and the number of pins and the chip size can be reduced. The structure of such a functional memory is shown in FIG. In the case of the functional memory configured as shown in FIG. 11, the data on the orthogonal memory cell 11 is both row data and column data.
Data is transferred to the outside using the row memory 13 and the row memory input / output circuit 14, and calculation is performed using the row register group 12, the row register selection circuit 24, and the row calculator 15.

FIG. 5 is a block diagram showing the configuration of an embodiment of the functional memory of the fifth invention. This functional memory is
In addition to the configuration of FIG. 1, a data input / output circuit 51 for inputting / outputting data between the bit on the orthogonal memory cell 11 designated by the row decoder 16 and the column decoder 22 and the outside is provided.

In the functional memory having such a configuration, when none of the row register group 12, the row memory 13, the column register group 18 and the column memory 19 is transferring data to and from the orthogonal memory cell 11, it is externally connected. The connected device can randomly access the orthogonal memory cell 11 through the data input / output circuit 51.

FIG. 6 is a block diagram showing the configuration of an embodiment of the functional memory of the sixth invention. This functional memory is
In addition to the configuration of FIG. 1, an instruction for instructing data transfer between the orthogonal memory cell 11, the row register group 12, the row memory 13, the column register group 18, and the column memory 19,
A program memory 61 for storing a series of commands, such as commands for instructing operations in the row calculator 15 and the column calculator 21, and a program memory input circuit for inputting a program to the program memory 61 from the outside. 62 and the instructions held in the program memory 61 one by one in order to instruct the row arithmetic unit 15 and the column arithmetic unit 21 to perform an arithmetic operation, and to operate the row decoder 16, the row transfer circuit 17, and the row register selection circuit 24. , A column decoder 22, a column transfer circuit 23, and a column register selection circuit 25, a sequencer 63 for instructing data transfer, an activation signal line 64 for instructing activation of a program from the outside, and an end signal notifying the end of execution of the program to the outside. A line 65 is provided.

In the functional memory having such a configuration, the instruction sequence of the process to be executed on this functional memory is stored in the program memory 61 on the same LSI through the program memory input circuit 62 in advance, so that the LSI
Since the processing can be performed without continuously giving instructions one by one from the outside, the external circuit configuration is simplified and the functional memory can be used more easily. When the execution of the program is activated through the activation signal line 64, the sequencer 63 sequentially fetches the instructions from the program memory 61,
Depending on the contents of the instruction, the row calculator 15 and the column calculator 2
1, operation instruction is given to the row decoder 16, the row transfer circuit 17, the row register selection circuit 24, the column decoder 22, the column transfer circuit 23, and the column register selection circuit 25. When the execution of a series of instructions is completed, the end signal line 65
Notify the outside of the process. Since the functional memory has the sequencer 63 and the program memory 61 on the same LSI, a higher-speed clock can be used, so that the processing speed can be increased.

[0044]

As described above, according to the present invention, the orthogonal memory cells, the plurality of arithmetic units arranged in one dimension for row operation, and the one-dimensional arrangement for column operation are arranged on the same LSI. By integrating a plurality of arithmetic units, a memory for continuous input / output of row data, and a memory for continuous input / output of column data, the data transfer bandwidth between the memory and the arithmetic units can be increased in columns in the row direction. Since it is possible to take a sufficiently wide range of directions, it is possible to execute an algorithm of the kind in which the same operation is applied to a large amount of data on a row-by-row or column-by-row basis within the LSI in parallel and at high speed. Data can be input and output at high speed in both the column and column directions.
There is an effect that a function of converting the two-dimensional data in the row direction and the column direction can be realized on the LSI.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a functional memory of the first invention.

FIG. 2 is a block diagram showing an embodiment of a functional memory of the second invention.

FIG. 3 is a block diagram showing an embodiment of a functional memory of a third invention.

FIG. 4 is a block diagram showing an embodiment of a functional memory of a fourth invention.

FIG. 5 is a block diagram showing an embodiment of a functional memory of the fifth invention.

FIG. 6 is a block diagram showing an embodiment of a functional memory according to the sixth invention.

FIG. 7 is a block diagram showing a configuration example of a conventional functional memory.

FIG. 8 is a block diagram showing a configuration example of a conventional orthogonal memory.

FIG. 9 is a block diagram showing a configuration example of a conventional orthogonal memory utilization system.

FIG. 10 is a diagram for explaining a bit configuration of an orthogonal memory cell, a row memory, and a column memory on a functional memory.

FIG. 11 is a block diagram showing an embodiment of a functional memory of the fourth invention.

[Explanation of symbols]

 11 orthogonal memory cell 12 row register group 13 row memory 14 row memory input / output circuit 15 row arithmetic unit 16 row decoder 17 row transfer circuit 18 column register group 19 column memory 20 input / output circuit 21 column arithmetic unit 22 column decoder 23 column transfer circuit 24 row register selection circuit 25 column register selection circuit 31 inter-matrix data transfer circuit 41 inter-matrix parallel data transfer circuit 51 data input / output circuit 61 program memory 62 program memory input circuit 63 sequencer 64 start signal line 65 end signal line 71 memory unit 72 Arithmetic processing unit 73 Row memory 81 Memory cell 91 Memory chip 92 Processor 93 Processor 94 Memory cell 101 Orthogonal memory cell 102 Row memory 103 Column memory

Claims (6)

[Claims] 1. A functional memory having a memory section and an arithmetic processing section on the same LSI, which holds data and can transfer data of a bit width at a time in the column and row directions. A memory cell, a row register group capable of holding a plurality of rows of data of an orthogonal memory cell, a means for selecting one row register from the row register group, and a row of data of an orthogonal memory cell One or more row memories that can be used, and the data on the row memories are continuously output from the end,
It has a means for continuously inputting data to the row memory sequentially from the end and a plurality of one-dimensionally connected arithmetic units. It broadcasts instructions from the outside to all arithmetic units and holds them in the row register group. Data is processed in parallel, the results are written to the row register group, and the row address that is input from the outside can be decoded, and the row address that is input from the outside is decoded and orthogonalized. Means for selecting one row on a memory cell and transferring data for one selected row on an orthogonal memory cell to a row register group or row memory at a time, or one row on a row register group or row memory Means for transferring the data of the above to the selected row on the orthogonal memory cell at a time, a column register group capable of holding data for a plurality of columns of the orthogonal memory cell, and one column register selected from the column register group. You Means and, one or more columns memory capable of holding data for one column of the orthogonal memory cell, or continuously output the data on the column memory from the end in order,
It has means for continuously inputting data into the column memory sequentially from the end and multiple one-dimensionally connected arithmetic units, which broadcast instructions from the outside to all arithmetic units and hold them in the column register group. Data is processed in parallel, the result is written to the column register group, and the column address input from the outside is decoded, and the column address input from the outside is orthogonalized. Means for selecting one column on a memory cell and transferring data for one column selected on an orthogonal memory cell to a column register group or column memory at a time, or one column on the column register group or column memory And a means for transferring the data in one row to a selected column on the orthogonal memory cells at a time. 2. A means for continuously transferring the data on the row memory to the column memory sequentially from the end, and for transferring the data on the column memory to the row memory successively from the end. The functional memory according to item 1. 3. A plurality of row memories and column memories are provided, and data in an arbitrary row memory is continuously transferred to an arbitrary column memory in order from the end, or data in an arbitrary column memory is ended in an arbitrary row memory. 2. The functional memory according to claim 1, further comprising means for performing a continuous transfer in sequence from a plurality of row memories and a plurality of column memories in parallel. 4. The data for one selected row on the orthogonal memory cells is transferred to the column memory at a time, or 1 row on the column memory is transferred.
Data for one row can be transferred to a selected row on the orthogonal memory cells at once, data for one selected column on the orthogonal memory cells can be transferred to the row memory at one time, or
2. The functional memory according to claim 1, further comprising means for transferring data for rows to selected columns on the orthogonal memory cells at a time. 5. A means for inputting / outputting data to / from an orthogonal memory element designated by a row address and a column address given from the outside.
Functional memory according to 2, 3 or 4. 6. An instruction for instructing data transfer between an orthogonal memory cell and a row register group, a row memory, a column register group, and a column memory, and an instruction for instructing data transfer between a row memory and a column memory. Command for instructing data transfer between adjacent arithmetic units in row arithmetic units and column arithmetic units,
A program memory for storing a series of instructions such as instructions for instructing operations in the row operation unit and the column operation unit, a means for inputting a program to the program memory, and a program memory Instructions are read out one by one, the arithmetic unit is instructed to perform an operation, the data transfer circuit is instructed to transfer data, the external program is instructed to start, and the execution end of the program is notified to the outside. 6. The functional memory according to claim 1, 2, 3, 4, or 5, further comprising means.