JP2812292B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image processing apparatus, and more particularly to a parallel image processing apparatus for performing high-speed binary image processing.

[0002]

2. Description of the Related Art FIG. 8 shows a configuration of a conventional parallel type image processing apparatus. Referring to FIG. 8, in a conventional parallel-type image processing apparatus, a processor array 100 includes a plurality of one-dimensional processors 200 each including a local memory 3, an arithmetic unit 4, and a register file 5 for storing image data and processing results. The instruction supply circuit 7
A program memory 8, a sequence controller 9,
Consists of

In the processor 200, the register file 5 and the local memory 3 are mutually connected by an address line 11 and a data line 12, and each processor 20
0 is the number of registers in the register file 5
It has an indirect addressing function of accessing the local memory 3 using the contents of the register selected by the instruction as an address.

Each processor 200 accesses the local memory 3 in each processor using the contents of a certain register in the register file 5 as an address, processes the accessed data, and writes the data in the local memory 3 again.
This series of memory access and processing can be executed simultaneously by all processors.

[0005] In image processing, data is not always processed in multi-valued form, and binarized data is frequently processed during processing.
For example, in processing such as expansion, contraction, removal of isolated points, and thinning, binary data is a processing target. In such processing, a value after processing of a processing target pixel is, for example, 3 × It is determined by calculating values of neighboring pixels such as three neighboring pixels.

In the conventional parallel type image processing apparatus shown in FIG. 8, when executing the binary image processing of determining the value of a certain pixel by the pixel value of a neighboring area, the following processing is performed.

First, one processor loads pixel data necessary for processing from a memory (local memory),
Next, by transferring the neighboring data from the neighboring processor, the data of the neighboring pixels is collected on the processor holding the pixel to be processed, and various logical operations are performed on the collected 1-bit data. , The processed value of the pixel to be processed is determined, and finally the data (the processed value) is written to the memory.

In this processing, the collected 1-bit data is bit-packed once for each processor to increase the number of bits, and then the bit-packed data is subjected to a logical operation process, so that the 1-bit data is obtained. In addition, processing can be performed at a higher speed than when performing a logical operation.

In addition, instead of performing a logical operation on the bit pack data, a memory (that is, a table) is accessed using the bit pack data as an address,
In some cases, high-speed processing can be performed by performing a table reference process of reading data (a logical operation result) stored in advance at the address. When performing this table reference processing, a local memory in each processor is allocated to a memory for storing table data, and the allocated memory is accessed by the indirect addressing described above.

[0010]

However, in the above-mentioned conventional parallel type image processing apparatus, the processing time required for bit-packing the binary image data becomes longer,
There is a problem that the realization of high-speed processing is prevented. This is because the neighboring pixel value is transferred between processors.
The bit data is transferred one bit at a time, and the collected pixel data is brought to a desired bit position by a shift operation or the like, then a logical operation is performed, and bit packing is performed. To pack a bit,
By requiring many operations.

In the above-described conventional parallel type image processing apparatus, when the same table data is used in each processor, the same table data is provided for each processor, and the local memory is wastefully consumed. Has the problem that

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a parallel image processing apparatus capable of performing binary pixel processing at a higher speed than a conventional apparatus. To provide.

[0013]

According to one aspect of the present invention, there is provided an image processing apparatus comprising a plurality of processors arranged in an array. And a means for bit-packing data in a predetermined register of the proximity processor and data in a predetermined register in each of the processors.

According to the present invention, in the bit pack operation, the processor shifts data between registers for storing data used for the bit pack,
There is provided means for reading data used in the next bit pack processing from a memory to a register.

In the present invention, a memory having one write port and a number of read ports equal to the total number of processors or the number obtained by dividing the total number of processors by a predetermined positive number is provided as a table reference memory. It is characterized by.

The principle and operation of the present invention will be described below. The present invention relates to a program-executable parallel image processing apparatus in which a processor array including a plurality of processors can execute read / write of data of an image row unit at a time with respect to an image memory. Means for bit-packing the binary image data in block units, and further, means for loading the next data to be bit-packed from the memory simultaneously with the bit-packing, that is, preferably in the same instruction cycle as the bit-packing. With this arrangement, the speed of the bit pack operation is increased, the increase in the circuit scale is suppressed, and high-speed image processing can be performed on the binary image data. Further, a memory having a one-write / multi-read port configuration is used as a memory used for a table reference process using bit-packed data, and can be read from all processors, so that a local memory of each processor is used as a table memory. As compared with the case, the memory usage can be greatly reduced.

[0017]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram showing the configuration of an embodiment of the image processing apparatus of the present invention.

Referring to FIG. 1, processor array 1 includes:
A plurality of one-dimensionally connected processors 2 each including a local memory 3, an arithmetic unit 4, a register file 5, and a bit pack block 6 for performing bit pack processing. 1, an instruction supply circuit 7 includes a sequence controller 8 and a program memory 9, reads instructions from the program memory 9 according to a program address generated by the sequence controller 8, and stores the read contents in a processor. Supply to array 1 as instructions. The host processor 10 loads data into the program memory 9 and the local memory 3 and the like.

The image processing apparatus according to the present embodiment is an apparatus capable of executing a program, and is a single instruction multi-function (SIMD) operating all processors 2 (processor elements, also referred to as “PEs”) with the same instruction stream.
ple data stream (single instruction multiple data control) type parallel image processing apparatus. This image processing apparatus has an instruction set such as an arithmetic and logic operation instruction, a shift instruction, a flag operation instruction, a data transfer instruction between PEs, and a load / store instruction.

FIG. 2A shows a 3 × 3 neighborhood area with P (i, j) as the center pixel when the pixel at the j-th row and i-th column of the image is P (i, j). FIG. Now, it is assumed that the data of one column of the image is dispersedly stored for each pixel in the local memory 3 of each processor 2. That is, the i-th processor 2 proceeds with the process while storing the data of the i-th column of the image in the local memory 4. Hereinafter, the processor 2 is represented by PE (processor element), the local memory is represented by M, the total number of processors is represented by n, and the number of the processor element PE is represented by i.
E is PE (i), j-th local memory of the i-th PE
Let the row be represented by M (i, j).

Assuming that the data of the j-th row of the image is stored in the j-th row of the local memory, the local memory M
(I, j) holds the pixel P (i, j).

Now, the i-th processor element PE
If the pixel to be processed in (i) is P (i, j), P
The neighboring 3 × 3 pixels centered at (i, j) are represented by P (i−
1, j-1), P (i, j-1), P (i + 1, j-
1), P (i-1, j), P (i, j), p (i + 1,
j), P (i-1, j + 1), P (i, j + 1), P
(I + 1, j + 1). In FIG. 2, the center pixel P (i, j) is P (k, m), i.e., i = k, j = m
As shown.

As shown in FIG. 2B, a case where eight pixels excluding P (i, j) which is a processing target pixel (center pixel) from these nine pixels are bit-packed into 8-bit data will be described below. Give an explanation.

FIG. 3 is a diagram showing a configuration for performing a bit pack process in a 3 × 3 area. The register of the processor element PE (i) for performing the bit pack process and the PEs (i−1) on both sides thereof are shown. And the connection relationship between PE (i + 1) and PE (i + 1). In FIG. 3, the number i is shown as k.

In PE (i), when bit packing of a 3 × 3 area is performed, P (i−1, j−1), P (i−1, j), P (i−1, j), P (i-
1, 3-bit data of P (i + 1, j−1), P (i +) from the processor PE (i + 1) on the right side.
The PE (i) needs 3-bit data of (1, j) and P (i + 1, j + 1). Similarly, the left P
E (i-1) converts the data of 3 bits each from PE (i-2) and PE (i) to PE (i + 1) on the right side.
Requires data of 3 bits each from PE (i) and PE (i + 2).

That is, for PE (i), a data input line of 3 bits and a data output line of 3 bits are provided from the left and right processors PE (i-1) and PE (i + 1).

Since such a configuration is common to all PEs, each PE has a 6-bit data transfer line 20 consisting of a 3-bit data input line and a 3-bit data output line for the bit pack. It shall be provided at the connection with.

Each PE has r1, r2, and r3.
It has one 1-bit register 21, and these three registers are configured to be directly referable from adjacent PEs.

For this reason, without performing data transfer between adjacent PEs by a data transfer instruction, each PE stores the three 1-bit registers r1, r2, and r3 of the adjacent PEs.
It can be used as a source (transfer source). That is, at the time of bit pack processing, the three 1-bit registers r1, r2, and r3 of the PEs on both sides can be specified as source operands in a register or a memory at the transfer destination (destination) of the own PE.

Further, as shown in FIG. 3, the 1-bit registers r1 to r3 are configured so that the selector 22 can perform a 1-bit logical left shift and a 1-bit logical right shift in each PE. I have. Where PE
The 1-bit registers r1, r2, and r3 in (i) are r1 (i), r2 (i), and r3 (i), respectively.

First, in response to a load instruction for the data in the (j-1) th row of the memory, the data in the (j-1) th row is transferred from the memory to the processor array to r1 of each PE.

Next, similarly, by a load instruction,
The data of the j-th row and (j + 1) -th row of the memory are transferred to r2 and r3 of each PE.

At this point, the 1-bit register r1 (i) of PE (i) stores M (i, j-1), and r2 (i) stores
M (i, j) and r3 (i) hold M (i, j + 1).

When a bit pack instruction is performed with the destination register 23 of PE (i) set to rd (i), the MSB (bit 7) of rd (i) is changed to LSB.
In the order of (bit 0), r1 (i-1), r1 (i), r
1 (i + 1), r2 (i-1), r2 (i + 1), r3
The contents of (i-1), r3 (i), and r3 (i + 1) are stored.

As a result, of the binary data in the 3 × 3 pixel area centered on the central pixel P (i, j), the data of eight pixels excluding the central pixel P (i, j) is rd (i). ) Is stored as a bit packed.

The above-mentioned bit pack processing is performed by
(I): 1 ≦ i among n PEs of 0 ≦ i ≦ n−1}
It is executed simultaneously in PE (i) in the range of ≦ n−2.

Exception processing is performed for the PEs at both ends of the one-dimensional processor array 1. FIG. 4 is a diagram for explaining the operation of the bit pack processing at the PEs at both ends.

PE (0) and PE at both ends of a processor array consisting of a one-dimensional array of n processor elements
For (n-1), PE (-1), PE
Since (n) does not exist, depending on the application, PE (0)
And PE (n−1) are regarded as adjacent PEs, and data is required. When it is necessary to input “0” as data from the PE direction where no adjacent PE exists, the adjacent PE
In the case where it is necessary to input "1" as data from the PE direction in which no data exists, there are three typical cases.

Therefore, in the present embodiment, one of the three modes described above is set in advance in the mode register 25 by an instruction in the mode register 25, and the set 2-bit value is used as a selection signal. Selector 24 selects the value of 1-bit register r1, r2, r3 of PE (n-1) or "0" or "1" for PE (0). Similarly, the selector 24 using the output from the mode register (m1) 25 as a selection signal causes the 1-bit register r of PE (0) to
The value of 1, r2, r3, “0” or “1” can be selected.

When the bit pack processing of the 3 × 3 pixel area centering on each pixel of the j-th row is completed and the processing is performed for the next (j + 1) -th row, the j-th row and the next (J
+2) Row data is required.

The data of the j-th row and the (j + 1) -th row are already held in the 1-bit registers r2 and r3, respectively, and can be used, and the data stored in the 1-bit register r1 can be used. The data in the (j-1) th row becomes unnecessary. Here, the (j +)
2) When the row data is transferred to the 1-bit register r1,
In the first bit pack process, the center pixel is set to r2, the (number of rows of center pixel−1) row is set to r1, and the (number of rows of center pixel +
1) The row is held in r3, but in the next bit pack processing, the center pixel is set to r3 and (the number of rows of the center pixel -1)
The row is held at r2, and the row (the number of rows of the center pixel + 1) is held at r1.

In order to perform bit pack processing using r1, r2, and r3, r2 (i) is used in order from the MSB (most significant bit) of the destination register rd (i) to the LSB (least significant bit). -1), r2 (i), r
2 (i + 1), r3 (i-1), r3 (i + 1), r1
It is necessary to store the contents of (i-1), r1 (i), and r1 (i + 1), and a register different from the first bit pack processing is stored in each bit position of rd (i). Become.

Further, regarding the bit pack processing of the 3 × 3 pixel area centered on the next (j + 2) -th row, the bit pack processing of the 3 × 3 pixel area centered on the j-th row and the (j + 1) -th row is also performed. Processing different from the processing is required.

As a circuit for realizing the three types of bit pack processing, one-bit registers r1 and r1 are used to obtain the result of each bit position of the bit pack data.
A three-input one-output selector circuit for selecting one from 2, r3 is provided with eight bits corresponding to one word (8 bits) to be bit-packed.
Need pieces.

Here, the case of the 3 × 3 pixel area has been described. However, in general, when the bit pack processing of the pixels excluding the center pixel of the m × m pixel area is performed by the above-described processing method, m types of bits are required. Pack instruction and (m ² -1) m
An input / output selector circuit is required (this is referred to as "method A"), and the number of necessary instructions and the circuit scale are increased.

In the present embodiment, in order to solve this problem, within the same instruction cycle as the bit pack processing,
The contents are transferred between the 1-bit registers r1, r2, and r3 of each PE, and data necessary for the next processing is read from the memory. More specifically, three types of bit pack instructions are prepared. One is to copy r1 ← r2 and r2 ← r3 at the same time as the above bit pack operation, and to transfer the data in the memory to r3. The other is a “pack & shift up & load instruction”, and the other is r1 → r2, r2 → r simultaneously with the above bit pack operation.
3 is a "pack & shift down & load instruction" for transferring data in the memory to r1, and the other is a "pack instruction" for performing only the above-described bit pack operation. These are used properly according to the processing purpose.

FIG. 5A is a diagram showing the number of rows stored in a register after execution of a "pack & shift up & load instruction" when processing is performed while increasing the processing in the row direction of the image. It is.

In the "pack & shift up & load instruction", when processing is performed while increasing in the row direction of the image, data of the next row is set to 1 at the same time as bit packing.
The data is loaded into the bit register r3, and the register r1 always stores the data of the row (row-1 of the pixel to be processed) in the register r2.
Represents the data of the row of the pixel to be processed, and the register r3 stores the data of the row of the pixel to be processed + 1. For this reason,
The next “pack & shift up & load instruction” can be executed immediately.

FIG. 5B is a diagram showing the number of lines stored in the register after execution of the "pack & shift down & load instruction" when the processing is advanced while decreasing in the line direction of the image. It is.

In the "pack & shift down & load instruction", when processing is performed while decreasing in the row direction of the image, data of the next row is loaded into the register r1 at the same time as bit packing, and the register r1 is always ( The data of the row of the pixel to be processed-1) is stored, r2 is the data of the row of the pixel to be processed, and r3 is the data of the row of the pixel to be processed + 1. For this reason, the following “Pack & Shift down &
Load instruction ”can be executed immediately. Further, the register r
The relationship between the rows of data stored in 1, r2, and r3 and the rows of the pixels to be processed is the same as in the case of the “pack & shift up & load instruction”, and is used as table data when performing table reference processing. Can be the same.

In the present embodiment, when performing bit pack processing of a 3 × 3 pixel area, there are three types of instructions, which are the same as those in the method A. However, in terms of circuit, three three-input one-output selectors are used. Only requires a small circuit size.

In the circuit for performing the bit pack processing of the m × m pixel area, at the same time as the bit pack processing, in the “pack & shift down & load instruction”, r1 ← r2, r2
← r3,..., R (m−1) ← rm and then load the data in the memory to rm. In the “pack & shift up & load instruction”, r1 → r2, r2 → r
3,..., R (m-1) → rm, and the data in the memory may be loaded into r1.

Therefore, only three bit pack instructions are required, which is the same as the case of the bit pack processing of the 3 × 3 pixel area. Regarding the circuit, in the case of the method A for the bit pack processing of the mxm pixel area, m three-input one-output selector circuits are required in comparison with the necessity of (m ² -1) m-input one-output selector circuits. Only an output selector is required, and the required number of instructions and the circuit scale can be greatly reduced.

FIG. 6 is a diagram showing the configuration of the second embodiment of the present invention. Compared with the embodiment shown in FIG. 1, in this embodiment, a table memory 13 which can be read from all processors simultaneously and which can be written by the host processor 10 or one processor 2 of the processor array 1 is added. Have been.

When the expansion processing is performed on a binary image, if the generated bit pack data is not “0”, at least one of the eight neighboring pixels is “1”. The pixel to be processed may be set to “1”.

This is one of the simplest logical operations on bit pack data, and if such a simple logical operation is sufficient, no table is required.

On the other hand, if the processing cannot be performed by a simple logical operation, a table reference method in which table data storing processing results calculated in advance is prepared based on the value of bit pack data is effective. . In order to execute the table reference method, the processing result for the bit pack data is stored in the memory as a table at the address corresponding to the content of the bit pack data at the time of downloading the program or before executing the table reference method. Write it down.

In the table reference processing, the processing result is read from the memory by accessing the table memory by indirect addressing using the bit pack data as an address. The bit pack data in the 3 × 3 pixel area is 8 bits, and the possible values are “0” to “2”.
Since there are 256 ways up to "55", in this case, it is sufficient that the table reference memory has 256 words.

In order to execute a table reference operation in a plurality of PEs, a table reference memory for the number of PEs is required. However, in many cases, the contents of the table may be common, and the table is required for each PE. This configuration has poor memory use efficiency.

Therefore, in this embodiment, as shown in FIG. 6, only one table memory 1 is provided for all PEs.
3 so that all PEs can access the table at the same time.

In this case, as shown in FIG. 7, as the table memory 13, one memory cell 30
Only one write port 31 and one read port 32 for the number of PEs (c = n), that is, one memory having n read ports 32 may be prepared.

The write port 31 is connected to the host processor 10, the controller 8, or a specific PE via a write address line and a write data line, and writes data to the memory cell 30 from any of them.

Each of the n read ports 32 is individually connected to the n PEs via its own read address line and read data line. With this configuration, all PEs share the memory cells of the table memory, and even when the parallelism is high, the increase in the circuit area (chip area) can be minimized. On the other hand, if there is a margin in the chip area, it is possible to integrate a larger-capacity table memory, or to integrate a plurality of table memories.
The size of one word of the table memory can be increased, and a plurality of table data can be held at the same time, so that the use of the table reference processing can be expanded.

When the number of read ports of the memory is limited from the viewpoint of circuit or chip layout, one table memory may be allocated to some PEs instead of all PEs. For example, if the total number of PEs is 64
If one table memory is assigned to each of the eight PEs, the table memory should have one write port and eight read ports.

[0065]

As described above, according to the present invention,
In a parallel image processing device incorporating many processors,
Each processor is provided with m 1-bit registers, and these registers can be referred to by an adjacent processor. Each of the processors has m bits of data from a processor within (m-1) / 2 PE and its own. Allocating (m ² -1) bits together with the (m-1) bits of the register to a bit position corresponding to the register to be stored,
² -1) bits register to be stored in bit-packed, yet at the same time between the m 1-bit register,
High-speed image processing is possible for binary image data by shifting the data and loading the next data from the memory to the end processor to which no data is sent during the shift. Can be executed.

Further, according to the present invention, a memory having a one-write / multi-read port configuration is used as a memory used for table reference processing using bit-packed data, and can be read from all processors. Compared with the case where the local memory of the processor is used as the table memory, the memory usage can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining bit pack processing near 3 × 3 of a binary image;

FIG. 3 is a block diagram illustrating a configuration of a bit pack block in the image processing apparatus according to the embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a bit pack block in processors at both ends of the image processing apparatus according to the embodiment of the present invention;

FIG. 5 is a diagram for explaining a bit pack instruction used in the image processing apparatus according to the embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of an image processing apparatus according to another embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a table memory in an image processing apparatus according to another embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration of a conventional image processing apparatus.

[Explanation of symbols]

 Reference Signs List 1 processor array 2 processor 3 local memory 4 arithmetic unit 5 register 6 bit pack block 7 instruction supply circuit 8 sequence controller 9 program memory 10 host processor 11 address line 12 data line 13 table memory 20 data transfer line 21 1-bit register 22 selector 23 Destination register 24 selector 30 memory cell 31 write port 32 read port 100 one-dimensional processor array 200 processor

Claims (4)

(57) [Claims] 1. An image processing apparatus comprising a plurality of processors provided in an array, wherein each processor is capable of directly referring to data in a predetermined register of a proximity processor, and the data in a predetermined register of the proximity processor is provided. Means for bit-packing data in a predetermined register in each of the processors. 2. The processor according to claim 1, wherein the processor shifts data between registers storing data used for the bit pack and reads data used for the next bit pack process from the memory to the register in the bit pack operation. 2. A parallel image processing apparatus according to claim 1, further comprising: means. 3. A memory having one write port and read ports having the same number as the total number of processors or a number obtained by dividing the total number of processors by a predetermined positive number, as a table reference memory. Claim 1 or 2
A parallel image processing apparatus as described in the above. 4. A parallel image processing apparatus in which a plurality of processors each including a local memory, an arithmetic unit, a register, and bit pack means for performing bit pack processing are connected in an array, wherein each of the processors The data of a predetermined register holding the pixel information of the processor can be directly referred to, and the predetermined register of the neighboring processor and the register used for the bit pack in the own processor are set as transfer sources (sources). ), The data is shifted between registers that store the data used for the bit pack, and the data used in the next bit pack process is loaded from the local memory to the register. Means for parallel image processing.