JP4537420B2 - SIMD type microprocessor - Google Patents

Description

  The present invention relates to a single instruction-stream multiple data-stream (SIMD) type microprocessor that performs the same processing on a plurality of data with a single instruction in order to process image data or the like at high speed, and in particular, a neighborhood operation of a processor element. The present invention relates to a SIMD type microprocessor that performs (adjacent processing).

  In recent years, in image processing such as digital copying machines and facsimile machines, image quality has been improved by increasing the number of pixels and diversifying image processing. In such image processing, the same processing is often performed for a plurality of data, and a single instruction-stream single data-stream (SISD) type microprocessor that processes one piece of data with one instruction. A SIMD (Single Instruction-stream Multiple Data-stream) type microprocessor that frequently processes a plurality of data is often used.

  The SIMD type microprocessor 2 includes a global processor 4, an operation array 6, and a register file 8 as shown in FIG. FIG. 5 is simplified for explaining the flow of data, and the processor element group 10 in FIG. 5 is a collection of processor elements (PE).

  In the present specification, for the sake of convenience, a description is given of a configuration having 256 processor elements. The configuration of each processor element will be described later.

  For example, image data input from an external input device such as a scanner or a camera is written to the register file 8, and image processing including logical arithmetic operation is performed by the arithmetic array 6, and is written to the register file 8 again. And output to an external output device such as a printer / storage device. The global processor 4 decodes the program and transmits a control signal to the register file 8 and the arithmetic array 6. The global processor 4 also performs arithmetic processing, data transfer, sequential processing, etc. in the global processor itself.

  FIG. 6 is a prior art example showing the processor element (PE) 12 of FIG. 5 in more detail. In FIG. 6, 256 processor elements 12 from PE [0] to PE [255] are prepared. Each processor element is numbered with an ordinal number of 0 to 255 as a “PE number”. In the present specification, numbers are assigned sequentially from the left side of each drawing.

  One processor element 12 includes a register 14 and an arithmetic unit centering on an ALU (arithmetic logic unit) 16. For example, 32 registers R0 to R31 are prepared, and some of the registers 14 are connected to an external input / output. The registers R0 to R31 are connected to a shift / expansion unit 18 that shifts / expands data, and are latched in the second storage unit 22 as data on one side of the ALU 16. The data on the other side of the ALU 16 is obtained by latching the value of the A register 24 provided in the arithmetic unit in the first storage unit 20. In the example of FIG. 6, the size of one register is 8 bits. Further, 24 registers R0 to R23 of the registers are connected to an external input / output. The registers 14 to the shift / extension unit 18 are 8 bits, and the shift / extension unit 18 expands the 8 bits to 16 bits. Are output to the storage unit 22. Therefore, the ALU 16, the A register 24, and the first storage unit 20 have 16 bits correspondingly.

  The data flow in FIG. 6 is roughly as follows. First, the 8-bit image data transferred from the external input to the R register 14 is expanded or shifted to 16-bit data by the shift / extension unit 18, transferred to the second storage unit 22, and subjected to data processing by the ALU 16. Is done. As a result, the data written to the A register 24 is written from the shift / extension unit 18 to the R register 14 and output to the external output.

  Further, in the prior art example of FIG. 7, the path between the R register 14 and the shift / expander 18 can be set between the R register 14 and the shift / expander 18 within the range of adjacent processor elements. Yes. 7 shows the ALU 16, the first storage unit 20 and the second storage unit 22, and the A register 24 together. Here, if the PE of interest is “PE [n]”, the computing unit 26 of PE [n] performs data communication with the R register 14 of PE [n], and the left PE (PE [n] -1]), two left PEs (PE [n-2]), three left PEs (PE [n-3]), one right PE (PE [n + 1]), two right PEs Data communication can be performed with the R registers 14 of a total of seven PEs (PE [n + 2]) and three right PEs (PE [n + 3]). At this time, a bus selector is necessary. In the prior art example of FIG.

  In this specification, data communication between the R register 14 and the arithmetic unit 26 in the adjacent PE is referred to as “PE shift”. Generally, it is also called a neighborhood operation (adjacent processing).

  Image processing using PE shift includes MTF (Modulation Transfer Function) correction and flare data removal.

  The above MTF correction is a correction realized by calculating an emphasis component of peripheral pixels excluding the target pixel, multiplying the result by the intensity magnification, and adding the result to the target pixel. In the filter matrix of 3 lines × 5 pixels as shown in FIG. 8, the pixel of interest at the center is d21, the MTF filter coefficient is M00 to M42, the intensity magnification is mag, the matrix of input pixel data to the filter is d00 to d42, When the output is mtfo, the MTF correction calculation is expressed by the following equation.

mtfo = d21 × M21 +
mag × (d00 × M00 + d10 × M10 + d20 × M20 + d30 × M30 + d40 × M40 + d01 × M01 + d11 × M11 + d31 × M31 + d41 × M41 + d02 × M02 + d12 × M12 + d22 × M22 + d32 × M33 + d42 × M42)

  The flare data removal is a process for removing flare light (light other than diffused light reflected from the document surface) generated by reading with a scanner or the like. In the region of 3 lines × 5 pixels shown in FIG. 9, the values of pixels having a value less than the threshold value T are integrated and divided by the number of pixels N to obtain an average value (flare correction amount). Is subtracted from the target pixel data.

  All of the above operations are operations that need to refer to data before and after the pixel of interest. The filter is exemplified by 3 lines × 5 pixels, but there are also filters in a matrix range of 5 lines × 7 pixels or more.

  Usually, the processing of one instruction in the SIMD type microprocessor is referred to as “1 SIMD”. For example, in the case of a digital copier, the image processing of one original is performed by multiplying the number of pixels in one line of the original by the number of pixels that can be processed by “1 SIMD” and the total number of times “SIMD” calculated by multiplying the number of lines. Is done by. Also, the line direction is generally referred to as the main scanning direction, and the vertical direction is referred to as the sub-scanning direction. Therefore, when processing in the main scanning direction is performed, it is efficient if data can be processed continuously by “1 SIMD” as shown in FIG.

  However, when neighboring pixel data is referred to as in the above-described processing, several data at the both ends of “1 SIMD” data (this number is determined by the number of pixels of the filter) are overlapped as shown in FIG. It must be imported and referenced in the form. Needless to say, the processing efficiency is better when there is no overlap.

By the way, in the following Patent Document 1, Patent Document 2, Patent Document 3 and Patent Document 4, the improvement of the neighborhood operation (adjacent processing) is aimed at, but it does not solve the above-described problem of overwrap. .
JP-A-11-15801 Japanese Patent No. 2756257 Japanese Patent No. 2812292 JP 2002-247347 A

  An object of the present invention is to eliminate the above-described overlap and efficiently process data when a single line is processed by a plurality of “SIMDs” in a SIMD type microprocessor.

The present invention has been made to achieve the above object. According to the first aspect of the present invention, there is provided a SIMD type microprocessor.
A global processor including sequential units, and max processor elements, each processor element is numbered in order from 0 to (max-1) ordinal,
Each processor element further includes an arithmetic unit for processing data and a plurality of registers connected to the input / output bus of the arithmetic unit.
With respect to processor elements within a predetermined first number range as viewed from both ends of the processor element arrangement, the i-th (i is a natural number and 1 ≦ i ≦ (first number)) processor element from the end The bus is connected from the processor element at the opposite end to the ((first number) -i) -th processor element by a path across each bus and a selector,
In the processor elements other than the processor elements within the first number range when viewed from both ends of the processor element arrangement, the buses of the processor elements adjacent to the left and right within the first number range centering on the respective processor elements , Connected by route,
The processor elements at both ends of the processor element arrangement are arranged in the vicinity,
Furthermore,
A register control signal sent from the sequential unit to each processor element is a pair in all the processor elements, and one signal indicating a register selection mode included in the register control signal is prepared.
Each of the processor elements within a predetermined first number range as viewed from both ends of the processor element arrangement includes a register selection changing device,
For the processor elements within a predetermined first number range when viewed from both ends of the processor element arrangement, the register selection changing device is within the first number range when viewed from both ends of the processor element arrangement according to the selection mode. A register different from a processor element other than the processor element can be selected .

  By using the present invention, the following effects can be obtained.

  First, in image processing with a large number of pixels in one line, extra overhead can be reduced.

  By making the arrangement of the processor elements into a mirror arrangement, the distance between the processor elements at both ends can be reduced, thereby preventing a reduction in speed due to wiring delay.

    DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will be described below with reference to the drawings.

<< First Embodiment >>
FIG. 1 is a block diagram of a processor element 12 according to the first embodiment of the present invention. FIG. 1 particularly shows the processor elements 12 at both ends of the processor element group 10.

  In the first embodiment, the bus connection for PE shift is changed in addition to the prior art example of FIG. That is, the PE shift selector 30 is newly set.

  Normally, the PE shift buses of the PEs 12 at both ends are inputted with a specific value, for example, “0” is connected by GND connection.

  In FIG. 1, the specification allows data communication between up to three processor elements on the left and up to three processor elements on the right. This number may be increased or decreased. In FIG. 1, it is possible to select from seven (PE) including its own processor element. Although not shown in FIG. 1, the bus size of the register 14 and the shift / extension / bus selector 28 'is 8 bits.

  PE [253], PE [254], PE [255] and PE [0], PE [1], and PE [2] are connected by the PE shift selector 30 so that data communication as shown in FIG. Is possible. In FIG. 12, “target PE” indicates a PE in which the notable calculator 26 exists, and “data transferable PE” indicates a register to which data is read / written by connecting to the notable PE calculator 26. Indicates the PE to which. L3 is 3 neighbors to the left from the PE of interest, L2 is 2 neighbors to the left, L1 is 1 neighbor to the left, C is its own PE, R1 is 1 neighbor to the right, R2 is 2 neighbors to the right, R3 is Three neighbors on the right.

  For example, in FIG. 12, the PE [254] bus is connected to PE [251], PE [252], and PE [253] on the left side, and PE [255] and PE shift selector 30 on the right side. [0] and also connected to PE [1] via the PE shift selector 30. The PE shift selector 30 selects “0” or “0FFh” (all bits “1”) (not PE [0] or PE [1]).

  The PE shift selector 30 is connected to PE [253], PE [254], PE [255], PE [0], PE [1], and PE [2]. These three PE shift selectors at both ends are in the block of each PE 12 (in FIG. 1, they are placed outside the block for convenience of explanation). The control signal of the PE shift selector 30 is supplied from the SCU 5 of the global processor 4. The PE shift selector 30 controls the selection of the opposite PE by a control signal (“0”, “1”). If “0” is set, all bits are 0, so there is no problem if connected to GND. If “0ffh” is set, since all bits are 1, VCC connection is sufficient. The PE shift selector 30 includes a selector, which may be a 2-bit select signal and a 3-to-1 multiplexer.

  The “opposite side” is PE [253], PE [254], or PE [255] when PE [0] is targeted. When PE1 is targeted, PE [254] or PE [255]. When PE2 is targeted, PE [255]. On the other hand, when PE [255] is targeted, it is PE [0], PE [1] or PE [2]. When PE [254] is targeted, it is PE [0] or PE [1]. When PE [253] is targeted, PE [0].

  FIG. 2 shows control signals of the register 14 in the first embodiment. The control signal of the register 12 is sent from the sequential unit (SCU) 5 of the global processor 4 to each PE as shown in FIG. The sequential unit 5 decodes a program written in the memory of the global processor 4, sends a control signal to the global processor 4 and the processor element 12, and moves each block.

The register is selected by the first register selection signal 32 and the second register selection signal 34. The first register selection signal 32 is sent to the registers 12 of PE [3] to PE [252], and the second register selection signal 34 is sent to PE [0] to PE [ 2 ], PE [253] to PE [255]. Here, the register selection signals (the first register selection signal 32 and the second register selection signal 34) are a set of a plurality of selection signals. In other words, if there are 32 registers in each PE, one register is required for the reading process and the writing process, so at least 64 control signals are required for each register selection signal.

  For example, in FIG. 7, one line of data is loaded from the external input / output of FIG. 6 in order of “1 SIMD” from the left. Here, the first “1 SIMD” data is loaded into R 1, the second “1 SIMD” data is loaded into R 2, and the third “1 SIMD” data is loaded into R 3. In other words, for example, if R1 is data to be processed at present, data of “SIMD” before and after “1 SIMD” of data to be processed is always placed in another register. In other words, data for the previous SIMD that was previously loaded by R1 is stored in R0, and data for the next SIMD that will be loaded by R1 next time is stored in R2.

  Here, in a certain filter process, for example, data is referred to from the R1 register of the PE whose PE number is larger by 1, and the data is calculated with the value of the A register 24 in the calculator 26 of each PE, and the result is stored in the A register 24 And store it in That is, the PE [0] A register 24 is PE [1] R1, the PE [1] A register 24 is PE [2] R1, and so on, from PE [0] to PE [254]. The A register 24 calculates the value of R1 from PE [1] to PE [255].

  Here, if the A register 24 of the PE [255] calculates the value of the R2 of the PE [0], the calculation of the same requirement as the other PEs is performed, and the first embodiment is used. This is easily possible. To perform this operation, a register may be specified by an instruction. The specification of the instruction is to change the register when referring to the PE exceeding the range of “1 SIMD” (that is, when referring to the PE on the opposite side).

  Further, when referring to the data of the previous SIMD, for example, the data is referred to from the R1 register of the PE of [PE number-3], and is operated with the A register 24 in the calculator 26 of each PE, and the result is A A case where data is stored in the register 24 is assumed. That is, PE [3] A register 24 is PE [0] R1, PE [4] A register 24 is PE [1] R1, and so on, from PE [3] to PE [255]. The A register 24 calculates the value of R1 from PE [0] to PE [252]. Here, if the A register 24 of PE [0] calculates the value of R0 of PE [253], it will perform the same calculation as other PEs and use the first embodiment. This is easily possible. Similarly, the A register 24 of PE [1] operates with the value R0 of PE [254], and the A register 24 of PE [2] operates with the value R0 of PE [255].

  In the first embodiment, the first register selection signal 32 and the second register selection signal 34 are set. Further, although not shown, one signal indicating the register selection mode is prepared from the SCU 5, and the register selection is changed to each block of PE [0] to PE [2] and PE [253] to PE [255]. A device is added, and register control signals are paired for all PEs. In the PE [0] to PE [2] and PE [253] to PE [255] blocks, the registers selected by other PEs are selected according to the selection mode. A different register may be selected.

<< Second Embodiment >>
In the second embodiment, as will be described below, the arrangement of the processor elements is devised. The other configuration is the same as that of the first embodiment.

  When the processor element 12 is laid out on the wafer, the bus wiring between PE [0] to PE [2] and PE [253] to PE [255] is very long if the layout arrangement shown in FIG. Become. Then, wiring resistance increases, delay increases, and becomes a decisive factor of fatal speed deterioration of PE shift. Between the other PEs, the wiring delay of the adjacent processing is equal.

  FIG. 4 shows an arrangement of processor elements according to the second embodiment of the present invention. The first half and the second half of all the processor elements are divided into two, and the mirror arrangement is adopted. In this way, the wiring delay of the adjacent processing is substantially equal in all the processor elements.

It is a block diagram of a processor element concerning a 1st embodiment of the present invention. The control signal of the register | resistor in 1st Embodiment is shown. 3 is an arrangement of processor elements according to the present invention. It is arrangement | positioning of the processor element which concerns on the 2nd Embodiment of this invention. It is a schematic block diagram of a SIMD type microprocessor. FIG. 6 is a block diagram illustrating the processor element of FIG. 5 in more detail. It is a block diagram of the processor element which concerns on a prior art. It is a schematic diagram which shows MTF correction | amendment. It is a schematic diagram which shows flare data removal. It is a relational diagram (1) of 1 line and 1 SIMD. It is a relational diagram (2) of 1 line and 1 SIMD. It is a table | surface which shows the data communication which concerns on this invention.

Explanation of symbols

2 ... SIMD type microprocessor, 4 ... global processor, 12 ... processor element, 26 ... arithmetic unit, 28, 28 '... shift / expansion / bus selector, 30 ... PE Shift selector.

Claims (1)

A global processor including sequential units, and max processor elements, each processor element is numbered in order from 0 to (max-1) ordinal,
Each processor element further includes an arithmetic unit for processing data and a plurality of registers connected to the input / output bus of the arithmetic unit.
With respect to processor elements within a predetermined first number range as viewed from both ends of the processor element arrangement, the i-th (i is a natural number and 1 ≦ i ≦ (first number)) processor element from the end The bus is connected from the processor element at the opposite end to the ((first number) -i) -th processor element by a path across each bus and a selector,
In the processor elements other than the processor elements within the first number range when viewed from both ends of the processor element arrangement, the buses of the processor elements adjacent to the left and right within the first number range centering on the respective processor elements , Connected by route,
The processor elements at both ends of the processor element arrangement are arranged in the vicinity,
Furthermore,
A register control signal sent from the sequential unit to each processor element is a pair in all the processor elements, and one signal indicating a register selection mode included in the register control signal is prepared.
Each of the processor elements within a predetermined first number range as viewed from both ends of the processor element arrangement includes a register selection changing device,
For the processor elements within a predetermined first number range when viewed from both ends of the processor element arrangement, the register selection changing device is within the first number range when viewed from both ends of the processor element arrangement according to the selection mode. A SIMD type microprocessor configured to be able to select a register different from a processor element other than the processor element .

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