JP5601817B2 - Parallel processing unit - Google Patents

Description

  The present invention relates to a SIMD (Single Instruction Multiple Data-path) type parallel arithmetic processing device in which a plurality of arithmetic elements connected to each other perform parallel processing by a single instruction.

  Today, SIMD type processors are used in various fields. The SIMD type processor is a processor that simultaneously processes a plurality of data with a single instruction. Conventionally, as such a SIMD type processor, a first shift register for serial-to-parallel conversion of input serial data, and a plurality of processors for processing parallel data output from the first shift register in parallel by the same program And a second shift register that converts the parallel data output from these processors into parallel serial data and outputs it as output serial data (see, for example, Patent Document 1).

JP-A-5-20448

  However, in the conventional parallel processing device, even if a plurality of computing elements are provided, the interconnection mechanism for referring to the data held by the computing elements at a desired distance from a certain computing element operates simultaneously and similarly. To do. For this reason, a SIMD processor in which M (M ≧ 2) operation elements are arranged in a SIMD type processor performs similar arithmetic processing on an O column (O ≧ 2) data string having N (N <M) data numbers. In the implementation, when it is desired to perform an operation independently for each data string (when it is not desired to perform cross-reference between data strings), it is necessary to sequentially process the data in the O column one by one. In this case, only N of the M computing elements can be used in parallel, so that all of the arithmetic processing capabilities of the SIMD processor cannot be exhibited, and there is a problem that a loss occurs in terms of processing time.

  Further, in the conventional parallel processing device, when the arithmetic processing to the sequential input and the bus input is required in one SIMD type processor, the block input is processed when the block input is processed by the SIMD type processor having the raster input interface. -Raster conversion processing (parallel-serial conversion processing) and raster-block conversion processing (serial-parallel conversion processing) are required when processing raster input data with a SIMD processor having a block input interface. However, there is a problem that a loss occurs in terms of processing time.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a parallel arithmetic processing device capable of increasing the processing speed.

The parallel arithmetic processing device according to the present invention includes a plurality of arithmetic unit groups having a plurality of arithmetic elements arranged one-dimensionally and connected to each other, and the arithmetic unit groups are formed into a one-dimensional torus or ring shape by an interconnection mechanism. In a parallel arithmetic processing unit that is connected and operates as a SIMD type, each arithmetic element is provided with a controller, and the controller controls the interconnection mechanism to output any other arithmetic element locally in the arithmetic unit group. And any one of the outputs of computing elements within a predetermined distance in consideration of wraparound, assuming that all computing units are a one-dimensional torus or a series of rings. The mode to be switched is switched .

In the parallel arithmetic processing device of the present invention, the controller controls the interconnection mechanism, so that the output of any one other arithmetic element is input locally within the arithmetic unit group, and all the arithmetic unit groups are primary. Considering the original torus or a series of rings, considering the wraparound, it is configured to switch to the mode that inputs any one of the outputs of the calculation elements within a predetermined distance, so the processing speed is increased. Can be achieved.

It is a block diagram which shows the parallel arithmetic processing apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows the raster input format which is a general input format of image data, and a block input format. It is a block diagram which shows the input interface of the parallel arithmetic processing unit by Embodiment 1 of this invention. It is explanatory drawing at the time of making the input interface of the parallel arithmetic processing unit by Embodiment 1 of this invention operate | move as a raster input interface. It is explanatory drawing at the time of operating the input interface of the parallel arithmetic processing unit by Embodiment 1 of this invention as a bus input interface. It is a block diagram which shows the output interface of the parallel arithmetic processing unit by Embodiment 1 of this invention. It is explanatory drawing at the time of making the output interface of the parallel arithmetic processing unit by Embodiment 1 of this invention operate | move as a raster output interface. It is explanatory drawing at the time of operating the output interface of the parallel arithmetic processing unit by Embodiment 1 of this invention as a bus output interface. It is a block diagram which shows the interconnection mechanism of the parallel arithmetic processing unit by Embodiment 1 of this invention. It is explanatory drawing which shows operation | movement of the interconnection mechanism of the parallel arithmetic processing unit by Embodiment 1 of this invention. It is a block diagram which shows the connection selection mechanism of the parallel arithmetic processing unit by Embodiment 1 of this invention. It is a block diagram of an interconnection mechanism, a connection selection mechanism, and arithmetic elements when N = 16 and M = 8 of the parallel arithmetic processing device according to the first embodiment of the present invention. It is a block diagram of the parallel arithmetic processing apparatus by Embodiment 2 of this invention. It is a block diagram of the parallel arithmetic processing apparatus by Embodiment 3 of this invention. It is a block diagram of the parallel arithmetic processing apparatus by Embodiment 4 of this invention. It is a block diagram of the parallel arithmetic processing apparatus by Embodiment 5 of this invention. It is a block diagram which shows the vertical interconnection mechanism of the parallel arithmetic processing unit by Embodiment 5 of this invention. It is a block diagram which shows the vertical connection selection mechanism of the parallel arithmetic processing unit by Embodiment 5 of this invention.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a parallel arithmetic processing apparatus according to Embodiment 1 of the present invention.
The parallel arithmetic processing apparatus shown in FIG. 1 is a SIMD type processor, and includes an arithmetic element 1, an input interface 2, an output interface 3, a controller 4, an interconnection mechanism 5, and a connection selection mechanism 6. A plurality of calculation elements 1 are arranged one-dimensionally and perform calculation and recording of calculation results, and include an ALU (Arithmetic Logic Unit) 11 and internal memories 12a and 12b. The ALU 11 is a calculation unit that performs a desired calculation according to a calculation command from the controller 4. The internal memories 12 a and 12 b are data recording means for recording the calculation result output from the ALU 11 and transferring it to the ALU 11 and the output interface 3.

  The input interface 2 is an interface for receiving data such as image data input from the outside in a raster format or a block format, and transferring the data to the inside of the parallel processing unit. The input interface 2 includes an input buffer 21 and a selector 22. Yes. The input buffers 21 are provided in the same number corresponding to the calculation elements 1, and are buffers for recording input data received from the outside and transferring them in parallel to the respective calculation elements 1. The selector 22 is input format selection means for selecting the input data format of the input interface 2.

  FIG. 2 is an explanatory diagram showing a raster input format and a block (bus) input format, which are general image data input formats, where (a) is a raster input format and (b) is a block (bus) input format. Represent. Circles in the figure indicate pixel data. As for the block input format, 4 × 4 data bus input is shown as an example. However, the bus width of the bus input is, for example, bus width = 4 data. The numbers in the figure represent general input orders in the respective formats.

  Returning to FIG. 1, the output interface 3 is an interface for receiving the output data from the computing element 1 and transferring the data to the outside in a raster format or block format, and internally includes an output buffer 31 and a selector 32. Have. The output buffers 31 are provided in the same number corresponding to the respective computation elements 1 and are used for recording the computation result data output from each computation element 1 and transferring the data to the outside. The selector 32 is output format selection means for selecting the output data format of the output interface 3.

  The controller 4 is a control unit for transferring a single calculation command to the calculation element 1, the input interface 2, the output interface 3, the interconnection mechanism 5, and the connection selection mechanism 6 to control the calculation process. The interconnection mechanism 5 is a reference data distance selection unit that connects the calculation elements 1 to each other and transfers data from the calculation element 1 at an arbitrary distance according to a calculation command of the controller 4. The connection selection mechanism 6 is a reference data group selection unit that is arranged at a constant interval between the interconnection mechanisms 5 and selects a connection configuration of the interconnection mechanism 5.

FIG. 3 shows details of the input interface 2.
Each selector 22 is configured to select an input format according to a control signal from the controller 4. Each selector 22 inputs raster input data and bus input data, and outputs the selected output to the input buffer 21. The input buffer 21 is configured to receive data from the selector 22 based on a control signal from the controller 4 and output the data to each arithmetic element 1. With such a configuration, the input interface 2 has two functions: a raster input interface function and a bus input interface function. Here, as an example, the bus input is a bus width of 4 data, but the bus width is not limited to 4 data.

FIG. 4 is an explanatory diagram when the input interface 2 operates as a raster input interface, and its data flow is indicated by a broken line.
When data is input by raster input, the leftmost selector 22 selects external raster input data, and the other selectors 22 select data in the input buffer 21 adjacent to the left. The selector control signal from the controller 4 is given so that the left input signal is selected by all the selectors 22.
Further, an input buffer control signal from the controller 4 is given so that all the input buffers 21 receive it. As a result, the input buffer 21 at the left end receives raster input data from the outside, and the other input buffers 21 receive data from the input buffer 21 adjacent to the left, respectively, so that an operation equivalent to the raster input interface is possible.

FIG. 5 is an explanatory diagram when the input interface 2 operates as a bus input interface, and its data flow is indicated by a broken line.
When data is input by bus input, a selector control signal from the controller 4 is given so that the input signal on the upper right side of the selector 22 is selected.
Further, the input buffer control signal from the controller 4 is given so that only the part to be written is received. As a result, any continuous input buffer 21 receiving the bus input receives the bus input data, and an operation equivalent to that of the bus input interface becomes possible.

FIG. 6 shows details of the output interface 3.
Each selector 32 is configured to select data from the calculation element 1 and shift data at the time of raster output in accordance with a control signal (upper selector control signal) from the controller 4. That is, as a selection of shift data at the time of raster output, selectors 32 other than the left end of the drawing each receive the output of the output buffer 31 on the left side. The selector 33 is a selector for selecting one data at an arbitrary position by a control signal (lower selector control signal) from the controller 4. Further, the output buffer 31 is configured to receive data from each selector 32 in accordance with a control signal from the controller 4.
With such a configuration, the output interface 3 has two functions: a raster output interface function and a bus output interface function. Here, as an example, the bus output has a bus width of 4 data, but the bus width is not limited to 4 data.

  In addition, the operation when fetching data from the computing element 1 is common to raster output and bus output. The input signal on the right side of the selector 32 is selected by the upper selector control signal from the controller 4, and at the same time, the output buffer control signal from the controller 4 is given. As a result, the data transferred from the computing element 1 is received by the output buffer 31 in parallel.

FIG. 7 is an explanatory diagram when the output interface 3 operates as a raster output interface, and its data flow is indicated by a broken line.
When data is output by raster output, an input signal on the left side of the selector 32 is selected by an upper selector control signal from the controller 4, and an output buffer control signal from the controller 4 is given at the same time. As a result, all the output buffers 31 simultaneously transfer data to the adjacent output buffer 31 (right adjacent in the figure) and receive data from the adjacent output buffer 31 (left adjacent in the figure). Here, the output buffer 31 at the right end carries out transfer to the outside.
In this way, the output interface 3 can operate as a raster output interface.

FIG. 8 is an explanatory diagram when the output interface operates as a bus output interface, and its data flow is indicated by a broken line.
When outputting data by bus output, the four selectors 33 are controlled by the lower selector control signal from the controller 4 to select four continuous output buffers at the positions to be output. In this way, the output interface 3 can operate as a bus output interface.

  The input interface 2 and the output interface 3 described above can deal with raster input and bus input with a single configuration. As a result, when the raster input and the bus input are required by a single SIMD type processor, the arithmetic processing required for the serial-parallel conversion process or the parallel-serial conversion process can be reduced as compared with the conventional case. The effect that it can be obtained.

FIG. 9 shows details of the interconnection mechanism 5.
A selector 51 in the figure is a selection means for selecting data transferred from the arithmetic element 1 at an arbitrary distance in accordance with a control signal from the controller 4. However, only the part for referring to the data of the calculation element 1 on the left side of the interconnection mechanism 5 is shown here. The portion for referring to the data of the calculation element 1 on the right side has the same configuration and operation as the left side (symmetrical), and therefore the description thereof is omitted here.
The numerical value [] in the brackets in the figure represents the position of the calculation element. That is, the arithmetic element [x] is an arithmetic element immediately below the interconnection mechanism 5, for example, the arithmetic element [x−8] is the arithmetic element on the left by eight, and the arithmetic element [x + 4] is the arithmetic element on the right of four. Represents an element.
The interconnection mechanism 5 transfers the data in the internal memory 12a or 12b of the calculation element 1 all at a desired distance all at once according to the calculation command of the controller 4. For example, when ordering the transfer of the distance of the left 1, each interconnection mechanism 5 transfers the data in the internal memory from the calculation element 1 at the position separated by 1 on the right as shown by the broken line in FIG. 10. In FIG. 10, the connection selection mechanism 6 is not shown.

  With such a function of the interconnection mechanism 5, it is possible to refer to data held by the nearby computing element 1 without operating the input interface 2. Here, as an example, the example of the interconnection mechanism 5 capable of referring to the distance of the left adjacent 8 is shown, but the number and the maximum distance are not limited to 8. It is also conceivable that the interconnection mechanism 5 refers to non-consecutive computing elements.

FIG. 11 shows details of the connection selection mechanism 6. However, like the interconnection mechanism 5, only the part for referring to the data of the left arithmetic element 1 is shown here. About the part for referring the data of the calculation element 1 of the right side, since it becomes the structure and operation | movement similar to the left side (symmetrical), description is abbreviate | omitted.
The connection selection mechanisms 6 are arranged at intervals of M in terms of the number of interconnection mechanisms 5 (= the number of computing elements 1). M is a number that satisfies M ≦ N / 2, where N is the total number of interconnection mechanisms 5. The selector 61 selects one of the data from the arithmetic element [x′−O] and the data from the arithmetic element [x ′ + MO] (1 ≦ O ≦ 8 in the figure) by the selector control signal from the controller 4. And selecting means for outputting to the arithmetic element [x ′ + 8−O].
By the connection selection mechanism 6, 8 data from the calculation element [x′-01] to the calculation element [x′−08] and 8 data from the calculation element [x ′ + M-01] to the calculation element [x ′ + M−08] are displayed. One of them can be selected and output from the calculation element [x ′] to the calculation element [x ′ + 07]. Here, x ′ is a value such that the calculation element located on the right side of the connection selection mechanism is the calculation element [x ′].

FIG. 12 shows details of a part of the interconnection mechanism 5, the connection selection mechanism 6, and the computing element 1 when N = 16 and M = 8 as an example.
By giving the connection selection mechanism 6 a control signal from the controller 4 so as to select the data of the calculation element [x′−O], 16 pieces of calculation elements [0] to [15] are calculated. The interconnection mechanism can operate in a connected state.
In addition, by giving a control signal from the controller 4 so as to select the calculation element [x ′ + MO] to the connection selection mechanism 6, eight elements from the calculation element [0] to the calculation element [7] are selected. The interconnection mechanisms are grouped together, and the eight interconnection mechanisms from the calculation element [8] to the calculation element [15] are grouped, and eight parallel × two interconnection mechanisms 5 can be used independently. .

Conventionally, independent cross-reference is required for each data string, and processing for a large data string with the number of data P and a small data string with the number of data Q (Q ≦ P / 2) is required by a single SIMD processor. In this case, it is necessary to sequentially process small data strings one by one.
However, as shown in the first embodiment, by using the connection selection mechanism 6 and configuring the SIMD type processor with N = P and M = Q, P / Q (however, the fraction is rounded down) small data strings are obtained. It becomes possible to process at the same time. That is, the processing speed of the small data string can be improved by P / Q times compared to the conventional case.

  As described above, according to the first embodiment, both the raster input and the bus input can be handled with a shorter calculation processing time than the conventional one. In addition, it is possible to perform arithmetic processing on two types of data strings with different numbers of data in a shorter arithmetic processing time than in the past.

  In the first embodiment, one data is 8 bits as an example, but this may be any value. In the first embodiment, N = 16 and M = 8 are set as an example, but any number may be used. N may not be a multiple of M, and N and M may not be even or a power of 2. Further, in the above example, the bus input / output of the input interface and the output interface is a bus width of 4 data, but this may be any value. The bus widths of the input interface and the output interface may be different.

  Further, in the above example, the calculation elements that can be referred to by the interconnection mechanism 5 are eight calculation elements that are continuous in the left and right, but this may be any value. Further, a configuration may be adopted in which non-consecutive calculation elements 1 can be selected. Furthermore, the number of arithmetic elements that can be referred to on the left and right may be different.

As described above, according to the parallel arithmetic processing device of the first embodiment, a plurality of arithmetic units having a plurality of arithmetic elements arranged one-dimensionally and connected to each other are provided, and an interconnection mechanism is provided between the arithmetic units. In a parallel arithmetic processing device that is connected to a one-dimensional torus or ring shape and operates as a SIMD type in each arithmetic element , a controller is provided, and the controller controls the interconnection mechanism, so that other local in the arithmetic unit group A mode in which the output of any one computation element is input, and all computation units are regarded as a one-dimensional torus or a series of rings, and the computation elements output within a predetermined distance in consideration of wraparound Since the mode for inputting any one of these is switched , the loss of processing time can be eliminated, and the processing speed can be increased.

  Further, according to the parallel arithmetic processing apparatus of the first embodiment, an input format for selecting either an input format of raster input or block input as an interface through which a plurality of computing elements 1 receive input data from outside. Since the input interface 2 having selection means is provided, when raster input and bus input are required by a single SIMD type processor, arithmetic processing required for serial-parallel conversion processing or parallel-serial conversion processing is performed. Can be reduced.

  Further, according to the parallel arithmetic processing apparatus of the first embodiment, an output format selection for selecting either an output format of raster output or block output as an interface through which a plurality of arithmetic elements 1 transfer output data to the outside Since the output interface 3 having means is provided, when the raster input and the bus input are required by a single SIMD type processor, the arithmetic processing required for the serial-parallel conversion process or the parallel-serial conversion process is reduced. can do.

Embodiment 2. FIG.
FIG. 13 is a configuration diagram of the parallel arithmetic processing apparatus according to the second embodiment.
The second embodiment is different from the parallel processing device of FIG. 1 shown in the first embodiment in that the control signal line from the controller 4 to the connection selection mechanism 6 is separated for each connection selection mechanism 6 ( (See the difference 100 in the figure). Since other configurations are the same as those of the first embodiment, the following description will be focused on differences from the first embodiment.
In the second embodiment, the control signal line from the controller 4 to the connection selection mechanism 6 is independent, so that either the data of the calculation element [x′−O] or the data of the calculation element [x ′ + MO] is stored. It can be selected or determined independently for each connection selection mechanism 6.
With the above configuration, the connection destination of the connection selection mechanism 6 can be switched at an arbitrary position, and a data string can be processed simultaneously for a plurality of types of small data strings having different numbers of data.

  As an example, a case where N = 256 and M = 16 will be described. Since it is possible to switch the connection selection mechanism 6 at an arbitrary position, for example, eight data strings with 32 interconnect mechanisms 5 as a group, four data strings with 64 interconnect mechanisms 5 as a group, etc. , 16 × i (i is a positive integer) interconnection mechanism 5 as a group, and 16 / i (i is a positive integer, rounded down) data string can be processed simultaneously and independently.

  It is also possible to divide the interconnection mechanism 5 at unequal intervals and perform data string processing as a group. As an example, a control signal from the controller 4 is given so as to divide the interconnection mechanism 5 at unequal intervals such as 128, 64, 32, and 32. Thus, one data string having 128 data, one data string having 64 data, and 32 data strings can be processed independently.

  As described above, according to the second embodiment, it is possible to perform arithmetic processing on three or more types of data strings having different numbers of data in a shorter arithmetic processing time than in the first embodiment.

In the above example, N = 256 and M = 16 are set as an example, but any number may be used. N may not be a multiple of M, and N and M may not be even or a power of 2.
In the above example, 32, 64, and 128 are given as examples of the number of interconnecting mechanisms 5 treated as a unit, but this means that M × i (i is a positive integer). Any number is acceptable as long as it is satisfied. Each may not be an even number or a power of 2.

  As described above, according to the parallel processing device of the second embodiment, the controller 4 individually controls the plurality of connection selection mechanisms 6, so that a plurality of types of small data strings having different numbers of data are obtained. On the other hand, data strings can be processed simultaneously.

Further, according to the parallel processing apparatus of the second embodiment, the connection selection mechanism 6 because to arrange at intervals not like, it is possible to perform operation to the three or more types of data strings having different number of data .

Embodiment 3 FIG.
FIG. 14 is a configuration diagram of the parallel arithmetic processing apparatus according to the third embodiment.
In the third embodiment, the control signal line from the controller 4 to the interconnection mechanism 5 is separated for each of the M interconnection mechanisms 5 as compared with the parallel processing unit of the first embodiment shown in FIG. Further, the control signal line from the controller 4 to the calculation element 1 is separated for each of the M calculation elements 1 (see the difference 102 in the figure). Since other configurations are the same as those of the first embodiment, the following description will be focused on differences from the first embodiment. In the following, the M computing elements 1 and the interconnection mechanism 5 are collectively referred to as a computing element group.

  By independently providing a control signal line from the controller 4 for each arithmetic element group, each arithmetic element group can be used as if it were an independent SIMD type processor. That is, it can be used as a multiple instruction multiple data (MIMD) type processor having a total of N / M (but rounded down) arithmetic element groups (= SIMD type processor with M parallel numbers).

When used as a MIMD type processor, first, the connection selection mechanism 6 is given a control signal from the controller 4 so as to select data of the arithmetic element [x ′ + MO]. As a result, the interconnection between the calculation elements is disconnected. At the same time, a control signal is given from the controller 4 to the calculation element group so that a separate calculation process is performed in each calculation element group and a separate cross-reference is performed.
By giving such a control signal, each calculation element group can execute a separate calculation instruction for an independent data string, and a function as a MIMD type processor is realized.

When used as a conventional SIMD type processor, a control signal from the controller 4 to the connection selection mechanism 6 is given so as to select the data of the calculation element [x′-O], and at the same time for each calculation element group All give the same control signal.
By giving the control signal as described above, the entire SIMD type processor can be used as one SIMD type processor as before.

  As described above, according to the third embodiment, the SIMD type processor can also be used as the MIMD type processor.

  In the above example, the entire controller is controlled by the single controller 4, but the controller 4 may be divided into a plurality. When the controller 4 is divided into a plurality of parts, the number of arithmetic element groups controlled by each of the divided controllers may be any number.

  As described above, according to the parallel arithmetic processing device of the third embodiment, the controller 4 controls the plurality of arithmetic elements 1 individually, so that the function as the MIMD type processor can be realized.

  Further, according to the parallel processing device of the third embodiment, the controller 4 individually controls the plurality of interconnection mechanisms 5, so that the function as the MIMD type processor can be realized.

Embodiment 4 FIG.
FIG. 15 is a configuration diagram of the parallel arithmetic processing apparatus according to the fourth embodiment.
The fourth embodiment is different from the parallel processing device of the first embodiment shown in FIG. 1 in that conventional interfaces are used for the input interface 2a and the output interface 3a. That is, the fourth embodiment has a configuration in which only the connection selection mechanism 6 is added to the conventional configuration. In the following, the description will be focused on the points different from the first embodiment.
If there is a data string with a single input format and output format but different numbers of data, only the connection selection mechanism 6 is added to the conventional configuration, and the conventional interface interface 2a and output interface 3a are used. It may be used. That is, the connection selection mechanism 6 does not necessarily need to be used in combination with the input interface 2 shown in FIGS. 3 to 5 or the output interface 3 shown in FIGS. 6 to 8. As described above, by configuring the SIMD type processor with N = P (large data string) and M = Q (small data string), P / Q small data strings can be processed simultaneously. .

  As described above, according to the fourth embodiment, it is possible to perform arithmetic processing on two types of data strings having different numbers of data in a shorter arithmetic processing time than in the past.

  In the fourth embodiment, a raster input interface or a bus input interface may be used as the input interface 2a. Similarly, a raster output interface or a bus output interface may be used as the output interface 3a. Further, the raster input interface and the bus output interface may be used simultaneously, or the bus input interface and the raster output interface may be used simultaneously. Furthermore, it is of course possible to use an input / output interface other than the raster format and bus format.

Embodiment 5 FIG.
The fifth embodiment is different from the first embodiment in that the calculation elements 1 are two-dimensionally arranged and there is a cross-reference in the vertical direction.
FIG. 16 shows the connection relationship between the computing element 1, the horizontal interconnection mechanism 5a, the vertical interconnection mechanism 5b, the horizontal connection selection mechanism 6a, and the vertical connection selection mechanism 6b in the fifth embodiment. As shown in the figure, the horizontal interconnection mechanism 5a and horizontal connection selection mechanism 6a in the horizontal direction and the vertical interconnection mechanism 5b and vertical connection selection mechanism 6b in the vertical direction are provided in the fifth embodiment. This is the same as the interconnection mechanism 5 and the connection selection mechanism 6 in the first embodiment. The selector 7 is a selector for selecting either the horizontal interconnection mechanism 5a or the vertical interconnection mechanism 5b according to a control signal from the controller 4. Since the configuration as the parallel arithmetic processing apparatus other than this is the same as that of the first embodiment, the following description will focus on the points different from the first embodiment.

FIG. 17 shows a detailed configuration of the vertical interconnection mechanism 5b.
The configuration and operation principle of the vertical interconnection mechanism 5b is exactly the same as that of the interconnection mechanism 5 in the first embodiment. However, the difference is that the upper data is referred to instead of the left data in FIG. The selector 51b is a selection means for selecting the data transferred from the computing element 1 at an arbitrary distance above according to the control signal from the controller 4. However, only the portion of the vertical interconnection mechanism 5b that refers to the data of the upper computing element 1 is shown here. The portion that refers to the data of the lower calculation element 1 has the same configuration and operation as those of the upper side (vertical symmetry), and thus the description thereof is omitted here. In addition, the calculation element [y] in the figure represents the position of the calculation element. The calculation element [y] is the calculation element immediately adjacent to the vertical interconnection mechanism 5b, the calculation element [y-8] represents the next eight calculation elements, and the calculation element [y + 4] represents the four lower calculation elements. .

  The vertical interconnection mechanism 5b transfers the data in the internal memory 12a or 12b of the calculation element 1 all at a desired distance all at once according to the calculation command of the controller 4. With this function, it is possible to refer to the data held by the nearby computing element 1 without operating the input interface 2. In FIG. 17, as an example, an interconnection mechanism capable of referring to up to eight adjacent distances is shown.

FIG. 18 shows details of the vertical connection selection mechanism 6b.
The configuration and operation principle of the vertical interconnection mechanism 6b is exactly the same as the connection selection mechanism 6 in the first embodiment. However, the difference is that the upper data is referred to instead of the left data in FIG.
In FIG. 18, as in the vertical interconnection mechanism 5 b shown in FIG. 17, only the part for referring to the data of the upper arithmetic element is shown here. The portion for referring to the data of the lower arithmetic element has the same configuration and operation as those of the upper side (vertical symmetry), and thus description thereof is omitted.
The vertical connection selection mechanisms 6b are arranged every R pieces in the number of vertical interconnection mechanisms 5b (= the number of computing elements 1). R is a number satisfying R ≦ S / 2, where S is the total number of vertical interconnection mechanisms 5. Further, the selector 61b receives one of the data from the calculation element [y′-T] and the data from the calculation element [y ′ + RT] (1 ≦ T ≦ 8 in the figure) according to the selector control signal from the controller 4. Is a selection means for selecting and outputting to the computation element [y ′ + 8−T].
By such a vertical connection selection mechanism 6b, eight data from the calculation element [y′-01] to the calculation element [y′-08] and the calculation element [y ′ + M-01] to the calculation element [y ′ + M−08] are obtained. ] Can be selected and output from the calculation element [y ′] to the calculation element [y ′ + 07]. Here, y ′ is a value such that the calculation element located below the connection selection mechanism is the calculation element [y ′].

With the vertical interconnection mechanism 5b and the vertical connection selection mechanism 6b as described above, data can be referred from an arbitrary position in the vertical direction in the same manner as in the horizontal direction.
Furthermore, the selector 7 selects either the horizontal arbitrary position data output from the horizontal interconnection mechanism 5a or the vertical arbitrary position data output from the vertical interconnection mechanism 5b according to a control signal from the controller 4. Data is selected and transferred to computing element 1.

  As described above, according to the fifth embodiment, in the SIMD type processor in which the calculation elements are arranged two-dimensionally, it is possible to refer to the internal data of the arbitrary calculation element 1 in the horizontal direction and the vertical direction. .

In the above example, the calculation element 1 that can be referred to by the horizontal interconnection mechanism 5a and the vertical interconnection mechanism 5b is assumed to be eight calculation elements continuous in the vertical direction, but any value may be used. Further, a configuration may be adopted in which non-consecutive calculation elements 1 can be selected. Furthermore, the number of arithmetic elements that can be referred to above and below may be different.
In the configuration of FIG. 16 described above, the horizontal connection selection mechanism 6a and the vertical connection selection mechanism 6b are arranged at intervals of two as an example, but this may be any value. Also, different values may be used for horizontal and vertical.

As described above, according to the parallel arithmetic processing device of the fifth embodiment, a plurality of arithmetic units having a plurality of arithmetic elements arranged one-dimensionally and connected to each other are provided, and an interconnection mechanism is provided between the arithmetic units. A parallel arithmetic processing unit in which a circuit connected in a one-dimensional torus or ring shape is arranged two-dimensionally and each arithmetic element operates as a SIMD type is provided with a controller, and the controller controls the interconnection mechanism, thereby calculating The wraparound is performed by considering the mode in which the output of any other arithmetic element is input locally in the unit group and all the unit units arranged in one dimension as a one-dimensional torus or a series of rings. since in view and to switch a mode to enter any one of the output of the operational elements within a predetermined distance, in addition to the effect of the first embodiment, the two-dimensional distribution Horizontal direction and the vertical direction, it is possible to refer to the internal data of an arbitrary calculation element 1 in.

  1 computing element, 2, 2a input interface, 3, 3a output interface, 4 controller, 5 interconnection mechanism, 5a horizontal interconnection mechanism, 5b vertical interconnection mechanism, 6 connection selection mechanism, 6a horizontal connection selection mechanism, 6b vertical connection Selection mechanism, 7, 22, 32, 51, 51b, 61, 61b selector, 11 ALU, 12a, 12b internal memory, 21 input buffer, 31 output buffer.

Claims (8)

A plurality of computing units having a plurality of computing elements arranged in a one-dimensional manner and connected to each other, the computing units are connected to each other in a one-dimensional torus or ring shape by an interconnection mechanism, and the computing elements are connected to each other. In a parallel processing device operating as a SIMD type ,
A controller, wherein the controller controls the interconnection mechanism;
A mode in which the output of any one other arithmetic element is input locally in the arithmetic unit group, and all the arithmetic unit groups are assumed to be a one-dimensional torus or a series of rings. A parallel arithmetic processing device for switching between a mode in which any one of outputs of arithmetic elements within the distance is input . A plurality of computing units having a plurality of computing elements arranged in one dimension and connected to each other are arranged, and a circuit in which the computing units are connected in a one-dimensional torus or ring shape by an interconnection mechanism is arranged in two dimensions. In the parallel arithmetic processing device in which each of the arithmetic elements operates as a SIMD type ,
A controller, wherein the controller controls the interconnection mechanism;
A mode in which the output of any one other arithmetic element is input locally in the arithmetic unit group, and all the arithmetic unit groups arranged in the one dimension are regarded as a one-dimensional torus or a continuous ring, A parallel arithmetic processing device that switches between a mode in which any one of outputs of arithmetic elements within a predetermined distance is input in consideration of wraparound .   The input interface having input format selection means for selecting an input format of either a raster input or a block input is provided as an interface through which a plurality of arithmetic elements receive input data from the outside. The parallel arithmetic processing apparatus according to claim 1 or 2.   2. An output interface having output format selection means for selecting an output format of either raster output or block output is provided as an interface through which a plurality of arithmetic elements transfer output data to the outside. The parallel processing unit according to claim 3.   The parallel arithmetic processing device according to claim 1, wherein the connection selection mechanisms are arranged at unequal intervals.   The parallel arithmetic processing device according to claim 1, wherein the controller individually controls the plurality of connection selection mechanisms.   The parallel arithmetic processing device according to claim 1, wherein the controller individually controls a plurality of arithmetic elements.   The parallel arithmetic processing device according to claim 1, wherein the controller individually controls a plurality of interconnection mechanisms.

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