JP3593439B2 - Image processing device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a general-purpose image processing apparatus in which bit widths of image data to be handled are various, and more particularly, to an image processing apparatus capable of changing a processing configuration according to a bit width of image data.
[0002]
[Prior art]
One of the methods for performing high-speed filter processing, which is one of image processing, is to perform processing while storing image data in a line memory (LM). In the method using the LM, the operation required for the filter processing can be partially performed in parallel. In addition, the filtering process can be performed by simply scanning the screen.
[0003]
FIG. 2 shows a schematic configuration of an image processing apparatus using LM. FIG. 3A shows a configuration in the case of 3 × 3 filter processing when the bit width of image data is 8 bits. In the 3 × 3 filter processing, nine image data including neighboring pixels are required for processing a certain pixel. These nine image data are given by a combination of two line memories and image data read from the processing target memory. Then, by using nine image data and nine coefficients used for the filter processing and performing a product-sum operation in parallel by using nine multipliers, the filter processing is executed at high speed.
[0004]
If the bit width of the image data handled by the same 3 × 3 filter is 16 bits, two line memories having a width of 16 bits are used as shown in FIG. Further, when the bit width of the image data is 8 bits and 5 × 5 filter processing is realized, four line memories having an 8-bit width are required as shown in FIG. 2C.
[0005]
2. Description of the Related Art Conventionally, 16-bit image data has been used for medical image processing requiring high resolution, and 8-bit or 1-bit image data has been used for image processing in other fields. Recently, there has been an increasing need for image processing using 16-bit width image data even in the industrial field.
[0006]
[Problems to be solved by the invention]
In a conventional image processing apparatus using a line memory, the configuration is fixed according to the specification of the maximum bit width in the image data to be processed. That is, in consideration of 3 × 3 filter processing, an image processing apparatus that handles image data having a maximum width of 8 bits has the configuration shown in FIG. 2A, and an image processing apparatus that handles image data having a maximum width of 16 bits has a configuration shown in FIG. (B). Therefore, in an image processing apparatus that handles 1-bit, 8-bit, and 16-bit image data, it is necessary to adopt the processing configuration shown in FIG.
[0007]
However, when processing image data of 1-bit width and 8-bit width using the processing configuration of FIG. 2B, there are many unused memory areas in the line memory, and the use efficiency of the memory is poor, which is not economical. There was a problem.
[0008]
Also, in the processing configuration of FIG. 2C that realizes 5 × 5 filter processing, the same problem as described above occurs when handling image data with a small bit width. Furthermore, when the 3 × 3 filter processing is performed, there is a problem that many unused circuits exist not only in the line memory but also in the arithmetic unit for the filter processing.
[0009]
The low use efficiency as described above is an important problem when speeding up processing. In general, pipeline processing is used for speeding up when a plurality of filter processes are continuously performed, and parallel processing for dividing a screen into small regions and performing processing for each small region is used for speeding up a single filter process. be able to. However, these pipeline processing and parallel processing require a large scale of a line memory and an arithmetic unit, and therefore, solving the above problems becomes an important issue.
[0010]
An object of the present invention is to provide an image processing apparatus which overcomes the problems of the prior art, can flexibly change the processing configuration according to the bit width and processing function of image data to be handled, and has excellent versatility and high resource use efficiency. Is to do. Another object of the present invention is to provide an image processing apparatus which can arbitrarily configure pipeline processing and parallel processing capable of high-speed processing according to the bit width of image data.
[0011]
[Means for Solving the Problems]
An object of the present invention is to provide an image processing apparatus for inputting image data to be processed to an image processing circuit using a line memory having a line width of a plurality of bits. A plurality of divided line memories are theoretically constructed by dividing the width, and the number of divided line memories used according to the set image processing function information (hereinafter, abbreviated as setting function) corresponds to the image processing circuit. This is achieved by providing a configuration for controlling the input and output.
[0012]
The above configuration has a function of controlling a combination of a plurality of arithmetic circuits in the image processing circuit according to the setting function, and includes changing a processing size such as 3 × 3 or 5 × 5 and / or It is characterized in that a processing form such as parallel processing can be changed.
[0013]
That is, the image processing apparatus of the present invention includes an image memory for storing image data to be processed, an image processing circuit for performing predetermined image processing, and converting the image data read from the image memory into block data corresponding to the processing size. An image processing apparatus having a line memory for outputting to the image processing circuit by dividing the line width of the line memory according to the bit width of the image data, theoretically forming a plurality of divided line memories, and setting function Configuration control means for controlling the input / output of the divided line memories of the number used in accordance with the image processing circuit, and line memory input data control means for generating input data to be input to the line memory. , Line memory output data for generating the block data from data output from the line memory. Characterized in that it comprises a control means.
[0014]
Further, in the P-stage pipeline processing by the i × i filter processing having a different setting function, when the number L to be used is (i−1) × P, the configuration control unit determines each stage of the pipeline processing. The divided line memory used in the first and second lines is a group of L / P lines, and a line group including a divided line memory for directly inputting image data read from the image memory is associated with the first stage image processing circuit. In the following image processing circuit, input / output control of the line memory is performed so as to sequentially correspond to a line group including a divided line memory for inputting processing data of a preceding stage.
[0015]
When the setting function is the parallel processing of the Q sets by the same i × i filter processing and the number L to be used is (i−1) × Q, the configuration control unit uses The divided line memories are divided into L / Q line groups, and one screen of the image data stored in the image memory is divided into Q in the vertical direction, and the image data read out in parallel from each area corresponds to the divided image data. It is characterized in that it is controlled to input to a line group.
[0016]
Further, when the configuration control means sets processing modes such as a filter size (i × i) indicating the setting function, the number of processes (1 or P or Q), and a pipeline, image processing for the number of processes is performed. It is characterized in that the circuit is controlled so as to be constituted by an arithmetic circuit corresponding to the filter size.
[0017]
According to the present invention, by changing the bit width of the line memory for one line according to the bit width of the image data to be handled, the theoretical number of line memories can be changed. For example, when a 32-bit line memory that realizes the same function as that of FIG. 2B is used, and when image data with a bit width of 16 bits is handled, the processing is the same as that of FIG. When handling image data having a width of 8 bits, the line memory can be controlled as shown in FIG. That is, since the processing configuration can be changed according to the bit width of the image data to be handled, the versatility and use efficiency of the image processing apparatus can be improved.
[0018]
Further, according to the present invention, since the input / output of the line memory can be controlled in accordance with the setting function of the image processing, a processing configuration capable of high-speed processing, such as multiple stages of pipeline processing and multiple sets of parallel processing, can be simplified. Can be built.
[0019]
Therefore, according to the present invention in which the configurations of the line memory and the image circuit are variably controlled as described above, for example, in the case of an image processing apparatus including a 32-bit line memory and a product-sum operation circuit capable of 5 × 5 filter processing The image data is processed by 3 × 3 filter processing of 16 bit width, the image data is processed by 5 × 5 or 3 × 3 filter processing of 1 to 8 bit width, or the image data is processed by 3 × 3 filter processing of 1 to 8 bit width It is possible to provide a general-purpose image processing apparatus capable of arbitrarily controlling the configuration of pipeline processing or parallel processing.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a functional block diagram illustrating an overall configuration of an image processing apparatus according to an embodiment. Arrows indicating the flow of signals in the figure correspond to pipeline processing described later.
[0021]
The configuration control unit 3 receives detailed information of the image data to be processed from the control device 1 and interprets it. Further, it interprets the image processing function transmitted from the control device 1 and issues a control signal for performing a processing configuration necessary for the function. Among the control signals issued by the configuration control unit 3, signals related to timing are transmitted to the memory control unit 10 via the signal transmission unit 4. The memory control unit 10 controls the processing target memory unit 100 that stores image data, the processing result memory unit 700, and the LM control unit 50 that controls the line memory (LM) 5.
[0022]
The configuration control unit 3 transmits a control signal for controlling input / output to the LM input data control circuit 200, the LM output control circuit 300, and the like based on the transmitted information of the image processing function and the bit width of the image data. 4. The LM input data control circuit 200 and the LM output data control circuit 300 control data input to and output from the LM 5 according to the control signal.
[0023]
The image data output from the LM output data control circuit 300 is calculated by the processor unit (PU) 400 of the image processing unit 90 and is input to the data integration circuit 500. Although the image processing unit 90 of the present embodiment executes the filter processing, a circuit for performing the shape conversion processing and the labeling processing may be added to the data integration circuit 500.
[0024]
The filtered processing result data is input to the data selection control circuit 600, the processing result data is selected by a control signal from the configuration control unit 3, and the data is output to the processing result memory unit 700. Also, in the data selection control circuit 600, when there is a feedback instruction from the control signal from the configuration control unit 3, the processing result data is fed back to the LM input data control circuit 200 via the feedback unit 800. In the pipeline processing configuration according to an embodiment of the present invention, the feedback processing result can be input to the LM 5 again to perform another filtering processing.
[0025]
FIG. 3 shows a schematic configuration of an image processing apparatus that performs pipeline processing. In the present embodiment, a different filter process B904 is processed in a pipeline manner by returning the output result of the filter process A903 to the LM5 again. This pipeline processing configuration can be changed from FIG. 2B or 2C. That is, LM5 has the same 32-bit width as in FIGS. 2B and 2C. Also, the 5 × 5 filter processing 902 in FIG. 2C uses 25 multipliers and 24 adders. Therefore, among them, 9 × 2 multipliers and 8 × 2 adders are used. 3 can be configured. Alternatively, if the system shown in FIG. 2B has 18 multipliers and 16 adders, the processing configuration shown in FIG. 3 can be changed.
[0026]
Next, each block in FIG. 1 will be described in detail. The configuration control unit 3 receives information related to image data and an instruction to execute an image processing function from the control device 1 via the bus 2.
[0027]
FIG. 4 shows an example of a management table for image data information and image processing function information. These pieces of information are set from the control device 1 in a management table provided in a storage device (not shown) of the configuration control unit 3. FIG. 7A shows a screen management table, which includes an image memory channel number indicating a memory in which image data to be processed is stored, a physical address starting on an image screen to be processed, a screen size, and the like. Further, image data information such as a bit width (w) of image data and a screen data type indicating an image type such as color or monochrome is stored.
[0028]
FIG. 2B shows an image processing function setting table, which stores processing contents such as filter processing, processing forms such as single processing, pipeline processing and parallel processing, and the number of processings and processing sizes. FIG. 8C shows a processing number management table for checking whether or not the processing function to be set is available. In the illustrated example, when the LM5 has a 32-bit width, the number of processing operations of the filter processing that can be configured by the image processing unit 90 is shown. Is shown. That is, the number of filter processes is set using the bit width (w) of image data and the process size (kernel size of the filter process) as parameters. For example, when the bit width of image data is w = 8 and 3 × 3 filter processing is performed, the number of possible processes is 2, and two different filter processes are performed in a pipeline or two identical filter processes are performed in parallel. Can be run with
[0029]
FIG. 5 shows a processing flow of the configuration control unit 3. The configuration control unit 3 generates signals for controlling each block, including input / output control of data to and from the LM 5, by setting image data information and setting image processing functions (s103). These control signals are issued based on the bit width (w) of the image data and the setting function, for example, as shown in FIG.
[0030]
The table in FIG. 5B shows an example of the control signal of each block of the 3 × 3 filter processing having a data width of 8 bits for single, pipeline processing, and parallel processing.
[0031]
The storage location and screen size of the image data are set for the memory control unit 10 by the control signal from the configuration control unit 3. In the case of the pipeline processing, as shown in FIG. 5B and FIGS. 6 and 7 described later, the data from the processing target memory unit 100 and the output data of the LM 5 are transmitted to the LM input data control circuit 200. And a control signal for generating input data of the LM 5 from the data of the image processing result. For the LM output data control circuit 300, the output (LM_out) 301 of the LM5 and the LM5 are controlled so that the PU 400 and the data integration circuit 500 realize the product-sum operation of the 3 × 3 filter processing according to the image processing function. Based on the data (LM_thr) 302 directly input from the input data control circuit 200, a control signal for generating block data to be distributed to each PU 400 is generated.
[0032]
Next, for each PU 400, a control signal for setting a coefficient and selecting a function such as multiplication or addition is generated so that a product-sum operation or the like realizes a desired function. For the data integration circuit 500, for example, a control signal for performing the configuration of the circuit shown in FIG. 8 is generated, and the addition processing of the product-sum operation is performed from the operation result from each PU 400. These are performed basically in the same manner as in the prior art.
[0033]
The data selection control circuit 600 generates a signal for selecting a 3 × 3 filter processing result stored in the processing result memory unit 700 and selecting image data to be fed back for realizing pipeline processing.
[0034]
After generating all the control signals, the configuration control unit 3 generates a start signal for starting image processing to the memory control unit 10 (s104). The memory control unit 10 generates an address for accessing each memory serving as image data storage means and a timing signal according to the start signal.
[0035]
As described above, in the case of the pipeline processing configuration of FIG. 3, the configuration control unit 3 theoretically divides the 32-bit width LM5 into LM0 to LM3 every 8 bits, and fetches input data corresponding to each divided LM. Enable. Further, two sets of 3 × 3 filter processing are performed according to the image processing function to be used. In the present embodiment, the 3 × 3 filter processing has been described, but a 5 × 5 filter processing configuration may be adopted. That is, the configuration of the product-sum operation can be changed according to the filter size so that the filter size can be freely selected.
[0036]
FIG. 8 shows a configuration for realizing two different 3 × 3 filter processes, and FIG. 9 shows a configuration for realizing 5 × 5 filter processes. In the product-sum operation in the filter processing, the multiplication is performed by the PU 400, and the addition is performed by the data integration circuit 500. The control of the filter size is realized by controlling the data flow in the data integration circuit 500. The flow of data is controlled by selectors 510 to 550, and desired filter processing is realized by combining adders according to the filter size. Therefore, the configuration in FIGS. 8 and 9 can be changed by controlling the data flow by each of the selectors 510 to 550.
[0037]
In the present embodiment, the configuration control unit 3 performs all controls relating to the processing configuration and image processing. However, other alternatives to the present embodiment are possible, for example, the control device 1 performs the same function, or a part of the function performed by the configuration control unit 3 is replaced by another block.
[0038]
Next, the input / output control of the LM 5 will be described in detail with reference to FIGS. 6, 7, and 10 to 15. FIG. First, the relationship between the LM input data control circuit 200, LM5, and LM output data control circuit 300 will be described with reference to FIG. In the figure, the data 201 having a bit width of 8 bits input from the processing target memory unit 100 is M [7: 0], and the data 203 input from the data selection control circuit 600 via the feedback means 800 is FB [7: 0], LM_in [31: 0] for data 210 input to LM5 having a 32-bit width, LM_out [31: 0] for data 301 (202) output from LM5, and LM output data control from LM input data control circuit 200. Data 302 input to the circuit 300 without passing through the LM5 is described as LM_thr [15: 0]. Note that the code of each data may be replaced with the code of the corresponding signal line.
[0039]
First, an outline of the functions of the LM input data control circuit 200 and the LM output data control circuit 300 will be described. In the LM input data control circuit 200, input data LM_in [31: 0] from M [7: 0], FB [7: 0], LM_out [31: 0] to LM5, and LM output data control circuit 300 Of the input data LM_thr [15: 0]. At this time, LM_in [31: 0] and LM_thr [15: 0] are controlled according to the bit width of the image data, and when the bit width is 8 bits, it is divided into 8 bits as shown in FIG. Use signal lines.
[0040]
FIG. 10 shows the relationship between the theoretical separation configuration of the LM5 and the bit width of the input data. If the bit width of the image data is 16 bits as shown in FIG. 2A, the processing configuration shown in FIG. 2B is used. Therefore, LM_in [15: 0] is assigned to LM0 and LM_in [31:16] is assigned to LM1. Is entered. As shown in FIG. 3B, when the bit width of the image data is 8 bits and the processing configuration of FIG. 3 is used, M [7: 0] is set to LM0, LM_out [7: 0] is set to LM1, and FB [is set to LM2. 7: 0], and LM_out [23:16] is input to LM3.
[0041]
Next, in the LM output data control circuit 300, data necessary for the filtering process is selectively controlled from LM_out [31: 0] and LM_thr [15: 0], and output to the PU 400. Here, the data flow when the 3 × 3 filter processing A and B are pipelined will be described in detail.
[0042]
FIG. 7 shows the configuration of the LM output data control circuit 300. Image data LM_out delayed by one or two lines in the vertical direction from the signal line 301 and image data LM_thr without delay in the vertical direction from the signal line 302 are input to the LM output data control circuit 300. In the figure, the numbers attached to the oblique lines on the signal lines indicate the number of each signal line, and correspond to the number of transmitted bits.
[0043]
Inside the LM output data control circuit 300, data delayed by two stages in the horizontal direction is generated using delay circuits (flip-flops) 311 and 312 in the horizontal direction, and block data required for 3 × 3 filter processing, that is, A combination of nine pieces of image data corresponding to a 3 × 3 area on the screen is created and distributed to each of the PUs 400 of the filter processing A. Similarly, for filter processing B using the processing result of filter processing A, block data is created using delay circuits 313 and 314. The output data is divided into the processing A and the processing B by the output data bit separation circuit 315.
[0044]
FIG. 20 shows a configuration of an LM output data control circuit 300 according to another embodiment. The delay circuits 311 to 314 and 321 to 324 in the horizontal direction each have four stages so that the delay circuits can be applied to both 3 × 3 and 5 × 5 filter processing. Specifically, output data is generated according to the processing size (kernel size) specified in the output data bit circuit.
[0045]
FIG. 11 shows the relationship between the data arrays of the filtering processes A and B. This example shows the relationship when there is no delay in the product-sum operation, and the filter A in the figure shows the operation of the filter processing at the position of Am, n. Here, the subscript m indicates the x coordinate of the image, and n indicates the y coordinate. Nine pieces of data used for the processing are combined into one set by the LM output data control circuit 300, and are input to the PU 400 and the data integration circuit 500, which are circuits that perform the product-sum operation at the same time.
[0046]
Next, a description will be given of a mechanism for performing pipeline processing of a different filter process B on the processing result of the filter process A. The processing result of Am, n in the filter processing A is transmitted to the LM input data control circuit 200 via the feedback means 800 and used for the filter processing B. At this time, the processing result of Am, n is Bm, n. At this time, the output result of the filter processing B is a position delayed by one line and one pixel from the processing result of the filter processing A because the processing result of the filter processing A is processed. That is, the filter processing A outputs the result at the pixel of (m, n) in absolute coordinates, and at this time, the filter processing B outputs the result of (m-1, n-1).
[0047]
Summarizing the above, in the filter processing A, the filter processing is performed on the data from the memory unit 100 to be processed, whereas in the filter processing B, the processing result of the filter processing A is filtered in a pipeline manner. Are doing. At this time, the difference between the configurations of the filter processing A and the filter processing B is that the processing is performed on the data from the processing target memory unit 100 or the processing is performed on the data resulting from the filtering processing A. Is the same as the processing configuration in the case of a single filtering process.
[0048]
The data control for realizing the pipeline processes of the filter processes A and B shown in FIG. 11 will be described in further detail. The purpose of the data control here is to control the timing of the data flow so that the three data indicated by the hatched portions in FIG. 11 can be simultaneously generated from the two data LM_out and LM_thr. Simultaneous generation of the above-mentioned hatched portions means that data of the above-mentioned hatched portions is generated in LM_out and LM_thr at the same time.
[0049]
FIG. 12 shows the bit configuration of the data in the hatched portion in FIG. In the drawing, data separated from LM_in, LM_thr, and LM_out are shown in the upper row for each bit width, and the data array in filter processing A and B corresponding to the data is shown in the lower row.
[0050]
6 is controlled by the LM input data generation circuit 250 in FIG. 6 and LM_thr is controlled by the LM pass data generation circuit 251. Regarding LM_out, the data read from LM5 already has the bit configuration shown in FIG.
[0051]
FIG. 13 shows a timing chart in the filtering processes A and B. (A) shows the case where there is no delay in the operation in the filter processing, where RA indicates the read address of LM5 and WA indicates the write address. The LM5 in this example uses a synchronous memory having a bit width of 32 bits, a processing target bit width of 8 bits, and outputting data of an address designated by RA one clock after the clock.
[0052]
At this time, control is performed so that the lower 16 bits of LM5 are used for filter processing A and the upper 16 bits are used for filter processing B. That is, control is performed so that the LM5 and the signal lines 210 and 302 can be used by being divided into two in accordance with the bit width of the image data by the filtering processes A and B.
[0053]
Next, the relationship between the operation of the LM 5 and the filter processing A and the filter processing B will be described more specifically with reference to FIGS. FIG. 14 is a conceptual diagram for explaining the data array on the image screen to be processed and the data array of LM5. The LM5 uses a synchronous memory that outputs the data at the address specified by RA one clock after. Image data used in the filter A is indicated by circled numbers, and image data used in the filter B is indicated by double circled numbers. As shown in the figure, when RA (= 8) and WA (= 7) are instructed to LA5, filter processing A performs processing of data 68 using nine image data in a rectangle, and filter processing B similarly. In, processing of the result data 57 (corresponding to the image data 57) of the processing A is performed. The following description focuses on the filter processing indicated by a rectangle.
[0054]
FIG. 15 is an explanatory diagram in which the operation of the LM 5 is monitored for three clock periods as in (a) to (c). Hereinafter, the data used in the filter A is distinguished by adding a suffix a, and the data used in the filter B is given a suffix b.
[0055]
In the state of FIG. 3A, WA = 5 and RA = 6. When the image data 59a is input from the image memory 100, the LM 5 is controlled so as to output the image data 57a and 58a in synchronization with the input. At this time, the filter processing A performs the filter processing using the image data of 37a, 38a, 39a, 47a, 48a, 49a, 57a, 58a, 59a, and the processing result is data 48b. The data 48b is used as an input of the LM5, and at the same time, is used for the filtering B. The filter processing B uses the result data 26b, 27b, 28b, 36b, 37b, 38b, 46b, 47b, 48b of the processing A to output the processing result at the position 37.
[0056]
Next, in the state of FIG. 7B one clock later, WA = 6 and RA = 7, and the output from LM5 is data 56b, 57b, 67a, 68a of the address specified one clock earlier. At this time, the image data input from the image memory 100 is 69a, and the processing result data of the filter processing A is 58b. The processing result data of the filter processing B is data at the position of 47. Further, in the state of FIG. 10C after one clock, WA = 7 and RA = 8, and the outputs from LM5 are data 66b, 67b, 77a and 78a. The processing result data of the filter processing A is 68b, and the processing result data of the filter processing B is data at the position of 57.
[0057]
Thus, the clocks WA and RA are counted up in accordance with the bit width of the image data input from the image memory 100. Then, the LM 5 is controlled so that the 3 × 3 filter processing can be executed in synchronization with the image data read from the image memory 100.
[0058]
The above-described operation of the LM5 is a description of the two-stage pipeline processing. However, regarding the individual filter processing A or the filter processing B, the operation of the ordinary 3 × 3 filter processing or 5 × 5 filter processing is different. Will be the same.
[0059]
Further, in the present embodiment, the number of delay stages of the operation in the filtering process is not considered, but the number of delay stages may be considered. When the number of delay stages is considered, as shown in FIG. 13B, the difference between the data combination of the filter processing A and the data of the filter processing B in LM_in and LM_thr is only one clock, and the control method has no delay. Is exactly the same as
[0060]
As described above, according to the present embodiment, the input / output of the line memory can be easily controlled by a combination of data, so that filter processing with different filter sizes, and further, pipeline processing and parallel processing can be performed by a common hardware (resource ) Can be efficiently realized by changing the processing configuration. Hereinafter, another embodiment having a different processing mode will be described.
[0061]
FIG. 16 shows a bit configuration of data input to the 3 × 3 filter processing 901 in the processing configuration of FIG. 2B in which the bit width of image data is 16 bits. As in the case of FIG. 12, LM_in, LM_thr, and LM_out indicate data to be controlled in the upper row, and target data in the filter processing A901 corresponding to the data are shown in the lower row. As in the previous example, the control of separating these bits is performed by the LM input data generation circuit 250 for LM_in and by the LM passage data generation circuit 251 for LM_thr. As for LM_out, the data read from LM5 has the bit configuration already shown in FIG.
[0062]
FIG. 17 shows a processing configuration in which the bit width of the image data is 1 bit and 16 stages of A to P pipeline processing are performed. Also in this case, LM5 is divided into LM0 to LM31 with a 1-bit width, and LM_in, LM_thr, and LM_out data to be input to each 3 × 3 filter are divided into 1-bit widths in comparison with the 8-bit width in FIG. By controlling, it can be realized similarly.
[0063]
As described above, the input / output of the LM is controlled in accordance with the bit width of the image data, and the number of LMs used is substantially optimized, thereby enabling a plurality of stages of pipeline processing and realizing high-speed image processing. ing.
[0064]
FIG. 18 shows the configuration of an image processing apparatus using parallel processing according to the present invention. As shown in the drawing, the configuration is the same as that of the embodiment of FIG. 1 except that n processing target memory units 100 and n processing result memory units 700 are used.
[0065]
FIG. 19 shows a processing configuration of two parallel processes. The processing configuration when parallel processing of two 3 × 3 filter processes A using an LM having a 32-bit width and an image data having a bit width of 8 bits is shown. As shown in FIG. 2B, when one screen is divided into two and processed in parallel, the processing time for performing the filter processing A by one can be reduced to half.
[0066]
This processing configuration can be easily changed from the processing configuration of the pipeline in FIG. For example, in the LM input data control circuit 200, it is only necessary to change the processing result data transmitted by the feedback unit 800 to image data from the processing target memory unit 100. Therefore, an arbitrary configuration is possible such that the processing configuration of FIG. 3 is employed when pipeline processing is required, and the processing configuration of FIG. 14 is employed when parallel processing is required. Of course, a change from the processing configuration of FIG. 2C is also possible.
[0067]
【The invention's effect】
According to the present invention, the number of theoretical line memories is changed by changing the bit width of the line memory for one line together with the bit width of the image data to be handled. The processing configuration corresponding to the function can be changed flexibly within the range of the scale of the line memory or the arithmetic unit.
[0068]
Further, according to the present invention, it is possible to freely configure a plurality of stages of pipeline processing and a plurality of sets of parallel processing by controlling input / output of a line memory according to a bit width of image data to be handled and an image processing size. And the speed of image processing can be increased.
[0069]
That is, according to the present invention, it is possible to provide various processing configurations according to the bit width of image data to be handled and the setting function of image processing, so that an image processing apparatus with excellent versatility and high resource use efficiency is provided. it can.
[Brief description of the drawings]
FIG. 1 is an overall configuration diagram of an image processing apparatus according to an embodiment of the present invention.
FIG. 2 is a conceptual diagram showing various processing configurations of an image processing apparatus using a line memory.
FIG. 3 is a conceptual diagram showing a processing configuration of an image processing apparatus for pipeline processing according to the present invention.
FIG. 4 is a table showing setting contents of image information and image processing function information.
FIG. 5 is an explanatory diagram showing a flow of processing by a configuration control unit and an example of a control signal to be issued;
FIG. 6 is a functional block diagram showing a configuration of an LM input data control circuit for controlling input data of a line memory and peripheral circuits thereof.
FIG. 7 is a functional block diagram showing a configuration of an LM output data control circuit.
FIG. 8 is a functional block diagram illustrating a circuit configuration of an image processing unit that implements 3 × 3 filter processing.
FIG. 9 is a functional block diagram illustrating a circuit configuration of an image processing unit that implements 5 × 5 filter processing.
FIG. 10 is a conceptual diagram showing a theoretical division configuration of a line memory.
FIG. 11 is an explanatory diagram showing transition of block data for realizing pipeline processing of 3 × 3 filter processing.
12 is a data configuration diagram corresponding to a hatched portion in FIG. 11 and showing LM input data, LM passing data, and LM output data for each bit width.
FIG. 13 is a timing chart of the block data of FIG. 11;
FIG. 14 is an explanatory diagram showing block data and the position of a line memory in pipeline processing of 3 × 3 filter processing.
FIG. 15 is an explanatory diagram showing data movement of a line memory in detail.
FIG. 16 is a data configuration diagram showing LM input data, LM passing data, and LM output data for each bit width when image data has a 15-bit width in another embodiment of the present invention.
FIG. 17 is a conceptual diagram of a processing configuration for performing 3 × 3 filter processing in a case where image data has a 1-bit width by 16-stage pipeline processing in another embodiment of the present invention.
FIG. 18 is an overall configuration diagram of an image processing apparatus that performs n sets of parallel processing according to another embodiment of the present invention.
FIG. 19 is an explanatory diagram of a processing configuration for performing two parallel processing of 3 × 3 filter processing and a target memory;
FIG. 20 is a functional block diagram showing a configuration of an LM output data control circuit according to another embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Control device, 2 ... Bus interface between a control device and an image processing device, 3 ... Configuration control unit, 5 ... Line memory (LM), 90 ... Image processing unit, 100 ... Memory to be processed, 200 ... LM input data Control circuit, 250 LM input data generation circuit, 300 LM output data control circuit, 311-314 delay circuit, 321-324 delay circuit, 330 output data bit separation circuit, 400 PU, 500 data integration circuit , 600: data selection control circuit, 700: processing result memory unit.

Claims (9)

An image memory for storing image data to be processed, an image processing circuit for performing predetermined image processing, and a line memory for converting the image data read from the image memory into block data according to the processing size and outputting the block data to the image processing circuit An image processing apparatus comprising:
Said cut line width of the line memory in accordance with the bit width of the image data, theoretically, to configure the plurality of divided line memories, and the division of the number to be used in accordance with the image processing function to be set (setting function) the output of the line memory, image processing apparatus characterized by comprising a configuration control means for control so as to correspond to the image processing circuit. According to claim 1, wherein the configuration control means in response to the image processing function to control the combination of a plurality of arithmetic circuits in the image processing circuit,
An image processing apparatus capable of changing a processing size such as 3 × 3 or 5 × 5 and / or changing a processing mode such as pipeline or parallel processing. An image memory for storing image data to be processed, an image processing circuit for performing predetermined image processing, and a line memory for converting the image data read from the image memory into block data according to the processing size and outputting the block data to the image processing circuit An image processing apparatus comprising:
The line width of the line memory is cut in accordance with the bit width of the image data to theoretically constitute a plurality of divided line memories, and the number of lines used in accordance with the set image processing function (setting function) is divided. the output of the line memory, and control Gosuru configuration controller to correspond to the said image processing circuit,
A line memory input data control unit that generates input data to be input to the line memory under the control of the configuration control unit, and a line memory output data control unit that generates the block data from data output from the line memory;
An image processing apparatus wherein a processing configuration can be arbitrarily changed within a range of a line width of the line memory. 4. The image processing function according to claim 3, wherein the number L used is (i−1) × P in P-stage pipeline processing by i × i filter processing having different image processing functions .
The configuration control means sets the divided line memory used for each stage of the pipeline processing to an L / P line group, and directly inputs the image data read from the image memory to the foremost image processing circuit. The input / output control of the line memory is controlled so that a line group including a line memory is associated, and a line group including a divided line memory for inputting processing data of a previous stage is sequentially associated with a subsequent image processing circuit. An image processing apparatus characterized in that the image processing is performed. 5. The image processing apparatus according to claim 4, wherein the line memory input data control unit is configured to calculate the image data read from the image memory, a part of output data of the line memory, and processing result data of each stage of the image processing circuit. An image processing apparatus for generating input data to be input to all divided line memories. 4. The image processing function according to claim 3, wherein the image processing function is the parallel processing of Q sets by the same i × i filter processing, and the number L used is (i−1) × Q.
The configuration control means sets the divided line memory used for each set of parallel processing to L / Q line groups, and divides one screen of image data stored in the image memory into Q in the vertical direction, and An image processing apparatus which controls image data read out in parallel from an area to be input to a corresponding line group. 7. The configuration control unit according to claim 4, wherein the configuration control unit sets a processing mode such as a filter size (i × i) indicating the image processing function , a processing number (1 or P or Q), and a pipeline. Then, control to configure the image processing circuits for the number of processes by an arithmetic circuit corresponding to the filter size,
In the image processing apparatus, when the processing mode is a pipeline, control is performed so that processing result data of each of the image processing circuits is fed back to the line memory input data control means. An image memory for storing image data to be processed, an image processing circuit for performing predetermined image processing, and a line memory for converting the image data read from the image memory into block data according to the processing size and outputting the block data to the image processing circuit An image processing apparatus comprising:
P sets of image processing circuits for performing P stages of pipeline processing by different i × i filter processes;
The line width of the line memory is cut in accordance with the bit width of the image data to theoretically constitute L (= (i−1) × P) divided line memories and set image processing functions A configuration control means for controlling input / output of the line memory by associating a divided line memory used in accordance with (setting function) with each image processing circuit for each of L / P line groups;
From the image data read from the image memory, a part of the output data of the line memory, and the processing result data of each stage of the image processing circuit, the line memory is input to all lines theoretically cut off. Line memory input data control means for generating input data for
A line memory output data control unit that generates the block data from data output from the line memory,
An image processing apparatus wherein a pipeline processing configuration can be arbitrarily changed within a range of a line width of a line memory. In claim 8, when i = 3 and P = 2,
The line memory input data control means transmits the M bits of the width of the image data read from the image memory and the M bits obtained from the output data by the image data read one clock before to the preceding image processing circuit. In the line group consisting of the two corresponding divided memories, the M bits of the processing result data of the preceding image processing circuit and the M bits of the processing result data one clock before this line correspond to the subsequent image processing circuit. Control to input to a line group consisting of two divided memories,
The line memory output data control means includes: a data set of three lines on the screen of the image data read from the image memory and two image data output from the preceding line group; one clock before the data set and two clocks; Nine data blocks are generated by combining the preceding data sets, and the preceding processing result data and the second processing result data output from the subsequent line group are sent to the preceding image processing circuit in the same manner as in the preceding stage. An image processing apparatus, which controls so as to generate a data block and output the generated data block to a subsequent image processing circuit.

Images