JPH08171538A - Signal processor - Google Patents

Abstract

PURPOSE: To provide the signal processor which can perform parallel processings with small bus constitution and is suitable for a convergence type processing of an image. CONSTITUTION: An arithmetic array 100b is composed of 10 arithmetic cells (E[x, y]) 103b which are specified with column numbers (x) (1<=x<=4) and row numbers (y) (x<=y<=4) and can be put in parallel operation. Each arithmetic cell 103b has one multiplier and one adder inside for product sum arithmetic operation. Input data to an arithmetic cell E[x, y] (2<=x and x<=y<=4) is supplied from an arithmetic cell E[x-1, y] and an arithmetic cell E[x-1, y-1] through a direct bus 109 and an oblique bus 110. For example, when pixel data regarding four pixels which are arrayed horizontally in an image are supplied individually to four arithmetic cells in the 1st column, arithmetic cells in the 4th column output the results of horizontal filter arithmetic operation of four taps.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device such as an image processing device.

[0002]

2. Description of the Related Art In recent years, in the field of image processing for moving images and still images, digitalization of analog filters such as high-pass filters and low-pass filters is progressing. Further, in order to support multimedia and the like, hardware capable of performing a plurality of filter calculations is required.

C. Joanblanq, et al., "A 54-MHz CMOS Pro
grammable Video Signal Processor for HDTV Applicati
ons ", IEEE Journal of Solid-State Circuits, Vol.25, N
O.3, pp. 730-734, June 1990, a programmable digital signal processor for HDTV is shown.
This is a one-chip operation unit in which a plurality of product-sum operation cells each having a multiplier and an adder are connected in cascade. According to this signal processing device, for example, the coefficient a1
, A2, a3, and the i-th input data (pixel data) is gi, the three tap-and-add operation cells are cascaded to obtain a 3-tap horizontal filter operation a1 x gi
+ A2 xg (i + 1) + a3 xg (i + 2) is executed.

In order to improve the image processing speed, it is necessary to operate a plurality of product-sum operation cells as described above in parallel.

Japanese Patent Laid-Open No. 59-172064 discloses an image in which a large number of MPUs (microprocessor units) are arranged in a two-dimensional lattice corresponding to display pixels and image processing operations are executed in parallel in each MPU. A processing device has been proposed. In this image processing apparatus, a data bus is provided between each MPU and four MPUs vertically and horizontally adjacent to each other.

Further, in Japanese Patent Laid-Open No. 60-159973,
Multiple PEs (processor elements) and multiple MEs
(Memory element), and an image processing apparatus has been proposed in which all PEs and all MEs are connected to a plurality of common buses. In this image processing apparatus, each PE and each ME are given a bus number indicating which of the plurality of common buses should be used.

[0007]

The filter processing is a multi-input / single-output convergent processing. Therefore, in the case of adopting a filter configuration in which a large number of multiply-accumulate operation cells that can be operated in parallel are arranged in a two-dimensional lattice and these are connected vertically and horizontally by a data bus, the data bus configuration becomes redundant. Become. When a filter configuration in which all product-sum operation cells that can operate in parallel are connected to a plurality of common buses, the common bus selection control becomes redundant.

An object of the present invention is to provide a signal processing device suitable for convergent processing which can execute parallel processing with a small bus configuration.

[0009]

In order to achieve the above object, the first signal processing device according to the present invention has a plurality of arithmetic cells which can operate in parallel in a pyramid shape, as shown in FIG. The cells are two-dimensionally arranged so as to form a hierarchical structure, and the operation cells are connected by a data bus so as to form a tree structure. Specifically, the first signal processing device of the present invention includes a calculation means for performing arithmetic calculation processing on data and a first calculation means for inputting a data signal from the outside to supply the data to the calculation means. An interface means and a second interface means for receiving the data subjected to the arithmetic operation processing from the arithmetic means and outputting the data signal to the outside, wherein the arithmetic means are two or more. Has an array of a plurality of arithmetic cells E [x, y] capable of parallel operation specified by two subscripts x and y satisfying 1 ≦ x ≦ M and x ≦ y ≦ M for an integer M of , Operation cell E
The input data of [1, y] (1 ≦ y ≦ M) is supplied from the first interface means, and the operation cell E [x, y] is supplied.
The input data of (2 ≦ x ≦ M and x ≦ y ≦ M) is supplied from the operation cell E [x-1, y] and the operation cell E [x-1, y-1], and the operation cell E [M, The output data of M] is the second
Of the interface means.

According to the first signal processing apparatus, the multi-input / single-output convergent processing is executed by the parallel operation of the plurality of arithmetic cells. Moreover, since a tree-structured data bus suitable for convergent processing is adopted, the bus configuration becomes small.

A second signal processing device according to the present invention is shown in FIG.
As illustrated in FIG. 5, a plurality of operation cells that can operate in parallel are two-dimensionally arranged so as to form a pyramid-like hierarchical structure, and an individual common bus is provided between each hierarchy. Specifically, a second signal processing device of the present invention is a first processing unit for applying arithmetic processing to data and a first processing unit for inputting a data signal from the outside and supplying the data to the processing unit. An interface means and a second interface means for receiving the data subjected to the arithmetic operation processing from the arithmetic means and outputting a data signal to the outside, wherein the arithmetic means is 2
An array of a plurality of arithmetic cells E [x, y] capable of parallel operation, which are specified by two subscripts x and y satisfying 1 ≦ x ≦ M and x ≦ y ≦ M with respect to the above integer M; 1 or more and M-1
The operation cell E [k, y] (k
≦ y ≦ M) and the operation cell E [k + 1, y] (k + 1 ≦ y ≦
M) and a time-division multiplexed common bus B [k], and the input data of the arithmetic cell E [1, y] (1≤y≤M) is supplied from the first interface means. , The input data of the operation cell E [k + 1, y] (k + 1 ≦ y ≦ M) is transferred from the operation cell E [k, y] (k ≦ y ≦ M) to the common bus B.
The output data of the operation cell E [M, M] supplied via [k] is supplied to the second interface means.

According to the second signal processing apparatus described above, the multi-input / one-output convergent processing is executed by the parallel operation of the plurality of arithmetic cells. Moreover, since the time-division multiplexed common buses are provided between the respective layers, the bus configuration can be reduced and the use of the common bus suitable for the convergent processing can be realized.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Nine image processing devices as signal processing devices according to embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of an image processing apparatus according to a first embodiment of the present invention. 1 in FIG.
00 is the column number x (1 ≦ x ≦ 4) and the row number y (1
This is an arithmetic array including 16 arithmetic cells (E [x, y]) 103 capable of parallel operation specified by ≦ y ≦ 4). The operation array 100 performs arithmetic operation processing on the data supplied from the input unit 102 and outputs the result to the output unit 1.
It supplies to 20. Operation cell E [1, in the first column
y] (1 ≦ y ≦ 4) is A1, B1, C1 and D1, second
The operation cells E [2, y] (1 ≦ y ≦ 4) in the columns are set to A2 and B.
2, C2 and D2, operation cell E [3, y] (1 in the third column
.Ltoreq.y.ltoreq.4) are named A3, B3, C3 and D3, and the arithmetic cells E [4, y] (1.ltoreq.y.ltoreq.4) in the fourth column are named A4, B4, C4 and D4, respectively. A data signal (pixel signal) from the outside is supplied to the input unit 102 via the four inputs 104. From the input unit 102 to the operation cell D1 of the first column
Data buses 105 and 10 are connected to C1, B1 and A1, respectively.
Data is individually supplied via 6, 107 and 108. Operation cell E [x, y] (2 ≦ x ≦ 4 and 2 ≦ y ≦
The input data of 4) is supplied from the operation cell E [x-1, y] and the operation cell E [x-1, y-1] via the data buses 109 and 110. Operation cell E [x-1, y]
To the operation cell E [x, y] is called a direct bus, and the data bus 110 from the operation cell E [x-1, y-1] to the operation cell E [x, y] is an oblique bus. Say Direct buses 109 are provided between the arithmetic cells A1, A2, A3, A4 in the first row. Data is individually supplied from the arithmetic cells D4, C4, B4, A4 in the fourth column to the output section 120 via the data buses 111, 112, 113, 114, respectively. The output unit 120 is 4
Data signal (pixel signal) to the outside through one output 121
Is output. The image processing apparatus in FIG. 1 further includes an MPU 11 and a memory 12, which will be described in detail later.

FIG. 2 shows an internal configuration example of the input unit 102 when the image processing apparatus of FIG. 1 is operated as a 4-tap horizontal filter. The input unit 102 of FIG. 2 includes three latches 20 connected in series for holding data.
1, 202, 203. In this example, pixel data g1 about four pixels arranged horizontally in the image,
g2, g3, g4 are the operation cells A1, B1, C in the first column
1 and D1, the pixel signal g supplied from the outside through one of the four inputs 104 is supplied to the data bus 105 as pixel data g4 and to the first stage latch 201. Supplied, first stage latch 20
1 is the pixel data g3 to the data bus 106, and the second stage latch 202 is the pixel data g2 to the data bus 107.
The latch 203 in the second stage transfers the pixel data g1 to the data bus 10
8 respectively.

The internal structure of the arithmetic cell A1 in FIG. 1 is shown in FIG. In FIG. 3, 131 is a rewritable coefficient register, 133 is a multiplier, 135 is an adder, and 136 is a latch. The multiplier 133 outputs the product of the coefficient held in the coefficient register 131 and the first input 132 supplied via the data bus 108. Adder 1
35 is the product output from the multiplier 133 and the second input 1
It outputs the sum with 34. The latch 136 holds the sum output from the adder 135 and outputs the held sum to the orthogonal bus 109 and the skew bus 110. The other operation cell 103 in FIG. 1 is also the operation cell A in FIG.
It has the same internal configuration as that of 1. However, the calculation cell E
[X, y] (2 ≦ x ≦ 4 and 2 ≦ y ≦ 4), that is, operation cells B2, C2, D2, B3, C3, D3, B4, C
4 and D4, the first input 132 is supplied from the direct bus 109, and the second input 134 is supplied from the oblique bus 110.

When a processing switching request signal is given through the control input 21, the MPU 11 shown in FIG. 1 receives through the data bus 22 the coefficient register 131 of each of the 16 arithmetic cells 103 constituting the arithmetic array 100. 7 arithmetic cells A having a coefficient set in and a first row and a first column
Second of each of 1, A2, A3, A4, B1, C1, D1
A constant is set in the input 134 of the. The memory 12 stores a program to be executed by the MPU 11 in response to the process switching request signal and data to be used for setting.

FIG. 4 is a diagram for explaining the operation of the arithmetic array 100 in FIG. Operation cells A1, B1, C1, D in the first column
Each of the coefficient registers 131 of 1 has coefficients a1, a2,
a3 and a4 are preset. Operation cell A2 in the second column
Coefficients 0, 0, 0, 1 are preset in the coefficient registers 131 of B2, C2, D2. The setting of the coefficient register 131 of the arithmetic cells of the third and fourth columns is the same as that of the second column. Further, the second inputs 134 of the seven arithmetic cells A1, A2, A3, A4, B1, C1, D1 forming the first row and the first column are all set to 0 in advance.

Pixel data g1, g2, g3, and g4 relating to four pixels arranged in the horizontal direction are input from the input unit 102 to the first pixel data.
When supplied to the operation cells A1, B1, C1, D1 of the column, the operation cell A1 gives a1 * g1 and the operation cell B1 gives a2.
Xg2, operation cell C1 is a3 xg3, operation cell D1
Outputs a4 × g4 respectively. As a result, in the second column, the arithmetic cell A2 has a1 * g1 and the arithmetic cell B2 has a1.
Xg1 and a2 xg2, the operation cell C2 is a2 xg2 and a3 xg3, and the operation cell D2 is a3 xg3 and a4 x
Receive each g4. Therefore, the operation cell A2 is 0
The operation cell B2 is a1 × g1 and the operation cell C2 is a2.
Xg2, and the operation cell D2 outputs a3 xg3 + a4 xg4. In the third column, the arithmetic cell A3 is 0, the arithmetic cell B3 is 0 and a1 * g1, and the arithmetic cell C3 is a1 * g.
1 and a2 × g2, and the operation cell D3 has a2 × g2 and a
Receive 3 x g3 + a4 x g4 respectively. Therefore, the arithmetic cells A3 and B3 are both 0, and the arithmetic cell C3 is a1.
Xg1 and the operation cell D3 is a2 xg2 + a3 xg3 + a
Output 4 x g4 respectively. In the fourth column, the arithmetic cell A4 is 0, the arithmetic cell B4 is 0 and 0, the arithmetic cell C4 is 0 and a1 x g1, and the arithmetic cell D4 is a1 x g1 and a2 x.
Receive g2 + a3 xg3 + a4 xg4 respectively. Therefore, the arithmetic cells A4, B4 and C4 are all 0, and the arithmetic cell D4 is a1 * g1 + a2 * g2 + a3 * g3 + a4.
Output xg4 respectively. Output data a1 of operation cell D4
Xg1 + a2 xg2 + a3 xg3 + a4 xg4 is output via the output unit 120 as the processing result of the horizontal filter.

As described above, according to the image processing apparatus of FIG. 1, ten arithmetic cells A1, B1, C1, D1, B2 connected to each other by the tree-structured data buses 109 and 110 are connected.
By mainly using C2, D2, C3, D3, and D4, 4-tap horizontal filter processing is executed. If the setting contents of the coefficient register 131 are changed so that the six arithmetic cells A2, B2, C2, B3, C3, and C4 are mainly used, it is possible to execute the horizontal filter process of 3 taps. In addition, a group consisting of the three arithmetic cells A3, B3, B4 and another group consisting of the three arithmetic cells C3, D3, D4 are operated independently to perform horizontal filter processing of 2 taps. It is also possible.

The latches 201 to 201 in the input unit 102
If each of 203 is replaced by a line memory, the arithmetic array 100 can be operated as a vertical filter having 2 to 4 taps. In addition, the latch 201 in the input unit 102
It is also possible to operate the arithmetic array 100 as a temporal filter by replacing each of to 203 with a field memory. The input unit 102 may be configured to supply each of the pixel signals supplied from the outside via the four inputs 104 as pixel data to the operation cells A1, B1, C1, D1 in the first column.

In the example of the 4-tap horizontal filter, only one of the four outputs 121 of the output section 120 is used. However, the arithmetic cells A4, B4, C4 in the fourth column
If valid data is output from each D4, 4
All one of the outputs 121 can be used. In this case, if the output unit 120 has a built-in buffer memory,
It is also possible to use one output 121 in the form of time division multiplexing.

The arithmetic array 100 is not limited to 4 rows and 4 columns,
Other configurations such as 4 rows and 8 columns may be used. Each operation cell 103
Is one multiplier 133 and one adder 1 as shown in FIG.
The configuration is not limited to the configuration of the multiply-accumulate operation cell including 35 and 35, and other configurations may be adopted. For example, in the seven arithmetic cells A1, A2, A3, A4, B1, C1 and D1 in which 0 is set to the second input 134 in the example of the 4-tap horizontal filter,
The addition of the adder 135 may be omitted, and the output of the multiplier 133 may be directly supplied to the latch 136. Further, a plurality of multipliers and a plurality of adders for the product-sum calculation may be incorporated in each calculation cell 103. Multiple calculation cells 1
It is also possible to configure each of 03 with MPU.

(Embodiment 2) FIG. 5 is a block diagram of an image processing apparatus according to a second embodiment of the present invention. As in the case of FIG. 1, the image processing apparatus of FIG. 5 also has an operation array 100a for performing arithmetic operation processing on data and an input unit for inputting a data signal from the outside and supplying the data to the operation array 100a. 102a, and an output unit 120a for receiving the data subjected to the arithmetic operation processing from the operation array 100a and outputting the data signal to the outside.
The operation array 100a of FIG. 5 has column numbers x (1 ≦ x ≦
4) and 16 arithmetic cells (E [x, y]) 103a capable of parallel operation designated by the row number y (1 ≦ y ≦ 4). In the operation array 100a, the input data of the operation cell E [x, y] (2 ≦ x ≦ 4 and 2 ≦ y ≦ 4) is the operation cell E [x-1, y] and the operation cell E [x-.
1, y-1] is supplied via the orthogonal bus 109 and the oblique bus 110, and the arithmetic cell E [x, 1] (2 ≦ x ≦ 4)
Input data is supplied from the arithmetic cell E [x-1,1] via the orthogonal bus 109. Moreover, E [x, y] (2
The input data of ≦ x ≦ 4 and 1 ≦ y ≦ 3) is further supplied from the arithmetic cell E [x-1, y + 1] via the reverse skew bus 119. That is, the arithmetic array 100a of the present embodiment is obtained by adding nine reverse skew buses 119 to the arithmetic array 100 of FIG. 1, and one of them is, for example, from the arithmetic cell D1 to the arithmetic cell C2. is there. The image processing apparatus in FIG. 5 further includes an MPU 11a and a memory 12a for setting a coefficient register built in each arithmetic cell 103a.

The image processing apparatus of FIG. 5 having the direct bus 109, the oblique bus 110, and the reverse oblique bus 119 enables more flexible processing than the image processing apparatus of FIG. In the arithmetic array 100 of FIG. 1, for example, arithmetic cells A1 to C2, arithmetic cells B1 to D
Data buses extending to 2 may be added.

(Embodiment 3) FIG. 6 is a block diagram of an image processing apparatus according to a third embodiment of the present invention. 1 in FIG.
00b is a column number x (1≤x≤4) and a row number y, respectively.
It is an arithmetic array provided with 10 arithmetic cells (E [x, y]) 103b capable of parallel operation specified by (x ≦ y ≦ 4). The arithmetic array 100b is for performing arithmetic operation processing on the data supplied from the input unit 102b and supplying the result to the output unit 120b. The operation cells E [1, y] (1 ≦ y ≦ 4) in the first column are A1, B1, C1 and D1, and the operation cells E [2, y] (2 ≦ y ≦ 4) in the second column are B2. C2 and D2, operation cell E [3, y] in the third column
(3 ≦ y ≦ 4) is C3 and D3, and the operation cell E in the fourth column
Name [4,4] as D4. A data signal (pixel signal) from the outside is supplied to the input unit 102b via the four inputs 104. Data is individually supplied from the input unit 102b to the arithmetic cells D1, C1, B1, A1 in the first column via the data buses 105, 106, 107, 108, respectively. The input data of the operation cell E [x, y] (2 ≦ x ≦ 4 and x ≦ y ≦ 4) is the operation cell E [x−1,
y] and the operation cell E [x-1, y-1] to the direct bus 1
09 and skew bus 110. The data bus 11 is provided from the arithmetic cell D4 in the fourth column to the output section 120b.
Data is supplied via 1. The output unit 120b is 1
Data signal (pixel signal) to the outside through one output 121
Is output. The image processing apparatus in FIG. 6 further includes an MPU 11b and a memory 12b, which will be described in detail later.

6 of the input unit 102b when the image processing apparatus of FIG. 6 is operated as a device having three functions of a horizontal filter function of 2 taps, a vertical filter function of 2 taps, and a synthesis function of the outputs of both filters. An example of the internal configuration is shown in FIG. The input unit 102b shown in FIG. 7 has one line memory 301 and two latches 302 and 303 for holding data. In this example, the operation cell D
The pixel data h3 one line before the pixel data g3 supplied to 1 is supplied to the operation cell C1, and the pixel data h1, h2, h3 relating to three pixels arranged in the horizontal direction are supplied to the operation cells A1, B1, C1. As supplied, the pixel signal g supplied from the outside via one of the four inputs 104 is supplied to the data bus 105 as the pixel data g3 and is also supplied to the line memory 301. Pixel data h3 to the data bus 106,
The first-stage latch 302 transfers the pixel data h2 to the data bus 1
07, the second stage latch 303 supplies the pixel data h1 to the data bus 108.

The internal structure of the arithmetic cell B1 in FIG. 6 is shown in FIG. The configuration of FIG. 8 is different from the configuration of FIG. 3 described above in that the rewritable second coefficient register 137 and the selector 13 are provided.
8 is added. A coefficient register (first coefficient register) 131, a multiplier 133 and an adder 1 in FIG.
The functions of 35 are the same as in the case of FIG. 3, respectively. The latch 136 in FIG. 8 holds the sum output from the adder 135, outputs the held sum to the orthogonal bus 109, and supplies the sum to the selector 138. Selector 138
Outputs one of the coefficient held in the second coefficient register 137 and the output of the latch 136 to the skew bus 110. The other operation cell 103b in FIG. 6 also has the same internal configuration as the operation cell B1 in FIG. However,
In the operation cells E [x, y] (2 ≦ x ≦ 4 and x ≦ y ≦ 4), that is, in the operation cells B2, C2, D2, C3, D3 and D4, the first input 132 is from the direct bus 109 to the second Inputs 134 are respectively supplied from the skew buses 110.

When the processing switching request signal is given through the control input 21, the MPU 11b shown in FIG. 6 receives the first data from each of the ten arithmetic cells 103b constituting the arithmetic array 100b through the data bus 22. Coefficient register 131
And a second coefficient register 137, and a constant is set in the second input 134 of each of the arithmetic cells A1, B1, C1, D1 in the first column. Memory 12b
Stores a program to be executed by the MPU 11b in response to the process switching request signal and data to be used for setting.

FIG. 9 is a diagram for explaining the operation of the arithmetic array 100b in FIG. Operation cells A1, B1, C1, in the first column
The first coefficient register 131 of each D1 has a coefficient a,
1, c, d, and the coefficient 0 is preset in the second coefficient register 137. The second input 134 of each of these four arithmetic cells A1, B1, C1, D1 is
Both are set to 0 in advance. Operation cell B2 in the second column
The coefficient b, 0, 1 is preset in the first coefficient register 131 of each of C2 and D2, and the coefficient 0 is preset in the second coefficient register 137. The coefficient 1 is preset in the first coefficient register 131 of each of the arithmetic cells C3, D3, D4 in the third and fourth columns, and the coefficient 0 is preset in the second coefficient register 137.

Four pixel data h1, h2, h3, g3
From the input unit 102b to the operation cells A1, B1, C in the first column
1 and D1 respectively, the operation cell A1 is a × h1
The operation cell C1 is c × h3, and the operation cell D1 is d × g.
Output 3 respectively. The calculation cell B1 has 1 × h2 (= h2
) Is output to the operation cell B2, and the coefficient 0 held in the second coefficient register 137 is output to the operation cell C2. As a result, in the second column, the operation cell B2 is a
Xh1 and h2, 0 and c × h3 in the operation cell C2,
The arithmetic cell D2 receives c * h3 and d * g3, respectively.
Therefore, the arithmetic cell B2 has a × h1 + b × h2, the arithmetic cell C2 has 0, and the arithmetic cell D2 has c × h3 + d × g3.
Are output respectively. Here, the output data a of the arithmetic cell B2
× h1 + b × h2 is the processing result of the 2-tap horizontal filter, and the output data of the operation cell D2 is c × h3 + d × g3.
Is the processing result of the 2-tap vertical filter.

In the third column, the arithmetic cell C3 is a × h1 + b
Xh2 and 0, the arithmetic cell D3 has 0 and c × h3 + d ×
Receive each g3. Therefore, the arithmetic cell C3 is a ×
h1 + b * h2, and the operation cell D3 is c * h3 + d * g3
Are output respectively. The operation cell D4 in the fourth column is a × h1 +
receive b * h2 and c * h3 + d * g3 respectively, and a *
Outputs h1 + b * h2 + c * h3 + d * g3. Output data of operation cell D4 a × h1 + b × h2 + c × h3 +
d × g3 is output via the output unit 120b as a synthesis result of the processing result of the 2-tap horizontal filter and the processing result of the 2-tap vertical filter.

As described above, according to the image processing apparatus of FIG. 6, the group consisting of the three arithmetic cells A1, B1 and B2 and the other group consisting of the three arithmetic cells C1, D1 and D2 are independently provided. By performing the operation, the 2-tap horizontal filtering process and the 2-tap vertical filtering process are executed in parallel. Moreover, the remaining four operation cells C2, C3,
The combination processing of both filter processing results is executed by D3 and D4.

Further, as can be seen from the description of the first embodiment, if the configuration of FIG. 2 is adopted for the input section 102b, ten data buses 109 and 110 of tree structure in the third embodiment are connected to each other. Operation cells A1, B1, C1, D
With 1, B2, C2, D2, C3, D3, and D4, 4-tap horizontal filter processing is executed without waste.

(Fourth Embodiment) FIG. 10 is a block diagram of an image processing apparatus according to a fourth embodiment of the present invention. Reference numeral 100c in FIG. 10 denotes 20 arithmetic cells (E [x, y]) capable of parallel operation, each of which is designated by a column number x (1 ≦ x ≦ 4) and a row number y (1 ≦ y ≦ 5). ) 103c is an arithmetic array. The arithmetic array 100c supplies a result obtained by performing arithmetic operation processing to the data supplied from the first input / output unit 102c to the second input / output unit 120c,
The result obtained by performing arithmetic operation processing on the data supplied from the second input / output unit 120c is the first input / output unit 102c.
To supply to. The four operation cells E [1, y] (2 ≦ y ≦ 5) in the first column are set to A1, B1, C1.
, D1, and three operation cells E [2, y] of the second column
(3 ≦ y ≦ 5) is B2, C2 and D2, two operation cells E [3, y] (4 ≦ y ≦ 5) of the third column are C3 and D3, and operation of the fourth column is Cell E [4,5] is named D4 respectively. Also, four operation cells E [4, y] (4 ≧ y ≧ 1) in the fourth column are set to P1, Q1, R1 and S.
1, three operation cells E [3, y] of the third column (3 ≧
y ≧ 1) is Q2, R2 and S2, two operation cells E [2, y] (2 ≧ y ≧ 1) of the second column are R3 and S3,
The operation cell E [1,1] in the first column is named S4.

The data signal (pixel signal) from the outside is 4
It is supplied to the first input / output unit 102c via one input 104 and to the second input / output unit 120c via the other four inputs 104, respectively. Data is individually supplied from the first input / output unit 102c to the four arithmetic cells D1, C1, B1, A1 in the first column via the data buses 105, 106, 107, 108, respectively. Operation cell E [x, y] (2
≦ x ≦ 4 and x + 1 ≦ y ≦ 5) is input to the operation cell E [x-1, y] and the operation cell E [x-1, y-1].
From the direct bus 109 and the oblique bus 110. Data is supplied from the operation cell D4 in the fourth column to the second input / output unit 120c via the data bus 111. The second input / output unit 120c has one output 121.
A data signal (pixel signal) is output to the outside via the. On the other hand, data is individually supplied from the second input / output unit 120c to the four arithmetic cells P1, Q1, R1, and S1 in the fourth column via the data buses 112, 113, 114, and 115, respectively. It The input data of the operation cell E [x, y] (1 ≦ x ≦ 3 and 1 ≦ y ≦ x) is the operation cell E [x + 1,
y] and operation cell E [x + 1, y + 1] to direct bus 1
09 and skew bus 110. From the operation cell S4 in the first column to the first input / output unit 102c,
Data is supplied via the data bus 116. The first input / output unit 102c outputs a data signal (pixel signal) to the outside via one output 121.

As described above, the arithmetic array 100c of the image processing apparatus shown in FIG. 10 has a structure in which the blank portion of the arithmetic array 100b shown in FIG. 6 is filled with the same arithmetic array. Therefore, when mounting on an LSI, the chip area can be used more effectively than in the case of FIG. The image processing apparatus of FIG. 10 further includes an MPU 11c and a memory 12c for setting a coefficient register incorporated in each arithmetic cell 103c.

According to the image processing apparatus of FIG. 10, ten arithmetic cells A1, B1, C1, D1, B2, C2, D2, which are connected to each other by the tree-structured data buses 109 and 110, are used.
C3, D3, D4 and data bus 10 of the same tree structure
Another 10 operation cells P connected to each other by 9,110
1, Q1, R1, S1, Q2, R2, S2, R3, S
By operating S3 and S4 independently of each other, horizontal filter processing, vertical filter processing, etc. can be executed. Also, these 20 arithmetic cells 103c
A cyclic filter can be easily constructed by making an external connection so as to form a loop.

(Embodiment 5) FIG. 11 is a block diagram of an image processing apparatus according to a fifth embodiment of the present invention. Reference numeral 500 in FIG. 11 denotes a column number x (1 ≦ x ≦ 4) and a row number y, respectively.
This is an arithmetic array provided with 16 arithmetic cells (E [x, y]) 503 capable of parallel operation designated by (1 ≦ y ≦ 4). Similar to the case of FIG. 1, the arithmetic cells E [1,
y] (1 ≦ y ≦ 4) is A1, B1, C1 and D1, second
The operation cells E [2, y] (1 ≦ y ≦ 4) in the columns are set to A2 and B.
2, C2 and D2, operation cell E [3, y] (1 in the third column
.Ltoreq.y.ltoreq.4) are named A3, B3, C3 and D3, and the arithmetic cells E [4, y] (1.ltoreq.y.ltoreq.4) in the fourth column are named A4, B4, C4 and D4, respectively. Operation cells A1 and B in the first column
1, C1, D1 and operation cells A2, B2, C2 in the second column
A time-division-multiplexed first common bus 531 is interposed between D2 and D2 to enable data transfer from any operation cell in the first column to any operation cell in the second column. Has become. Similarly, the second row arithmetic cells A2, B2, C2, D
2 and the arithmetic cells A3, B3, C3, D3 of the third column, a second common bus 532 is provided between the arithmetic cells A3, B of the third column.
3, C3, D3 and operation cells A4, B4, C4 in the fourth column
Third common buses 533 are provided between D4 and D4, respectively.

The operation array 500 performs arithmetic operation processing on the data supplied from the input section 502 and supplies the result to the output section 520. A data signal (pixel signal) from the outside is input to the input unit 50 via four inputs 504.
2 is supplied. Input unit 502 to operation cell D in the first column
1, C1, B1, A1 to data buses 505, 5 respectively
Data is individually supplied via 06, 507, and 508. Data buses 511, 512, 51 are connected from the operation cells D4, C4, B4, A4 in the fourth column to the output section 520, respectively.
Data is supplied individually via 3, 514. The output unit 520 outputs a data signal (pixel signal) to the outside via the four outputs 521. The image processing apparatus of FIG. 11 further includes an MPU 51 and a memory 52, which will be described in detail later.

The internal structure of the arithmetic cell A2 in FIG. 11 is shown in FIG.
It is shown in FIG. In FIG. 12, 541 is an input timing unit, 542 is a processing unit, and 543 is an output timing unit. The input timing unit 541 includes a rewritable register 601, a match detection circuit 602, and an input control unit 603.
When the value set in the register 601 and the value (for example, 0) given in advance to the match detection circuit 602 match, data is input from the first common bus 531. The processing unit 542 has a coefficient register (not shown) for multiplication and addition operation, a multiplier, and an adder, and performs multiplication and addition operation processing on the data supplied from the input timing unit 541.
The result is supplied to the output timing unit 543. The output timing unit 543 includes a rewritable register 611, a match detection circuit 612, and an output control unit 613.
And outputs the data to the second common bus 532 when the value set in the register 611 and the value (for example, 0) previously given to the match detection circuit 612 match. The other arithmetic cell 503 in FIG. 11 also has the same internal configuration as the arithmetic cell A2 in FIG. However, it is not necessary to provide the input timing section 541 for the operation cells D1, C1, B1, A1 in the first column and the output timing section 543 for the operation cells D4, C4, B4, A4 in the fourth column.

When the processing switching request signal is given through the control input 61, the MPU 51 shown in FIG. 11 receives through the data bus 62 the processing unit 542 of each of the 16 processing cells 503 forming the processing array 500. The coefficient is set in the coefficient register (not shown). In addition, this MPU51
Also has a function of setting constants in the register 601 of the input timing unit 541 and the register 611 of the output timing unit 543 of each of the 16 arithmetic cells 503 forming the arithmetic array 500 via the data bus 62. . In the memory 52, a program to be executed by the MPU 51 in response to the process switching request signal, and a register 60
A program to be executed by the MPU 51 for setting constants to 1,611 and data to be used for setting are stored.

FIG. 14 is a timing chart for explaining the operation of the image processing apparatus shown in FIG. FIG. 14 shows an example of five data transfers between arithmetic cells via the first common bus 531 (D1 → D2, C1 → C2, B1 → B2, A1 → A).
2, C1 → B2) is shown. Note that "HiZ" in FIG. 14 indicates a high impedance state of the output.

In the first cycle, the arithmetic cell D in the first column
Pixel data is supplied to each of 1, C1, B1, and A1,
Arithmetic processing is executed in parallel.

In the second cycle, the arithmetic cell D in the first column
1, C1, B1, A1 output timing sections 543
0,3,2,1 is set in the register 611 of the same, and similarly 0,3,2,1 is set in the register 601 of the input timing unit 541 of each of the operation cells D2, C2, B2, A2 in the second column. It As a result, the operation cell D1 becomes the first common bus 5
The data D is output to 31, and the arithmetic cell D2 inputs the data D. During this time, the three operation cells C1 and B in the first column
1, A1 holds the output in a high impedance state.

In the third cycle, the arithmetic cell D in the first column
1, C1, B1, A1 output timing sections 543
1, 0, 3, 2 are set in the register 611 of FIG. It As a result, the arithmetic cell C1 becomes the first common bus 5
The data C is output to 31, and the arithmetic cell C2 inputs the data C. During this time, the three operation cells D1 and B in the first column
1, A1 holds the output in a high impedance state.

In the fourth cycle, the arithmetic cell D in the first column
1, C1, B1, A1 output timing sections 543
2, 1, 0, 3 are set in the register 611 of the same, and similarly, 2, 1, 0, 3 are set in the register 601 of the input timing unit 541 of the operation cells D2, C2, B2, A2 in the second column. It As a result, the arithmetic cell B1 becomes the first common bus 5
The data B is output to 31, and the arithmetic cell B2 inputs the data B. During this time, the three operation cells D1 and C in the first column
1, A1 holds the output in a high impedance state.

In the fifth cycle, the arithmetic cell D in the first column
1, C1, B1, A1 output timing sections 543
3, 2, 1, 0 are set in the register 611 of the same, and similarly, 3, 2, 1, 0 are set in the register 601 of the input timing unit 541 of each of the operation cells D2, C2, B2, A2 in the second column. It As a result, the arithmetic cell A1 becomes the first common bus 5
The data A is output to 31, and the arithmetic cell A2 inputs the data A. During this time, the three operation cells D1 and C in the first column
1, B1 holds the output in a high impedance state.

In the sixth cycle, the arithmetic cell D in the first column
1, C1, B1, A1 output timing sections 543
Of the input timing unit 541 of each of the arithmetic cells D2, C2, B2, A2 of the second column are set to 1, 0, 3, 2 in the register 611 of FIG. It As a result, the arithmetic cell C1 becomes the first common bus 5
The data C is re-output to 31 and the data C is output to the operation cell B2.
To enter. During this time, the three operation cells D1 and B in the first column
1, A1 holds the output in a high impedance state.

As described above, according to the image processing apparatus of FIG. 11, the arithmetic cells D1, C1, B1, A1 in the first column to the arithmetic cells D2 in the second column are connected via the first common bus 531.
Time division multiplexing data transfer to C2, B2, A2 is executed. The function of the second and third common buses 532 and 533 is also the same. Therefore, for example, the data flow as shown in FIG. 4 can be realized also in this embodiment, and the 4-tap horizontal filter processing is achieved. A vertical filter can be realized by introducing a line memory into the input unit 502.

Data may be transferred from one operation cell to a plurality of operation cells at the same time. At least one of the registers 601 and 611 in FIG. 12 can be replaced with a counter that is updated every cycle according to the clock. The example shown in FIG.
2 registers 601 and 611 in 2 are counters 604 and 6
It is replaced with 14. In FIG. 11, the arithmetic array 5
00 has a 4-row cell configuration, so both counters 6
Each of 04 and 614 is composed of 2 bits. If the configuration of FIG.
After the initialization of, the clocks are applied to both counters 604 and 614 to execute the time division multiplexing data transfer.

(Sixth Embodiment) FIG. 15 is a block diagram of an image processing apparatus according to a sixth embodiment of the present invention. Reference numeral 500a in FIG. 15 denotes 10 arithmetic cells (E [x, y]) capable of parallel operation designated by a column number x (1 ≦ x ≦ 4) and a row number y (x ≦ y ≦ 4). ) 503. Similar to the case of FIG. 6, the arithmetic cell E in the first column
[1, y] (1 ≦ y ≦ 4) is A1, B1, C1 and D
1, the operation cell E [2, y] (2 ≦ y ≦ 4) in the second column is B
2, C2 and D2, the operation cell E [3, y] (3
≦ y ≦ 4) is C3 and D3, and the arithmetic cell E [4,
4] as D4. Operation cell A in the first column
1, B1, C1, D1 and operation cells B2, C2 in the second column
A time-division-multiplexed first common bus 531 is interposed between D2 and D2 to enable data transfer from any operation cell in the first column to any operation cell in the second column. Has become. Similarly, the second common bus 5 is provided between the arithmetic cells B2, C2, D2 in the second column and the arithmetic cells C3, D3 in the third column.
32, a third common bus 533 is interposed between each of the arithmetic cells C3 and D3 in the third column and the arithmetic cell D4 in the fourth column.

The operation array 500a performs arithmetic operation processing on the data supplied from the input section 502a and supplies the result to the output section 520a. A data signal (pixel signal) from the outside is supplied to the input unit 502a via the four inputs 504. Data is individually supplied from the input unit 502a to the arithmetic cells D1, C1, B1, A1 in the first column via the data buses 505, 506, 507, 508. Output unit 520 from operation cell D4 in the fourth column
Data is supplied to a via the data bus 511. The output unit 520a outputs a data signal (pixel signal) to the outside via one output 521.

The arithmetic cell 503 in FIG. 15 also has an internal structure similar to that of FIG. 12 or 13. However, the input timing unit 5 is provided in the arithmetic cells D1, C1, B1, A1 in the first column.
41 may not be provided. In addition, the operation cell D4 in the fourth column
The input timing unit 541 and the output timing unit 54
Both of 3 may not be provided. The image processing apparatus of FIG. 15 further includes an MPU 51a and a memory 52a for setting a coefficient register incorporated in each arithmetic cell 503.

According to the image processing apparatus of FIG. 15, for example, the data flow as shown in FIG. 9 can be realized via the first to third common buses 531, 532, 533.

(Embodiment 7) FIG. 16 is a block diagram of an image processing apparatus according to a seventh embodiment of the present invention. The configuration of FIG. 16 is obtained by adding seven bypass buses to the configuration of FIG.

Reference numeral 500b in FIG. 16 is an arithmetic array having 16 arithmetic cells (E [x, y]) 503. Between the operation cell of the first column and the operation cell of the second column, between the operation cell of the second column and the operation cell of the third column, and between the operation cell of the third column and the operation cell of the fourth column Between the first, second, and third common buses 531, 532, 533, each of which is time division multiplexed.
Is intervening.

The arithmetic array 500b performs arithmetic operation processing on the data supplied from the input section 502b and supplies the result to the input / output section 520b. A data signal (pixel signal) from the outside is supplied to the input unit 502b via the five inputs 504. Data is individually supplied from the input unit 502b to the arithmetic cells D1, C1, B1, A1 in the first column via the data buses 505, 506, 507, 508. Fourth row arithmetic cells D4, C4, B4
Data bus 51 is connected from A4 to input / output unit 520b.
Data is individually supplied via 1, 512, 513, and 514. A first bypass bus 711 is interposed between the input unit 502b and the first common bus 531.
Via the bypass bus 711 and the first common bus 531 from the input unit 502b to the second row arithmetic cells D2, C2.
Data can be directly transferred to B2 and A2. A second bypass bus 712 is interposed between the first common bus 531 and the second common bus 532.
Data can be directly transferred from the operation cells D1, C1, B1, A1 in the column to the operation cells D3, C3, B3, A3 in the third column. Furthermore, the third bypass bus 7 going from the second common bus 532 to the third common bus 533.
13 and a fourth bypass bus 714 from the third common bus 533 to the input / output unit 520b.
The input / output unit 520b has a function of outputting a data signal (pixel signal) to the outside through the five outputs 521, and also has a data signal (pixel signal) from the outside through one input 504.
It has a function to input. Moreover, the input / output unit 520
A fifth bypass bus 715 is interposed between the input / output unit 520b and the third common bus 533 so that data can be transferred from b to the arithmetic cells D4, C4, B4, A4 in the fourth column. Furthermore, a sixth bypass bus 716 from the third common bus 533 to the second common bus 532 and a seventh bypass bus 732 from the second common bus 532 to the first common bus 531.
And a bypass bus 717 are provided.

Each arithmetic cell 503 forming the arithmetic array 500b has the structure shown in FIG. However, the register 611 of the output timing unit 543 is replaced with a 3-bit counter 614 (see FIG. 13) whose count value changes in the range of 0 to 5. The image processing apparatus in FIG. 16 further includes an MPU 51b and a memory 52b for initializing the counter 614 of the output timing unit 543 built in each arithmetic cell 503.

FIG. 17 is a timing chart for explaining the operation of the image processing apparatus shown in FIG. FIG. 17 shows an example of three data transfers (D1 → C2, C1 → D2, B1 → A2) between arithmetic cells via the first common bus 531 and data transfer using the first bypass bus 711. Example (input section →
B2) is shown.

In the first cycle, the arithmetic cell D in the first column
Pixel data is supplied to each of 1, C1, B1, and A1,
Arithmetic processing is executed in parallel.

In the second cycle, the arithmetic cell D in the first column
1, C1, B1, A1 output timing sections 543
0, 5, 4, and 3 are set in the counter 614 of. Second
1, 0, 5, 4 are set in the register 601 of the input timing unit 541 of each of the operation cells D2, C2, B2, A2 in the column. As a result, the operation cell D1 outputs the data D to the first common bus 531 and outputs the data D to the operation cell C2.
To enter. During this time, the three operation cells C1 and B in the first column
1, A1 holds the output in a high impedance state.

In the third cycle, the arithmetic cell D in the first column
1, C1, B1, A1 output timing sections 543
Counter 614 is incremented to 1, 0, 5, 4. The register 601 of the input timing unit 541 of each of the arithmetic cells D2, C2, B2, A2 in the second column has 0,
5, 4, and 3 are set. As a result, the arithmetic cell C1 outputs the data C to the first common bus 531 and the arithmetic cell D2 inputs the data C. During this time, the three arithmetic cells D1, B1, A1 in the first column hold the output in the high impedance state.

In the fourth cycle, the arithmetic cell D in the first column
1, C1, B1, A1 output timing sections 543
Counter 614 is incremented to 2, 1, 0, 5. The register 601 of the input timing unit 541 of each of the operation cells D2, C2, B2, and A2 in the second column has 3, 3.
2, 1, 0 is set. As a result, the arithmetic cell B1 outputs the data B to the first common bus 531 and the arithmetic cell A2 inputs the data B. During this time, the three arithmetic cells D1, C1, A1 in the first column hold the output in the high impedance state.

In the fifth cycle, the arithmetic cell D in the first column
1, C1, B1, A1 output timing sections 543
Counter 614 is incremented to 3, 2, 1, 0. The register 601 of the input timing unit 541 of each of the arithmetic cells D2, C2, B2, A2 in the second column has 4,
3, 2, 1 are set. As a result, the arithmetic cell A1 outputs the data A to the first common bus 531 but the arithmetic cell in the second column does not input the data A. During this period, the three arithmetic cells D1, C1, B1 in the first column hold the outputs in the high impedance state.

In the sixth cycle, the arithmetic cell D in the first column
1, C1, B1, A1 output timing sections 543
Counter 614 is incremented to 4, 3, 2, 1. The register 601 of the input timing unit 541 of each of the operation cells D2, C2, B2 and A2 in the second column has 5,
4, 3, 2 are set. As a result, all the operation cells in the first column hold the output in the high impedance state, and the output side of these operation cells becomes an empty cycle. Also, no data is input from the first common bus 531 to any of the operation cells in the second column.

In the seventh cycle, the arithmetic cell D in the first column
1, C1, B1, A1 output timing sections 543
Counter 614 is incremented to 5, 4, 3, 2. In the register 601 of the input timing unit 541 of each of the operation cells D2, C2, B2, A2 in the second column, 2,
1, 0, 5 are set. As a result, all the operation cells in the first column hold the output in the high impedance state, and the output side of these operation cells becomes an empty cycle. However, using this empty cycle, the input unit 5
02b outputs the data Z to the first common bus 531 via the first bypass bus 711. This data Z is input to the arithmetic cell B2.

As described above, according to the image processing apparatus of FIG. 16, only data transfer from the operation cells D1, C1, B1, A1 in the first column to the operation cells D2, C2, B2, A2 in the second column is required. Instead of the input unit 502b via the first bypass bus 711 to the operation cells D2, C2, B2, A2 in the second column.
Data transfer to / from is also possible. Therefore, the first and second
And 10 arithmetic cells A1, B1, C1, D1, B connected to each other by the third common buses 531, 532, 533.
2, C2, D2, C3, D3, D4 are used to perform 4-tap horizontal filter processing, while data is input from the input unit 502b to the operation cell A2 that is not used in the horizontal filter processing by using an empty cycle. Can be transferred. As a result, high use efficiency of the arithmetic array 500b can be realized, and more complicated arithmetic operations can be performed as compared with the case of FIG. 11 in which the bypass bus is not provided. It should be noted that in the present embodiment, the two cycles are idle cycles, but the present invention is not limited to this.

Further, according to the image processing apparatus of FIG. 16, it is possible to use the second to seventh bypass buses 712 to 717. In particular, since the configuration of FIG. 16 includes the bypass buses 715, 716, 717 for data feedback, there is an effect that the cyclic filter can be easily configured.

(Embodiment 8) FIG. 18 is a block diagram of an image processing apparatus according to an eighth embodiment of the present invention. The configuration of FIG. 18 is obtained by adding six bypass buses to the configuration of FIG.

Reference numeral 500c in FIG. 18 denotes an arithmetic array provided with 16 arithmetic cells (E [x, y]) 503. Between the operation cell of the first column and the operation cell of the second column, between the operation cell of the second column and the operation cell of the third column, and between the operation cell of the third column and the operation cell of the fourth column Between the first, second, and third common buses 531, 532, 533, each of which is time division multiplexed.
Is intervening.

The operation array 500c performs arithmetic operation processing on the data supplied from the input section 502c and supplies the result to the input / output section 520c. A data signal (pixel signal) from the outside is supplied to the input unit 502c via the five inputs 504. Data is individually supplied from the input unit 502c to the arithmetic cells D1, C1, B1, A1 in the first column via the data buses 505, 506, 507, 508. Fourth row arithmetic cells D4, C4, B4
Data bus 51 is connected from A4 to input / output unit 520c.
Data is individually supplied via 1, 512, 513, and 514. A first bypass bus 721 is interposed between the input unit 502c and the first common bus 531.
Via the bypass bus 721 and the first common bus 531 from the input unit 502c to the second row arithmetic cells D2, C2.
Data can be directly transferred to B2 and A2. Similarly, second and third bypass buses 722 and 723 are interposed between the input unit 502c and the second common bus 532 and between the input unit 502c and the third common bus 533, respectively. . The input / output unit 520c has four outputs 52
In addition to the function of outputting a data signal (pixel signal) to the outside via the input terminal 1, a function of inputting a data signal (pixel signal) from the outside via one input 504 is provided. Moreover, from the input / output unit 520c to the operation cell D2 of the second column.
To be able to transfer data directly to C2, B2, A2,
A fourth unit is provided between the input / output unit 520c and the first common bus 531.
By-pass bus 724 is interposed. Similarly, fifth and sixth bypass buses 725 and 726 are interposed between the input / output unit 520c and the second common bus 532 and between the input / output unit 520c and the third common bus 533, respectively. ing. The image processing apparatus shown in FIG.
The U51c and the memory 52c are further provided.

The internal structure of the arithmetic cell A2 in FIG. 18 is shown in FIG.
9 shows. In FIG. 19, 541 is an input timing unit, 542 is a processing unit, and 543 is an output timing unit. Input timing unit 541 and output timing unit 5
Reference numeral 43 has the internal structure shown in FIG. 12 or 13. The processing unit 542 of FIG. 19 includes the first latch 621.
, A second latch 622, a coefficient register 623, a multiplier 624, an adder 625, and a third latch 626. First and second latches 621,6
Reference numeral 22 holds the data supplied from the input timing unit 541 through the input 627. Of these, the second latch 622 can reset the held data to 0. The multiplier 624 uses the coefficient register 62.
3 outputs the product of the coefficient held by 3 and the data held by the first latch 621. The adder 625 outputs the sum of the product output from the multiplier 624 and the data held in the second latch 622. Third latch 62
Reference numeral 6 holds the sum output from the adder 625 and supplies the held sum to the output timing unit 543 via the output 628. Another operation cell 503 in FIG.
Also has the same internal configuration as the arithmetic cell A2 in FIG.
However, the input timing section 541 is provided for the operation cells D1, C1, B1, A1 in the first column, and the operation cells D4, C in the fourth column are provided.
It is not necessary to provide the output timing units 543 in 4, B4 and A4.

The MPU 51c shown in FIG.
When a processing switching request signal is applied via the data bus 62, the operation array 500c is configured via the data bus 62.
The coefficient is set in the coefficient register 623 in the processing unit 542 of each of the arithmetic cells 503. In addition, this MPU51
c also has a function of setting constants via the data bus 62 to the register / counter of the input timing unit 541 and the register / counter of the output timing unit 543 of each of the 16 arithmetic cells 503 forming the arithmetic array 500c. have. In the memory 52c, the program to be executed by the MPU 51c in response to the process switching request signal and the MPU 5 for setting constants in the register / counter.
A program to be executed by 1c and data to be used for setting are stored.

The input unit 502c of the input unit 502c when the image processing apparatus of FIG. 18 is operated as a device having three functions of a 2-tap horizontal filter function, a 2-tap vertical filter function, and an output synthesizing function of both filters. The internal configuration is as shown in FIG. 7 described above. In this case,
The pixel data h3 one line before the pixel data g3 supplied to the operation cell D1 is supplied to the operation cell C1 and pixel data h1 and h2 relating to three pixels arranged in the horizontal direction.
, H3 are supplied to the arithmetic cells A1, B1, C1.

FIG. 20 shows an arithmetic array 500 when the input unit 502c shown in FIG. 18 has the same internal structure as that shown in FIG.
It is operation | movement explanatory drawing of c. Operation cells A1, B1, in the first column
The coefficient registers 623 of C1 and D1 respectively store the coefficients a,
b, c, d are preset. Operation cell C2 in the second column
D2, operation cell D3 in the third column and operation cell D4 in the fourth column
The coefficient 1 is preset in each of the coefficient registers 623. Also, five arithmetic cells A1, B1, C1,
The data held in the second latch 622 of each of D1 and D4 is reset to 0 in advance.

Four pixel data h1, h2, h3, g3
From the input unit 502c to the operation cells A1, B1, C in the first column
1 and D1 respectively, the operation cell D1 is d × g3
The operation cell C1 is c × h3, and the operation cell B1 is b × h.
2 and the arithmetic cell A1 sequentially outputs a × h1 to the first common bus 5
Output to 31. In the arithmetic cell D2 in the second column, the first latch 621 sequentially receives d × g3 from the arithmetic cell D1 and the second latch 622 sequentially receives c × h3 from the arithmetic cell C1. As a result, the operation cell D2 is connected to the second common bus 532.
To c × h3 + d × g3. On the other hand, in the arithmetic cell C2 in the second column, the first latch 621 sequentially receives b × h2 from the arithmetic cell B1 and the second latch 622 sequentially receives a × h1 from the arithmetic cell A1. As a result, the operation cell C2
Outputs a × h1 + b × h2 to the second common bus 532. Here, the output data a × h1 + b of the arithmetic cell C2
* H2 is the processing result of the 2-tap horizontal filter, and the output data c * h3 + d * g3 of the operation cell D2 is the processing result of the 2-tap vertical filter.

In the arithmetic cell D3 in the third column, the first latch 621 outputs c × h3 + d × g3 from the arithmetic cell D2, and the second latch 622 axh1 + b × from the arithmetic cell C2.
Receive h2 sequentially. As a result, the operation cell D3 is
To common bus 533 of a × h1 + b × h2 + c × h3 + d
Output xg3. The arithmetic cell D4 in the fourth column outputs a × h1 + b × h2 + c × h3 + d × g3 from the arithmetic cell D3 as they are. Output data a × h1 of the processing cell D4
+ B × h2 + c × h3 + d × g3 is output via the input / output unit 520c as a result of combining the processing result of the 2-tap horizontal filter and the processing result of the 2-tap vertical filter.

As described above, according to the image processing apparatus of FIG. 18, the group consisting of the three arithmetic cells A1, B1 and C2 and the other group consisting of the three arithmetic cells C1, D1 and D2 are independently provided. By performing the operation, the 2-tap horizontal filtering process and the 2-tap vertical filtering process are executed in parallel. In addition, the two processing cells D3 and D4 execute the synthesis processing of both filter processing results.

However, in the above image processing, eight operation cells A2, B2, A3, B surrounded by broken lines in FIG.
3, C3, A4, B4, C4 are not used. These 8
The image processing device of FIG. 18 includes the first to sixth bypass buses 721 to 726 so that the individual arithmetic cells can be effectively used.
Is provided.

FIGS. 21 and 22 are timing charts for explaining the operation of the image processing apparatus of FIG. 18, which shows the second bypass bus 722 during execution of the horizontal filter processing, vertical filter processing and synthesis processing. An example of usage is shown.

In the first cycle, the arithmetic cell D in the first column
Pixel data is supplied to each of 1, C1, B1, and A1,
Arithmetic processing is executed in parallel.

In the second cycle, the operation cell D1 outputs the data d × g3 to the first common bus 531 and the data is received by the first latch 621 of the operation cell D2.

In the third cycle, the operation cell C1 outputs the data c × h3 to the first common bus 531 and the data is received by the second latch 622 of the operation cell D2. The arithmetic cell D2 that has received the two data executes arithmetic processing.

In the fourth cycle, the arithmetic cell B1 outputs the data b × h2 to the first common bus 531 and the first latch 621 of the arithmetic cell C2 receives the data. on the other hand,
The operation cell D2 transfers data c × h3 to the second common bus 532.
+ D × g3 is output and the data is received by the first latch 621 of the arithmetic cell D3.

In the fifth cycle, the arithmetic cell A1 outputs the data a × h1 to the first common bus 531 and the data is received by the second latch 622 of the arithmetic cell C2. The arithmetic cell C2 that has received the two data executes arithmetic processing. All the operation cells in the second column hold the output in the high impedance state, and the output side of these operation cells becomes an empty cycle. However, by utilizing this empty cycle, the input unit 502c causes the second bypass bus 722 to operate.
The data Z1 is output to the second common bus 532 via the. This data Z1 is stored in the first latch 6 of the arithmetic cell C3.
21.

In the sixth cycle, the arithmetic cell C2 outputs the data a × h1 + b × h2 to the second common bus 532.
The data is received by the second latch 622 of the arithmetic cell D3. The arithmetic cell D3 that has received the two data executes arithmetic processing.

In the seventh cycle, all the operation cells in the second column hold the outputs in the high impedance state, and the output side of these operation cells becomes an empty cycle. However, using this empty cycle, the input unit 502c
Sends the second data Z2 through the second bypass bus 722.
Output to the common bus 532. This data Z2 is received by the second latch 622 of the arithmetic cell C3. The arithmetic cell C3 that has received the two data executes arithmetic processing. On the other hand, the operation cell D3 outputs the data a * h1 + b * h2 + c * h3 + d * g3 to the third common bus 533,
The calculation cell D4 receives the data.

After the eighth cycle, the arithmetic cell C3 can use the third common bus 533 for outputting data.

As described above, according to the image processing apparatus of FIG. 18, it is only necessary to transfer the data from the operation cells D2, C2, B2, A2 in the second column to the operation cells D3, C3, B3, A3 in the third column. Instead of the input unit 502c via the second bypass bus 722, the arithmetic cells D3, C3, B3, A3 in the third column.
Direct data transfer to / from is also possible. Therefore, the first,
Eight arithmetic cells A1, B1, C1, D1, connected to each other by the second and third common buses 531, 532, 533
Horizontal filter processing using C2, D2, D3, D4,
While performing the vertical filtering process and the synthesizing process, the data can be transferred from the input unit 502c to the operation cell C3 that is not used in the series of processes, for example, by utilizing an empty cycle. As a result, it is possible to realize high usage efficiency of the arithmetic array 500c and not include the bypass bus.
A more complicated calculation is possible as compared with the case of 1.

Further, according to the image processing apparatus of FIG. 18, the first bypass bus 721 and the third to sixth bypass buses 723 to 726 can be used. In particular, the configuration of FIG. 18 has a bypass bus 72 for data feedback.
Since 4,725,726 are provided, there is an effect that a recursive filter can be easily configured.

(Ninth Embodiment) FIG. 23 is a block diagram of an image processing apparatus according to a ninth embodiment of the present invention. Reference numeral 500d in FIG. 23 denotes 20 arithmetic cells (E [x, y]) capable of parallel operation, which are designated by column numbers x (1 ≦ x ≦ 4) and row numbers y (1 ≦ y ≦ 5). ) 503. This operation array 500d includes a first input / output unit 5
The result obtained by performing arithmetic operation processing on the data supplied from 02d is supplied to the second input / output unit 520d, or obtained by performing arithmetic operation processing on the data supplied from the second input / output unit 520d. The obtained result is supplied to the first input / output unit 502d. Similar to the case of FIG. 10, four operation cells E [1, y] (2 ≦ y ≦
5) is A1, B1, C1 and D1, three operation cells E [2, y] (3 ≦ y ≦ 5) in the second column are B2, C2 and D2, and two in the third column Operation cell E [3, y]
(4 ≦ y ≦ 5) is named C3 and D3, and the operation cell E [4,5] in the fourth column is named D4. Also, the fourth
Four operation cells E [4, y] in the column (4 ≧ y ≧ 1)
, P1, Q1, R1 and S1, and three operation cells E [3, y] (3 ≧ y ≧ 1) in the third column to Q2, R2 and S1.
2, two operation cells E [2, y] of the second column (2 ≧
y ≧ 1) is R3 and S3, the operation cell E in the first column
Name [1,1] as S4.

The data signal (pixel signal) from the outside is 4
One input 504 is supplied to the first input / output unit 502d, and another four inputs 504 are supplied to the second input / output unit 520d. From the first input / output unit 502d to the four arithmetic cells D1, C1, B1, A1 in the first column via the data buses 505, 506, 507, 508, respectively.
The data bus 51 is connected from the second input / output unit 520d to the four operation cells P1, Q1, R1, and S1 in the fourth column.
Data is individually supplied via 2, 513, 514, and 515. First row operation cells S4, A1, B1, C1,
D1 and operation cells S3, R3, B2, C2, D2 in the second column
And a first common bus 531 of time division multiplexing is interposed between and, and six operation cells A1, B1, C1, D1, R
4 arithmetic cells B from arbitrary arithmetic cells of S3 and S3
Data can be transferred to any of the operation cells 2, 2, C 2, D 2, and S 4. Also, the operation cell S in the second column
3, R3, B2, C2, D2 and operation cells S2 in the third column
A second common bus 532, which is time division multiplexed, is interposed between R2, Q2, C3 and D3, and six arithmetic cells B2 and C are provided.
Data can be transferred from any operation cell of 2, 2, D2, Q2, R2, S2 to any operation cell of the four operation cells C3, D3, R3, S3. Furthermore,
Operation cells S2, R2, Q2, C3, D3 in the third column and a fourth operation cell
A time-division-multiplexed third common bus 533 is interposed between the column arithmetic cells S1, R1, Q1, P1, D4, and the six arithmetic cells C3, D3, P1, Q1, R1, S1 Four operation cells D4, Q2, R from any of the operation cells
Data can be transferred to any operation cell of S2 and S2. Data is supplied from the arithmetic cell D4 in the fourth column to the second input / output unit 520d via the data bus 511, and the second input / output unit 520d outputs one output 52.
A data signal (pixel signal) is output to the outside via the 1.
On the other hand, data is supplied from the operation cell S4 in the first column to the first input / output unit 502d via the data bus 516, and the first input / output unit 502d outputs data to the outside via one output 521. A signal (pixel signal) is output.

As described above, the arithmetic array 500d of the image processing apparatus of FIG. 23 has a structure in which the blank portion of the arithmetic array 500a of FIG. 15 is filled with the same arithmetic array. Therefore, when mounting on an LSI, the chip area can be used more effectively than in the case of FIG. In addition,
The image processing apparatus of FIG. 23 further includes an MPU 51d and a memory 52d for setting a coefficient register incorporated in each arithmetic cell 503.

According to the image processing apparatus of FIG. 23, ten arithmetic cells A1, B1, C1, D1, B connected to each other via the first to third common buses 531, 532, 533 are connected.
2, C2, D2, C3, D3, D4 and ten other operation cells P1, Q1, R1, S which are also connected to each other via the first to third common buses 531, 532, 533.
1, Q2, R2, S2, R3, S3, and S4 are operated independently of each other to perform horizontal filtering,
Vertical filtering or the like can be performed. Also,
A cyclic filter can be easily configured by externally connecting the 20 arithmetic cells 503 so as to form a loop. In addition, two operation cells (for example,
It is also possible to construct a recursive filter with B2 and R3). The bypass bus shown in FIGS. 16 and 18 may be added to the configuration of FIG.

As described above, according to each of the above-described embodiments, it is possible to achieve the parallel operation of the plurality of product-sum operation cells forming the operation array for programmable image processing. Moreover, it is possible to execute parallel processing with a small bus configuration, and the effect is great.

The MPU in each embodiment can be incorporated in the arithmetic array. For example, the MPU 11 in FIG.
Can also receive pixel data from the input unit 102 and perform arithmetic logic operation processing on the received pixel data. Further, the MPU 11 has 16 arithmetic cells 103.
It is also possible to receive data from any of the above and perform arithmetic logic operation processing on the received data.
The result of the processing by the MPU 11 is one of the calculation cells 1
03 or the output unit 120.

[0098]

As described above, according to the first signal processing apparatus of the present invention, a plurality of arithmetic cells capable of operating in parallel are two-dimensionally arranged in a pyramid shape and each has a tree structure. Since the configuration in which the layers are connected by the data bus is adopted, it is possible to realize the signal processing device suitable for the convergence type processing capable of executing the parallel processing with a small bus configuration.

Further, according to the second signal processing device of the present invention, a plurality of arithmetic cells capable of operating in parallel are two-dimensionally arranged in a pyramid shape, and an individual common bus is provided between layers. Since this is adopted, it is possible to realize a signal processing device suitable for convergent processing capable of executing parallel processing with a small bus configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of a signal processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of an input unit in FIG.

FIG. 3 is a block diagram showing an internal configuration of an arithmetic cell in FIG.

FIG. 4 is an operation explanatory diagram of the arithmetic array in FIG.

FIG. 5 is a block diagram of a signal processing device according to a second embodiment of the present invention.

FIG. 6 is a block diagram of a signal processing device according to a third embodiment of the present invention.

FIG. 7 is a block diagram showing an internal configuration of an input unit in FIG.

FIG. 8 is a block diagram showing an internal configuration of a calculation cell in FIG.

9 is an explanatory diagram of the operation of the arithmetic array in FIG.

FIG. 10 is a block diagram of a signal processing device according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram of a signal processing device according to a fifth embodiment of the present invention.

FIG. 12 is a block diagram showing an example of the internal configuration of a calculation cell in FIG.

13 is a block diagram showing another internal configuration example of the arithmetic cell in FIG.

14 is a timing chart for explaining the operation of the signal processing device of FIG.

FIG. 15 is a block diagram of a signal processing device according to a sixth embodiment of the present invention.

FIG. 16 is a block diagram of a signal processing device according to a seventh embodiment of the present invention.

17 is a timing diagram for explaining the operation of the signal processing device of FIG.

FIG. 18 is a block diagram of a signal processing device according to an eighth embodiment of the present invention.

FIG. 19 is a block diagram showing an internal configuration of a calculation cell in FIG.

20 is an operation explanatory diagram of the signal processing device of FIG. 18;

FIG. 21 is a timing diagram for explaining the operation of the signal processing device of FIG.

22 is another timing diagram for explaining the operation of the signal processing device of FIG.

FIG. 23 is a block diagram of a signal processing device according to a ninth embodiment of the present invention.

[Explanation of symbols]

11, 11a to 11c MPU 12, 12a to 12c memory 21 control input 22 data bus 51, 51a to 51d MPU 52, 52a to 52d memory 61 control input 62 data bus 100, 100a to 100c arithmetic array (arithmetic means) 102, 102a 102c input unit or input / output unit (first interface unit) 103, 103a to 103c operation cell 104 input 105 to 116, 119 data bus 120, 120a to 120c output unit or input / output unit (second interface unit) 121 Output 131, 137 Coefficient register 133 Multiplier 135 Adder 136 Latch 138 Selector 201-203 Latch (data holding means) 301 Line memory (data holding means) 301, 303 Latch (data holding means) 500, 5 00a to 500d Arithmetic array (arithmetic means) 502, 502a to 502d Input section or input / output section (first interface means) 503 Arithmetic cell 504 Input 505 to 508, 511 to 516 Data bus 520, 520a to 520d Output section or input Output unit (second interface unit) 521 Output 531 to 533 Common bus 541 Input timing unit 542 Processing unit 543 Output timing unit 601,611 Register 602,612 Match detection circuit 604,614 Counter 621,622,626 Latch 623 Coefficient register 624 multiplier 625 adder 711-717, 721-726 bypass bus

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location G06F 15/66 K (72) Inventor Tamotsu Nishiyama 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. Within

Claims (20)

[Claims] 1. Arithmetic means for applying arithmetic operation processing to data, first interface means for inputting a data signal from the outside to supply data to the arithmetic means, and arithmetic operation processing from the arithmetic means. Second interface means for receiving the supplied data and outputting a data signal to the outside, wherein the arithmetic means is 1 ≦ x ≦ M and x ≦ y for an integer M of 2 or more. An array of a plurality of operation cells E [x, y] capable of parallel operation specified by two subscripts x and y satisfying ≦ M, and an operation cell E [1, y] (1 ≦ y ≦ M ) Is supplied from the first interface means, and the input data of the operation cell E [x, y] (2 ≦ x ≦ M and x ≦ y ≦ M) is the operation cell E [x-1, y]. And operation cell E
The signal processing device is characterized in that the output data of the arithmetic cell E [M, M] is supplied from [x-1, y-1] to the second interface means. 2. The signal processing device according to claim 1, wherein the arithmetic means is capable of parallel operation designated by two subscripts x and y satisfying 2 ≦ x ≦ M and 1 ≦ y ≦ x−1. Further comprising an arithmetic cell E [x, y], input data of the arithmetic cell E [x, 1] (2 ≦ x ≦ M) is supplied from the arithmetic cell E [x−1, 1], [X, y] (3 ≦ x ≦ M and 2 ≦ y ≦ x−
The input data of 1) is supplied from the operation cell E [x-1, y] and the operation cell E [x-1, y-1], and the operation cell E [M, y] (1≤y≤M-1) Output data is supplied to the second interface means. 3. The signal processing device according to claim 2, wherein the input data of the operation cell E [x, y] (2 ≦ x ≦ M and 1 ≦ y ≦ M−1) in the operation means is the operation cell E. [X-
1, y + 1] is further supplied from the signal processing device. 4. The signal processing apparatus according to claim 1, wherein the first interface unit has M-1 data holding units that are cascaded with each other for holding data. Signal processing device. 5. The signal processing device according to claim 1, wherein the arithmetic cells E [x, y] (1 ≦ x ≦ M and x ≦ y ≦ M) in the arithmetic means are multiplications for sum-of-products arithmetic. And a signal adder having an adder. 6. The signal processing device according to claim 5, wherein the operation cell E [x, y] (1 ≦ x ≦ M and x ≦ y ≦ M) in the operation means is one input of the multiplier. A signal processing apparatus further comprising a rewritable coefficient register for supplying a coefficient to the. 7. Arithmetic means for applying arithmetic operation processing to the data, and data for supplying data to the arithmetic means by inputting a data signal from the outside, respectively, and for processing the arithmetically processed data from the arithmetic means. First and second interface means for receiving and supplying a data signal to the outside are provided, and the computing means sets 1 ≦ x ≦ M and 1 ≦ y ≦ M + 1 for an integer M of 2 or more. It has an array of a plurality of operation cells E [x, y] capable of parallel operation designated by two subscripts x and y to be satisfied, and inputs of the operation cells E [1, y] (2 ≦ y ≦ M + 1) The data is supplied from the first interface means, and the operation cell E [x, y] (2 ≦ x ≦ M and x + 1 ≦ y ≦ M
+1) input data is supplied from the operation cell E [x-1, y] and the operation cell E [x-1, y-1], and the output data of the operation cell E [M, M + 1] is the second interface. The input data of the operation cell E [M, y] (1 ≦ y ≦ M) is supplied from the second interface means, and the operation cell E [x, y] (1 ≦ x ≦ M−1) And 1 ≦ y ≦
x) input data is supplied from the operation cell E [x + 1, y] and operation cell E [x + 1, y + 1], and output data of the operation cell E [1, 1] is supplied to the first interface means. A signal processing device characterized by: 8. Arithmetic means for performing arithmetic operation processing on data, first interface means for inputting a data signal from the outside to supply data to the arithmetic means, and arithmetic operation processing from the arithmetic means Second interface means for receiving the supplied data and outputting a data signal to the outside, wherein the arithmetic means is 1 ≦ x ≦ M and x ≦ y for an integer M of 2 or more. An array of a plurality of operation cells E [x, y] capable of parallel operation specified by two subscripts x and y satisfying ≦ M, and an operation for each integer k of 1 or more and M-1 or less The cell E [k, y] (k ≦ y ≦ M) and the operation cell E [k + 1,
y] (k + 1 ≦ y ≦ M) and a time division multiplexed common bus B [k], and the input data of the operation cell E [1, y] (1 ≦ y ≦ M) is The input data of the operation cell E [k + 1, y] (k + 1 ≦ y ≦ M) supplied from the first interface means is transferred from the operation cell E [k, y] (k ≦ y ≦ M) to the common bus B [k]. The signal processing device is characterized in that the output data of the operation cell E [M, M] is supplied to the second interface means. 9. The signal processing device according to claim 8, wherein the arithmetic means is capable of parallel operation designated by two subscripts x and y satisfying 2 ≦ x ≦ M and 1 ≦ y ≦ x−1. Further, the operation cell E [x, y] is provided, and the input data of the operation cell E [k + 1, y] (1 ≦ y ≦ M) is common from the operation cell E [k, y] (1 ≦ y ≦ M). Bus B
The signal processing apparatus is characterized in that the output data of the operation cell E [M, y] (1 ≦ y ≦ M−1) supplied via [k] is supplied to the second interface means. 10. The signal processing apparatus according to claim 8, wherein the first interface unit has M-1 data holding units connected in series for holding data. Signal processing device. 11. The signal processing device according to claim 8, wherein the arithmetic cell E [k + 1, y] (k + 1 ≦ in the arithmetic means.
y ≦ M) has a rewritable register and inputs data from the common bus B [k] when a value set in the register and a value given in advance match. Signal processing device. 12. The signal processing device according to claim 8, wherein the arithmetic cell E [k + 1, y] (k + 1 ≦ in the arithmetic unit.
y ≦ M) has a counter that is sequentially updated according to the clock, and inputs data from the common bus B [k] when the held value of the counter and the value given in advance match. Signal processing device. 13. The signal processing device according to claim 8, wherein an arithmetic cell E [k, y] (k ≦ y ≦ M) in the arithmetic means.
Is a rewritable register, and outputs data to a common bus B [k] when a value set in the register and a value given in advance match. 14. The signal processing device according to claim 8, wherein an arithmetic cell E [k, y] (k ≦ y ≦ M) in the arithmetic means.
Has a counter that is updated sequentially according to the clock,
A signal processing device, which outputs data to a common bus B [k] when a held value of the counter matches a value given in advance. 15. The signal processing device according to claim 8, wherein the operation cell E [x, y] (1 ≦ x ≦ M and x ≦ y ≦ M) in the operation means is a multiplication for a product-sum operation. And a signal adder having an adder. 16. The signal processing device according to claim 15, wherein the arithmetic cell E [x, y] (1 ≦ x ≦ M and x ≦ y ≦ M) in the arithmetic means is one input of the multiplier. A signal processing apparatus further comprising a rewritable coefficient register for supplying a coefficient to the. 17. The signal processing device according to claim 8, further comprising a bypass bus interposed between the first interface unit and the common bus B [k] (1 ≦ k ≦ M−1) of the arithmetic unit. A signal processing device further comprising: 18. The signal processing apparatus according to claim 8, further comprising a bypass bus interposed between the common bus B [k] (1 ≦ k ≦ M−1) of the arithmetic means and the second interface means. A signal processing device further comprising: 19. The signal processing device according to claim 8, wherein the plurality of common buses B [k] (M ≧ 3 and 1 of the arithmetic means.
The signal processing device further comprising a bypass bus interposed between at least two of ≦ k ≦ M-1). 20. Arithmetic means for performing arithmetic operation processing on the data, and data for supplying data to the arithmetic means by inputting a data signal from the outside, respectively, and for processing the arithmetically operated data from the arithmetic means. It is provided with first and second interface means for receiving the supply and outputting the data signal to the outside, wherein the arithmetic means is 1 ≦ x ≦ M and 1 ≦ y ≦ M + 1 for an integer M of 2 or more.
An array of a plurality of operation cells E [x, y] capable of parallel operation designated by two subscripts x and y satisfying the above condition, and an operation cell E for each integer k of 1 or more and M-1 or less. [K, y] (1 ≦ y ≦ M + 1) and the operation cell E [k +
, Y] (1 ≦ y ≦ M + 1) and a time division multiplexed common bus B [k], and input data of the operation cell E [1, y] (2 ≦ y ≦ M + 1) Is supplied from the first interface means, and the input data of the operation cell E [k + 1, y] (k + 2 ≦ y ≦ M + 1) is the operation cell E [k, y] (k + 1 ≦ y ≦ M +
1) and the operation cell E [k + 1, y] (1 ≦ y ≦ k + 1)
From the operation cell E [M, M + 1] to the second interface means, and the operation cell E [M, y] (1 ≦ y ≦ M) Input data is supplied from the second interface means, and the input data of the operation cell E [k, y] (1 ≦ y ≦ k) is the operation cell E [k + 1, y] (1 ≦ y ≦ k + 1) and the operation From cell E [k, y] (k + 1 ≦ y ≦ M + 1) to common bus B
The signal processing device is characterized in that the output data of the operation cell E [1,1] is supplied to the first interface means via the [k].