JPH1115801A - Data arithmetic unit, method and transmission medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily execute the processing of a data arithmetic unit. SOLUTION: A selector 60A is arranged in a 1st processor element(PE) out of N PEs 15 and a selector 60B is arranged in an N-th PE 15. The data of a data memory 12 in the 1st PE 15 and values '0' and '1' are supplied to the selector 60A and the data of a data memory 12 in the N-th PE 15 and the values '0', '1' are supplied to the selector 60B, so that a program control circuit 17 can select and output the data of the selectors 60A, 60B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device and method, and a transmission medium, and more particularly to a data processing device and method suitable for performing SIMD parallel control.
And a transmission medium.

[0002]

2. Description of the Related Art As a conventional data processing device, Japanese Patent Application No.
No. 07-230743 and IEEE (The Institute
of Electrical and Electronics Engineers, Inc.) 19
90 CUSTOM INTEGRATED CIRCUITS CONFERENCE, P17. 3.1
There is a processor called SVP (Serial Video Processsor). The SVP is a processor that digitally processes a video signal in real time, and includes 1024 processors in one chip. And this SVP
Is a SIMD (Single Instruction stream / Multiple Datas
(tream) structure, the pixel data of the horizontal scanning line can be processed in parallel. Here, SIMD is one of the data processing methods of a computer, and performs the same job simultaneously, although the data is different.

FIG. 12 shows a configuration example of such a conventional data processing device. This data processing device is the above-described SIMD control parallel processor. In this data processing device, the input serial access memory 11, the data memory 12, the arithmetic circuit 13, and the output serial access memory 14 form a processor element group parallelized in a linear array type. These processor elements 15 are controlled in conjunction with each other according to one program of the program control circuit 17. The program memory 18 stores programs for controlling various circuits, and supplies the programs to the program control circuit 17.

[0004] The program control circuit 17 has a built-in sequence control circuit for controlling the address of the program memory 18, updates the address of the program memory 18 in accordance with the program stored in the program memory 17, and controls various control signals. To control various circuits.

The input serial access memory 11,
Data memory 12, output serial access memory 14
Is mainly composed of memory. 12, it is assumed that row address decoders for these memories are included in the program control circuit 17. The data memory 12 is a memory having three ports of two read and one write. In this case, a bit line for writing or reading data runs vertically in this case. The arithmetic circuit 13 is connected.

[0006] The parallelized processor element 15
(For a single element) corresponds to the hatched portion in the figure, and a plurality of processor elements 15 are arranged in the horizontal direction in the figure. That is, only the hatched portions in the figure have components corresponding to one processor. The element operation circuit 16 is a circuit for a single element of the operation circuit 13.

FIG. 13 shows a configuration example of the data memory 12 and the element operation circuit 16 for a single element. At the time of calculation in each processor element, the calculation may be performed using data allocated to the neighboring processor element 15 in addition to the data allocated to itself. Therefore, the data memory 12 is provided with the selector 70 and the selector 71, and the data supplied to the data memory of the adjacent processor element 15 can be appropriately read under the control of the program control circuit 17. ing.

For example, the selector 70 is supplied with the data of the data memory 12 shown in the figure and the data of the data memory 12 of the processor element 15 (not shown) adjacent to the left and right sides. One of these three inputs is selected under the control of the program control circuit 17 and supplied to the selector 80 and the selector 81. The same applies to the selector 71.

However, among the processor elements 15, the leftmost and rightmost processor elements 15 have the adjacent data memory 12 only on one side thereof.
At the time of calculation in the data memory 12 adjacent to the left side.
Is performed, the leftmost processor element 15 cannot read data from the left side. Therefore, it is conceivable that 0 or 1 is fixed as input data in that case.

The data from the selector 70 is transmitted to the selector 8
The signal is supplied to the register 84 via the “0” and the register 85 via the selector 81. Selector 7
1 from the register 86 via the selector 82.
Supplied to The selector 80 selects one data from a preset value 1 or 0, data from the data memory 12, and data fed back from the register 84, and supplies the selected data to the register 84. . The register 87 holds carry-over data supplied from the full adder 91 via the selector 83.

The AND circuit 88 calculates the AND of the data held in the registers 84 and 85. The exclusive OR circuit 89 performs an exclusive OR operation on the output of the AND circuit 88 and the data supplied from the program control circuit 17, and supplies the operation result to the full adder 91. The full adder 91 is further supplied with data held in the registers 86 and 87. The full adder 91 performs addition of these three inputs, and generates a sum (su) generated as a result of the operation.
m) and carryover are output to the selector 92. Of these, carryover is also supplied to the selector 83.

The selector 90 selects the data supplied from the exclusive OR circuit 89 and the register 86 according to the value of the register 84 and outputs the data to the selector 92. The selector 92 selects one of a total of three inputs, the input of the selector 90 and the two inputs from the full adder 91, according to the control signal of the program control circuit 17, and outputs the selected input to the data memory 12. . Selector 93
Is controlled by a signal from the program control circuit 17, and selects the values of the register 85 and the AND circuit 88.

For example, the selector 93 is controlled by a signal from the program control circuit 17, and data supplied from the data memory 12 and held in the register 85 is input to the full adder 91 via the exclusive OR circuit 89. You. The full adder 91 receives data input from the exclusive OR circuit 89 (data supplied from the register 85), data supplied from the data memory 12 and stored in the register 86, and the previous data stored in the register 87. The carry-over data generated during the operation is added, and the result of the addition and the newly generated carry-over data are output to the selector 92. The carryover is also supplied to the register 87 and held.

The program control circuit 17 can control the selector 92 to select the carry-over output from the full adder 91 and output it to the data memory 12. Alternatively, one of the data supplied from the exclusive OR circuit 89 or the register 86 is selected by the selector 90, and the selected data is further selected by the selector 92.
It can be supplied to the data memory 12.

The program control circuit 17 includes a logical product circuit 8
When it is desired to invert the logic of the data output from 8 and supply the inverted data to the full adder 91, a logical 1 is output to one input of the exclusive OR circuit 89. In this way, the exclusive OR circuit 89 outputs a logical 0 when the logical 1 is output from the logical AND circuit 88, and outputs a logical 1 when the logical 0 is input from the logical AND circuit 88. I can do it.

In order to calculate the logical product of the newly input data and the previous data, the program control circuit 17 causes the selector 80 to select the data held in the register 84 again. By doing so, the next data is held in the register 85, so that the logical product circuit 88
, The current data and the immediately preceding data are input, and the logical product thereof is calculated. Register 84 by selector 80
By repeating the selection of the output, the calculation of the new input data and the past input data becomes possible.

When the operation assigned to one horizontal scanning period is completed as described above, the data calculated during the horizontal scanning period is transferred to the output serial access memory 14 during the horizontal scanning period.

As described above, during one horizontal scanning period, the transfer of the input data stored in the input serial access memory 11 to the data memory 12, the calculation by the arithmetic circuit 13, and the data transfer to the output serial access memory 14 Is executed according to a SIMD control program in units of bits. This process is sequentially repeated in units of the horizontal scanning period.

The output serial access memory 14
Are output from the output serial access memory 14 in the next horizontal scanning retrace period.

As described above, the input processing for taking the input data into the input serial access memory 11, the transfer of the input data accumulated in the input serial access memory 11 to the data memory 12 by the program control circuit 17, and the operation by the arithmetic circuit 13 Calculation and calculation processing of transfer of output data to the output serial access memory 14, and
Three processes of output processing for reading output data from the output serial access memory 14 are performed on each input data of each processor element 15. Note that these three processes are executed as pipeline processes in units of one horizontal scanning period of the image signal. That is, in the data processing device, three processes are collectively performed on the assigned pixel data for one horizontal scanning period.

In such a data arithmetic device, when performing a thinning filter operation, an interpolation filter operation, or the like, a different operation for each pixel data or an operation using different coefficients is required. For this reason, each processor element 15 is assigned a number as information indicating its position, and a flag for allowing a predetermined operation and a predetermined coefficient to be selected is generated. Each time, a predetermined calculation is performed using the flag. Such an operation is enabled by defining the program in the program memory 18 as such and controlling the program control circuit 17 based on the program.

[0022]

However, under SIMD control, it is difficult to assign a number to each processor element 15 and generate a flag.

Also, as described above, in the transfer of data between adjacent processor elements 15, the processor elements 15 at the left and right ends cannot obtain data from outside. Therefore, if 0 or 1 is fixed as input data in this case, the DC gains of the processor elements at both ends fluctuate. Therefore, processing such as repeatedly inputting the data of the processor elements 15 at both ends can be considered. However, there is a problem that the processing is required for that and the number of steps of the program is increased.

The present invention has been made in view of such circumstances, and has as its object to facilitate the processing of a data processing device.

[0025]

According to a first aspect of the present invention, there is provided a data processing apparatus comprising: a control unit for controlling an operation of each processor element; and a first or Nth processor among the N processor elements. The data of the element storage means and the numerical value 0 and the numerical value 1 are supplied, and there is provided a selection means for selecting one of them in accordance with the control by the control means. When reading data from the storage means, the first or Nth processor element is controlled to read the data selected by the selection means.

[0026] According to a third aspect of the present invention, in the data operation method, a control step of controlling an operation of each processor element;
Of the N processor elements, the data of the storage means of the first or Nth processor element, the numerical value 0 and the numerical value 1 are input, and one of them is selected according to the control in the control step. And selecting a first or Nth processor element to read the data selected in the selecting step when each processor element reads data from storage means of an adjacent processor element. Features.

According to a fourth aspect of the present invention, there is provided the transmission medium, wherein the control step controls the operation of each processor element, and the data stored in the storage means of the first or Nth processor element among the N processor elements. , A numerical value 0 and a numerical value 1 are inputted, and a computer program having a selection step of selecting one of them in response to the control in the control step is transmitted.

[0028] In the data operation device according to the first aspect, the data operation method according to the third aspect, and the transmission medium according to the fourth aspect, the first or Nth one of the N processor elements is provided. The data of the storage means of the third processor element and one of the numerical values 0 and 1 are selected. Then, when each processor element reads data stored in an adjacent processor element, control is performed so that the first or Nth processor element reads the selected data.
For example, when each processor element reads data from the storage means of the processor element on the left, the first
The third processor element can read the selected value 0.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below. In order to clarify the correspondence between each means of the invention described in the claims and the following embodiments, each means is described. When the features of the present invention are described by adding the corresponding embodiment (however, an example) in parentheses after the parentheses, the result is as follows. However, of course, this description does not mean that each means is limited to those described.

According to the first aspect of the present invention, there is provided a data processing device comprising: a control unit (for example, the program control circuit 17 in FIG. 1) for controlling the operation of each processor element; The data of the storage means of the N-th processor element, the numerical value 0 and the numerical value 1 are inputted,
Selecting means (for example, selectors 60A and 60B in FIG. 1) for selecting any one of them, and the control means, when each processor element reads data from the storage means of the adjacent processor element, selects the first or second data. N
The processor element is controlled to read out the data selected by the selection means.

FIG. 1 is a block diagram showing an example of the configuration of a data processing device according to the present invention. In the drawing, portions corresponding to those shown in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. I do. In this configuration example, the data operation device includes:
It is composed of N processor elements 15. Assuming that the leftmost processor element 15 is the first processor element and the rightmost processor element 15 is the Nth processor, the selector 60A is provided for the first processor element 15 and the selector 60B is the Nth processor element. It is provided for the processor element 15.
The detailed description of the selector 60A and the selector 60B will be described later with reference to FIGS. Other configurations are the same as those in FIG.

Next, the operation of the data processing device shown in FIG. 1 will be described. The input data (image data for one pixel)
It is supplied to the input serial access memory 11 by a control signal from the program control circuit 17. Since this data sequentially moves from the first processor element 15 to the Nth processor element 15, the input data is the first processor element 1
5 from the cell of the input serial access memory 11
The input is sequentially supplied to the cells of the input serial access memory 11 of the processor element 15. Such an input operation is repeated every horizontal scanning period.

Each time data for one horizontal scanning period of an image signal is accumulated in the input serial access memory 11 in this manner, the program control circuit 17 operates according to the program stored in the program memory 18. 11, the data memory 12, the arithmetic circuit 13, and the output serial access memory 14 are subjected to SIMD control as follows to execute processing. Since this processing is SIMD control, the following operations are similarly executed in parallel in all processor elements 15.

The input data for one horizontal scanning period stored in the input serial access memory 11 is transferred from the input serial access memory 11 to the data memory 12 as needed in the next horizontal scanning retrace period. The program control circuit 17 supplies the data held in each data memory 12 to the element operation circuit 16 of each processor element 15 according to the program. An arithmetic operation or a logical operation is performed on the data. Then, the operation result is written to a predetermined address of the data memory 12.

FIG. 2 shows a configuration example of the data memories 12-1 to 12-N and the element operation circuits 16-1 to 16-N of the N processor elements 15. The selectors 70-1 to 70-N and the selectors 71-1 to 71-N provided between the data memories 12-1 to 12-N and the respective element operation circuits 16-1 to 16-N include: The data of the data memory 12 of the three processor elements 15 including the one corresponding to itself and the one adjacent to the right and left is input, and the data is controlled by the program control circuit 17 in FIG. One is selected and supplied to each element operation circuit 16.

Here, the N processor elements 15
Among them, the first processor element 15 and the N-th processor element 15 have adjacent processor elements 15 on only one side. Therefore, as an input from the other, the selector 60A is connected to the selector 70-1 and the selector 71-1 of the first processor element 15, and the Nth
The selector 60B is connected to the selector 70-N and the selector 71-N of the processor element 15. By doing so, for example, when each processor element 15 is controlled to read data from the data memory 12 of the processor element 15 adjacent on the left side, the first processor element 15 Data can be read from 60A.

A numerical value 0, a numerical value 1, and data of the data memory 12-1 are input to the selector 60A.
One of them is selected under the control of the program control circuit 17 of FIG.
1-1. A numerical value 0, a numerical value 1, and data of the data memory 12-N are input to the selector 60B, and are controlled in the same manner as the selector 60A. For example,
When the first processor element 15 and the N-th processor element 15 repeatedly perform the operation by using the same data, the same data is re-input to the selectors 60A and 60B and used for the next operation. Can be.

FIG. 3 shows the data memory 12-1 and the element operation circuit 16-1 of the first processor element 15.
The same reference numerals are given to portions corresponding to the case shown in FIG. 13, and the description thereof will be omitted as appropriate. In this configuration example, the selector 70-1 and the selector 71-1 have data of the data memory 12-1 and
The data of the processor element 15 (not shown) adjacent to the right side and the data of the selector 60A are input. The data selected by the selector 70-1 and the selector 71-1 is supplied to the element operation circuit 16-1 and the element operation circuit 1 of the other processor element 15
The calculation is performed by the control common to that of FIG.

When different processing is performed in each processor element 15, all processing that may be selected is performed in advance for all processor elements 1.
5 is executed, the respective results are stored in the data memory 12 of each processor element 15, and a flag generated in advance is stored in the register 84, and stored in the data memory 12 of each processor element 15 by this flag. A predetermined result is selected from the calculated results and output.

Further, even when the calculation is performed using a different coefficient for each processor element 15, similarly, a coefficient that may be selected is generated, stored in the data memory 12, and set by a flag. An operation is performed using the selected coefficient. When these flags and coefficients are generated and supplied externally, they may be taken from the input serial access memory 11, stored in the data memory 12, read out as appropriate, and used. In the data operation device of the present invention, the program control circuit 17 controls the data operation device based on the program in the program memory 18 to generate flags and coefficients.

FIG. 4 shows that each processor element 15 has
10 is a flowchart illustrating a process when a flag for distinguishing the first processor element 15 is given.
First, in step S101, the program control circuit 17 sends the data memory 1 of each processor element 15
Second, a work address is secured. Then, step S
At 102, the program control circuit 17 stores the numerical value 1 in the working address of the data memory 12 of each processor element 15.

In step S103, when each processor element 15 is controlled to read a numerical value (data) from the data memory 12 of the processor element 15 on the left side, the program control circuit 17 determines that the selector 60A has a numerical value of 0. And select to output. Then, in step S104, the program control circuit 17 controls each processor element 15 to read the numerical value stored in the work address of the data memory 12 of the processor element 15 on the left. At this time, in response to the setting in step S103, the first processor element 15 selects the selector 60A
Read the value 0 from.

In step S105, the program control circuit 17 stores the numerical value read by each processor element 15 as a flag in the working address of the data memory 12. As a result, only the first processor element 15 is given the numerical value 0 as a flag, and the other processor elements 15 are given the numerical value 1 as a flag.

FIG. 5 is a flowchart for explaining a process in which a flag for distinguishing an arbitrary processor element 15 is given to each processor element 15 by applying the process shown in FIG. Note that this process
It is assumed that the processing is continued from the processing in FIG. Step S
In 201, the program control circuit 17 inverts the numerical value stored in the working address of the data memory 12 of each processor element 15.

Next, in step S202, the program control circuit 17 determines that each processor element 15
Control is performed so that the numerical value stored in the work address of the data memory 12 of the processor element 15 on the left side is read. Subsequently, in step S203, the program control circuit 17 stores the numerical value read by each processor element 15 in the working address of the data memory 12.

In step S204, the program control circuit 17 determines whether or not the processing in steps S202 and S203 has been performed L times. If the program control circuit 17 determines that the process has not been performed L times, the process returns to step S202, and if it determines that the process has been performed L times, the process proceeds to step S205.

In step S205, the program control circuit 17 sets a numerical value finally stored in the data memory 12 of each processor element 15 as a flag. By such control, only the (L + 1) -th processor element 15 obtains a numerical value 1 as a flag,
The other processor elements 15 obtain the numerical value 0 as the flag. That is, when it is desired to give the 50th processor element 15 a numerical value of 1 as a flag, it is sufficient to set L = 49 in this processing.

FIGS. 6 and 7 are flowcharts for explaining other processing when a flag for distinguishing an arbitrary processor element 15 is given to each processor element 15. First, in step S301, the program control circuit 17 secures a working address in the data memory 12 of each processor element 15. Next, in step S302, the program control circuit 1
7 is a data memory 12 of each processor element 15
The numerical value 1 is stored in the work address.

In step S303, when each processor element 15 is controlled to read a numerical value from the data memory 12 of the processor element 15 on the left, the program control circuit 17 selects the selector 60A.
Is set to select and output the numerical value 0. Then, in step S304, the program control circuit 17
Controls each processor element 15 to read a numerical value from the working address in the data memory 12 of the processor element 15 on the left side.

In step S 305, the program control circuit 17 stores the numerical value read by each processor element 15 in the work address of the data memory 12. Subsequently, proceeding to step S306, when the program control circuit 17 controls each processor element 15 to read a numerical value from the data memory 12 of the processor element 15 on the left side, the selector 60A
Set to select and output the numerical value 1.

Then, in step S304, the program control circuit 17
Is the data memory 1 of the processor element 15 on the left.
Control is performed so that the numerical value stored in the work address 2 is read. At this time, the first processor element 15 reads the numerical value 1 from the selector 60A.

In step S 305, the program control circuit 17 stores the numerical value read by each processor element 15 in the working address of the data memory 12. Next, proceeding to step S306, the program control circuit 17 causes the selector 60A to select the numerical value 1 when each processor element 15 is controlled to read a numerical value from the data memory 12 of the processor element 15 on the left. Set to output.

In step S307, the program control circuit 17 controls each processor element 15 to read the numerical value stored in the working address of the data memory 12 of the processor element 15 on the left. Then, in step S308, the program control circuit 17 stores the numerical value read by each processor element 15 in the work address.

In step S309, the program control circuit 17 determines whether or not the processing in steps S307 and S308 has been performed L times. When the program control circuit 17 determines that the process has not been performed L times, the process returns to step S307, and when it determines that the process has been performed L times, the process proceeds to step S310.

In step S310, the program control circuit 17 sets the numerical value finally stored in the work address of the data memory 12 of each processor element 15 as a flag. As a result, a numerical value 0 is generated as a flag in an arbitrary processor element 15 and a numerical value 1 can be given to another processor element 15 as a flag.

FIGS. 8 and 9 show each processor element 1.
5 is a flowchart for explaining still another process when a flag for discriminating an arbitrary processor element 15 is given to 5. First, in step S401, the program control circuit 17 secures a working address in the data memory 12 of each processor element 15. Subsequently, in step S402, the program control circuit 17
Stores a numerical value 1 in a work address of the data memory 12 of each processor element 15.

In step S403, when each processor element 15 is controlled to read a numerical value from the data memory 12 of the processor element 15 on the left, the program control circuit 17 selects the selector 60A.
Is set to select and output the numerical value 0.

In step S404, the program control circuit 17 controls each processor element 15 to read a numerical value from the working address of the data memory 12 of the processor element 15 on the left. And
In step S405, the program control circuit 17 stores the numerical value read by each processor element 15 in the working address of the data memory 12.

In step S406, the program control circuit 17 determines whether the processing in steps S404 and S405 has been performed L-1 times. When the program control circuit 17 determines that the process has not been performed L−1 times, the process returns to step S404, and when it determines that the process has been performed L−1 times, the process proceeds to step S407.

In step S407, the program control circuit 17 controls each processor element 15 to read the numerical value stored in the working address of the data memory 12 of the processor element 15 on the left. Then, in step S408, the program control circuit 17 performs an exclusive OR operation between the numerical value read by each processor element 15 and the numerical value stored in the work address of the data memory 12. Subsequently, in step S409, the program control circuit 17 uses the numerical value obtained as a result of the calculation as a flag in the data memory 12
At the work address. As a result, the value 1 is given to the L-th processor element 15 as a flag, and the value 0 is given to other processor elements 15 as flags.

Next, FIG. 10 is a flowchart for explaining the process of numbering each processor element 15. First, in step S501, the program control circuit 17 secures a working address in the data memory 12 of each processor element 15. Next, step S
In 502, the program control circuit 17 causes the selector 60A to select and output the numerical value 0 when each processor element 15 is controlled to read a numerical value from the data memory 12 of the processor element 15 on the left. Set to.

In step S503, the program control circuit 17 controls each processor element 15 to read the numerical value stored in the working address of the data memory 12 of the processor element 15 on the left. Next, in step S504, the program control circuit 17 adds 1 to the numerical value read by each processor element 15 and stores the result in the working address of the data memory 12.

In step S505, the program control circuit 17 determines whether or not the processing in steps S503 and S504 has been performed N times. If the program control circuit 17 determines that the processing in steps S503 and S504 has not been performed N times, the program control circuit 17 returns to step S503. If it determines that the processing in steps S503 and S504 has been performed N times, the processing ends. I do. As a result, the first to Nth processor elements 15
, Numbers from 1 to N can be assigned in order.

Here, in the processing in the flowchart of FIG. 10, if the process of adding 1 is to add a predetermined numerical value H, an arithmetic difference value of the predetermined numerical value H is generated as a coefficient in each processor element. can do. Further, instead of addition, subtraction may be performed.

FIG. 11 is a flow chart for explaining a process of giving each processor element 15 a modulo system of a predetermined numerical value. First, in step S601, the program control circuit 17 secures a working address in the data memory 12 of each processor element 15. Subsequently, in step S602, when each processor element 15 is controlled to read a numerical value from the data memory 12 of the processor element 15 on the left side, the program control circuit 17 selects the selector 60A.
Is set to select and output the numerical value 0.

In step S603, the program control circuit 17 controls each processor element 15 to read the numerical value stored in the working address of the data memory 12 of the processor element 15 on the left. Then, in step S604, the program control circuit 17 determines whether or not a numerical value obtained by adding 1 to the numerical value read by each processor element 15 is equal to a predetermined numerical value M. If it is determined that the read numerical value is equal to the predetermined numerical value M, the process proceeds to step S605. If it is determined that the read numerical value is not equal to the predetermined numerical value M, the process proceeds to step S605.
Proceed to 606.

In step S605, the program control circuit 17 stores the numerical value 0 in the working address of the data memory 12. On the other hand, in step S606,
The program control circuit 17 stores a numerical value obtained by adding 1 to the read numerical value in a work address of the data memory 12.

In step S607, the program control circuit 17 executes steps S603 to S606.
Is determined L times. Step S
If it is determined that the processing of Steps 603 to S606 has not been performed L times, the process returns to Step S603. If it is determined that the processing of Steps S603 to S606 has been performed L times, the processing ends. This allows
A mod (modul) of a predetermined numerical value M is assigned to each processor element.
o: remainder system).

In the above description, the case where each processor element reads a numerical value from the data memory 12 of the processor element 15 on the left side has been described.
When performing the process of reading a numerical value from the data memory 12, the Nth processor element 15 reads the numerical value from the selector 60B.

[0070]

As described above, according to the data operation device according to the first aspect, the data operation method according to the third aspect, and the transmission medium according to the fourth aspect, the operation of each processor element is supported. The data read by the first processor element and the N-th processor element among the N processor elements is selected and output, so that complicated processing is not required,
Different information can be given to each processor element. Further, it is possible to easily perform the repetition processing of the pixel data of the image signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a data processing device to which the present invention has been applied.

FIG. 2 is a block diagram illustrating a configuration example of data memories 12-1 to 12-N and element operation circuits 16-1 to 16-N.

FIG. 3 is a block diagram showing a more detailed configuration example of a data memory 12-1 and an element operation circuit 16-1.

FIG. 4 is a flowchart illustrating a process of giving a flag for distinguishing a first processor element 15 to each processor element 15;

FIG. 5 is a flowchart illustrating a process of generating a flag for distinguishing an arbitrary processor element 15 from each processor element 15;

FIG. 6 is a flowchart illustrating another process of generating a flag for distinguishing an arbitrary processor element 15 from each processor element 15;

FIG. 7 is a flowchart following FIG. 6;

FIG. 8 is a flowchart illustrating still another process of generating a flag for distinguishing an arbitrary processor element 15 from each processor element 15;

FIG. 9 is a flowchart following FIG. 8;

FIG. 10 is a flowchart illustrating a process of assigning a number to each processor element.

FIG. 11 is a flowchart illustrating a process of giving a remainder system of a numerical value M to each processor element 15;

FIG. 12 is a block diagram illustrating a configuration example of a conventional data operation device.

FIG. 13 shows a data memory 12 of the data processing device of FIG.
FIG. 3 is a block diagram showing a more detailed configuration example of an element operation circuit 16.

[Explanation of symbols]

11 serial access memory, 12 data memory, 13 arithmetic circuit, 14 output serial access memory, 15 processor element, 16 element arithmetic circuit, 17 program control circuit, 18 program memory, 60A, 60B selector

Claims (4)

[Claims] 1. Each of the processor elements includes N processor elements, each of the processor elements includes: an operation unit that operates on predetermined data; and a storage unit that stores data relating to the operation unit. A data processing device capable of reading data stored in the storage means of the processor element, wherein the control means controls the operation of each processor element; and a first of the N processor elements Data provided in the storage means of the Nth or Nth processor element and numerical value 0 and numerical value 1 are provided, and in response to control by the control means, there is provided selection means for selecting one of them. Is the storage method of the processor element adjacent to each processor element. Data processing apparatus, characterized in that when reading data, the first second or the N-th processor element is controlled to read out the data selected by said selecting means from. 2. The data processing device according to claim 1, wherein said selection means is provided for said first or Nth processor element. 3. Each of the processor elements includes N processor elements, each of the processor elements includes: an operation unit that operates on predetermined data; and a storage unit that stores data related to the operation unit. A data operation method in a data operation device capable of reading data stored in said storage means of said processor element, comprising: a control step of controlling an operation of each of said processor elements; The data of the storage means of the first or Nth processor element and the numerical value 0 and the numerical value 1 are supplied, and a selection step of selecting one of them in response to the control in the control step is provided. The control step is such that the processor elements are adjacent to each other. And controlling the first or the Nth processor element to read the data selected in the selection step when reading data from the storage means of the processor element. . 4. Each of the processor elements includes N processor elements, each of the processor elements includes: an operation unit that operates on predetermined data; and a storage unit that stores data related to the operation unit. A transmission medium for transmitting a computer program for controlling a data processing device capable of reading data stored in said storage means of said processor element, wherein a control step of controlling the operation of each processor element; Of the processor element of the first or Nth processor element, and numerical values 0 and 1 are supplied, and one of them is selected according to the control in the control step. Transmitting a computer program having a selecting step A transmission medium characterized by being transmitted.