JPH03273592A - Cache memory device - Google Patents

Abstract

PURPOSE:To accelerate the operations of saving/restoring a register to continuous areas or updating a cache by providing a data memory which can simultaneously read and write N-words of data, tag memory, comparator, address decoder, data exchange and controller. CONSTITUTION:An address register 10 is provided and a data memory 50 is provided to simultaneously read and write the N words of data which positions of addresses and columns are mutually different at all. Then, a tag memory 40 is provided to simultaneously read the N words at the same address, and comparators 61-64 are provided to compare the value read out from the tag memory 40 with one part of the value of the address register 10, and an address decoder 30 is provided. Further, a data exchange 80 is provided to exchange orders for the N words of data, and a controller 90 is execute entire control. Thus, the plural words can be simultaneously read and written and the operations can be accelerated for saving/restoring the register to the continuous areas and updating the cache or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory device that performs simultaneous reading and simultaneous writing of a plurality of words having consecutive addresses.

[Conventional technology]

In conventional cache memory devices of this type, when reading and writing multiple words consecutively during program execution and reading and writing multiple words when updating the cache, in many cases the cache memory is read -word by word. Or writing has been done. Furthermore, even if simultaneous reading or writing is possible, there are restrictions on the combination of addresses, number of words, etc. that can be accessed simultaneously.

[Problem to be solved by the invention]

As mentioned above, in conventional cache memory devices, reading or writing has been performed word by word, so when reading or writing multiple words with consecutive addresses, processing time is required for the number of words to be read, read or written. Met. Even when updating the cache, reading and writing have been performed one by one. Furthermore, even if simultaneous reading and writing were possible, the address values, number of words, etc. that could be accessed simultaneously were specified, making it impossible to access freely.

[Means to solve the problem]

The cache memory device of the present invention is composed of an address register that holds an address for reading or writing data, and N columns of memory, and N words of data at the same address in each column and N words of data at the same address in each column. , a data memory that can simultaneously read and write N words of data whose addresses and column positions are all different from each other, and a memory of N columns that allows simultaneous reading of N words at the same address, the data memory a tag memory that holds a part of the address of data stored in the tag; a comparator that compares a value read from the tag memory with a part of the value of the address register; an address decoder that decodes the value of the address register with respect to the memory; a data exchanger that changes the order of N words of data read simultaneously from the data memory; and a control device that performs overall control. It has

Another cache memory device of the present invention is composed of an address register that holds an address for reading or writing data, and N columns of memory, and includes N words of data at the same address in each column and N consecutive addresses. a data memory in which N words of data whose addresses and column positions are all different from each other can be simultaneously read and written; a tag memory that holds part of the address of the data stored in the data memory; an adder that adds the values stored in the address register; a comparator that compares part of the values of the address register; an address decoder that decodes the values of the address register and the adder with respect to the data memory and the tag memory; It has a data exchanger that changes the order of N words of data, and a control device that performs overall control.

Furthermore, another cache memory 11m1t of the present invention is composed of an address register that holds addresses for reading or writing data, and N columns of memories, and N words of data at the same location in each column and N consecutive Within an address, the addresses and column positions are all different from each other.
It consists of a data memory that can read and write word data simultaneously, and a memory that can read M words in N columns simultaneously, and it is possible to read M*N words of data stored at M addresses simultaneously. A tag memory that holds part of the address of the data stored in the data memory, an adder that adds the value stored in the address register, and a value read from the tag memory. a comparator that compares a part of the value of the address register; a comparator that compares a value read from the tag memory with a value of the adder; It has an address decoder that decodes the values of the address register and the adder, a data exchanger that changes the order of N words of data read simultaneously from the data memory, and a control device that performs overall control. are doing.

Furthermore, in another cache memory device of the present invention, in the cache device according to claim 3, when updating data, a value at an address consecutive to a value to be newly stored has already been stored. In some cases, these addresses are stored in the same column in the tag memory, and the cache memory update method prioritizes storing data in the data memory according to the position of that column.

[Effect]

In a cache memory device, data is stored in a data memory and its corresponding address is stored in a tag memory. This situation is shown in FIG. In FIG. 4, it is assumed that the data memory and the tag memory each consist of four columns of memories, and four words can be read and written simultaneously. It is assumed that the data memory holds four words of data in each block. The tag memory stores an address portion common to four words stored in the same block.

In FIG. 4, a portion of data up to address A-A+3 is stored in each column of the first block of the data memory. In a general cache memory device, the four words A-A+3 are stored in the same column, but in this method, these four words are stored in different columns as shown in Figure 4. Simultaneous reading and writing are possible. This data memory stores four 1's in the same row (for example, A, B, C, D in Figure 4), and four values (one word in each column of four consecutive rows) (
For example, A, A+1. A+2. A+3 of 4
word, A+2. A+3. A+4゜A+5 4 words, B, B+
1. B+2. B+3 (4 words, etc.) can be read and written simultaneously.

In FIG. 4, the I word at address B+1 is read out as follows. First, the row (first block) of the tag memory corresponding to address B+1 is read out and compared with B+1. As a result, it can be seen that the value in the first column corresponds to B+1. At the same time, the values of each column in the data memory corresponding to address B+1 (A+1°B+1.C+1.B+1 in the data memory in FIG. 4) are read out. Among these values, the value (B+1) in the second column is selected based on the above comparison result and the lower value of the address.

When writing one word, it is basically done in the same way as reading one word, but first the value of the tag memory is read, and then the comparison result and the lower address of the data to be written are read. A specific location in the data memory is selected depending on the value of and data is written. - When reading multiple words with consecutive addresses, first, the values in the tag memory are compared, and the data memory is read based on the comparison result. For example, when reading four words of data from address C, first, the value in the first row of the tag memory is read and compared with the address. As a result, it can be seen that data corresponding to address C is stored in the second column. Then,
In the case of reading data of multiple words, instead of reading data of four words in the same row, C, placed in different columns of consecutive rows,
C+1. C+2. Four words of C+3 are read out. Reading and writing across blocks can be achieved by performing the above operation twice.

Writing of multiple words with consecutive addresses is performed in the same way as reading.

Furthermore, reading multiple words across blocks can be achieved by multiplexing tag memory reading. For example, when reading four words from address A+2, the values of block 1 and the next block 2 in the tag memory corresponding to address A+2 are read simultaneously, and the values of block 1 and the next block 2 in the tag memory corresponding to address A+2 are read, and the values of block 1 and block 2 corresponding to address A+2 and the next block are read simultaneously. A+E3 (A+2+4 (number of columns)
), it can be confirmed that blocks 1 and 2 in the data memory are the blocks having the values to be read. In this case, depending on the comparison results and the value of the lower bit of the address, the 6th row and 2nd column, the 7th row and 3rd column,
By simultaneously reading four pieces of data in the 8th row, 0th column and 9th row, 1st column, it is possible to read out 4 words of data from A+2 at the same time.

Writing of multiple words having consecutive addresses and extending between blocks is performed in the same manner.

In FIG. 4, for example, when reading words from address B+2 to 4, since address B-B+3 and addresses B+4 to B+7 are not stored in the same column on the tag memory, the data memory The data storage locations in block 1 and block 2 are not the same. Therefore, data at address B+2 (5th row, 3rd column) and address B+5 (8th row, 3rd column) are stored in the same column on the data memory, and four words cannot be read out at the same time. In such a case, this can be achieved by performing the above read operation twice, once for each block.

To avoid this situation, when updating the tag memory and data memory, check the tag memory, and if consecutive addresses have already been registered, A ""'
By putting the addresses in the same column on the tag memory and placing the data on the data memory according to their position in that column, as in the case of A+3 and A+4 to A+7, simultaneous reads and writes can be made higher. It can be achieved with probability.

〔Example〕

Hereinafter, the apparatus of the present invention will be explained in detail using the drawings.

FIG. 1 shows an embodiment of the first invention. In FIG. 1, the first invention includes an address register 10, a decoder 20, and a tag memory 40, which is made up of 30.4 memory columns.A data memory 6, which is made up of 40.4 memory columns.
0, comparators 61 to 64, latches 70 to 73, a data exchanger 801, and a control device 90 for overall control.

A cache device that is an embodiment of the first invention can simultaneously read and write multiple pieces of data only within the same block.

Reading of one word of data is performed as follows. When reading out the value of data at address B+1, the value B+1 of the address register 10 is first given to the decoder 20, the contents of each column of block 1 are read out, and the comparators 81, 6
It is compared with the value of address register 10 by 2.63.84. At the same time, the value of the address register IO is given to the decoder 30, and the value of the 5th row of block 1 is read out. The comparison results of the comparators et, 82, 63, 84 and the value of the address register 10 are passed to the control device, thereby controlling the data exchanger 80 and the data memory 50.
The value of B+1 is sent to latch 70, and the value of C+1 is sent to latch 71.
, the value of B+1 is sent to latch 72, and the value of A+1 is sent to latch 7.
3 and stored. The value of latch 70 is then provided to the arithmetic unit.

Writing of one word is performed by applying the data to be written from the arithmetic unit to the latch 70 and the address to the address register 110. In writing, address B+1 is first given to address register 10, and the value of block 1 corresponding to address B+1 is read from tag memory 40.
It is compared with the value of address register 10 by comparators 61162.83.84. The comparison result and decoder 3
The value of the latch 70 is written to the second column and fifth row of the data memory 50 by the decoding result of the address register 10 by 0 and the controller 90 .

In FIG. 1, simultaneous reading of multiple words is performed as follows. Assuming that four words are read from address B in a row, first, value B of address register 10 is given to decoder 20, value of block 1 is read out, and comparator 61°62, Et3. It is compared with a value of 10.

Next, the comparison results of each comparator, the decoding result of the address register 1o by the decoder 3o, and the control device 90
The four words B, B+1.8+2.813 of block 1 in the data memory 50 are read out under the control of the controller θO, and shifted by the data exchanger under the control of the controller θO.
The value of B is sent to latch 70, the value of B+1 is sent to latch 71, and B
The value +2 is stored in the latch 72 and the value B+3 is stored in the latch 73, and read out to the arithmetic unit or memory device.

For simultaneous writing of multiple words, the data memory is selected in the same way, and the latches 70 and 7 are selected by the arithmetic unit or memory device.
1.72.73 The data given to data memory 50
will be written to.

As mentioned above, the data exchanger 80 is for exchanging data, and can be realized by a crossbar switch, a shifter, or the like. .

Next, an embodiment of the second invention will be described. In FIG. 2, an embodiment of the second invention includes an address register 10, a decoder 20, a tag memory 40 consisting of 3014 memory columns, and a data memory 50 consisting of 4014 memory columns. These are comparators 61 to 84, latches 70 to 73, data exchanger 80, control device 90 for overall control, latch 1001 adder 110, and selector 120.

The processing of reading and writing one word and simultaneously reading and writing data in the same block in the data memory 50 is performed in the same manner as in FIG.

Simultaneous reading and simultaneous writing of a plurality of words across blocks of the data memory 50 is performed as follows.

In simultaneous reading of multiple words, assuming that four words of data are to be read from address A+2, first,
The address A+2 is given to the address register 10 from the arithmetic unit, and the data memory 5 is sent in the same manner as in the case of FIG.
A of block 1 of 0, A+1. A+2. The value of A+3 is read. At this time, data A+2 is placed in the latch 70 and data A+3 is placed in the latch 71 according to instructions from the control device 90.
is stored in

Next, the value of the address register 10 is added by the adder 110, the selector 120 is switched by the control device 90, and the output (A+8) of the adder is added to the tag memory 40.
, and in the same manner as above, data A+4°A+5 . A+6. The value of A+7 is read out, and A+4 is stored in the latch 72 and A+5 is stored in the latch 73 according to instructions from the control bag wt90.

Finally, the values of latches 70.71 and 72.73 are passed to the arithmetic unit. In this way, reading out multiple words spanning blocks is done in two cycles.

Writing of multiple words across blocks is also performed by writing within the same block twice, similar to reading.

Next, an embodiment of the third invention will be described. In Figure 3,
An embodiment of the third invention includes an address register 101, a decoder 20, a tag memory 40, which is composed of 3014 memory columns that can read two words simultaneously, and a data memory 50, which is composed of 2014 memory columns. Comparators 61-68
, latches 70-73, data exchanger 80. The entire control is performed by the row now control AT device 90, the latch 1001, the adders 110 and 115, and the selector 120.

1 word reading and writing and data memo 1J50
The processing of simultaneous reading and writing of data in the same block is performed in the same manner as in FIG.

Simultaneous reading and simultaneous writing of a plurality of words across blocks of the data memory 50 is performed as follows.

If you want to read 4 words of data from A+2,
First, the address A+2 is given to the address register 10 by the arithmetic unit. At this time, the decoder 20 simultaneously reads block 1 corresponding to address A+2 and the next block 2 according to an instruction from the control device 90 (if block n-1 is selected by the address value, , block 0 is selected as the next block)
. The value read from block 1 of the tag memory 40 is compared with the value of the address register 10 by comparators 81, 82, 63.84, and the value read from block 2 is the addition result (A+8 ) and comparator 85.8
Compare by 8.67.68.

Next, A+2°A+3 . A+4. The value of A+5 is read and shifted by the data exchanger 80,
The data of +2 is stored in the latch 70, the data of A+3 is stored in the latch 71, the data of A+4 is stored in the latch 72, and the data of A+5 is stored in the latch 73, and then passed to the arithmetic unit. Whether the values stored in the latches 72 and 73 are correct values can be determined from the fact that the comparison results of the comparator 65 match.

If the given address is B+2, the same process as above is performed, but addresses B to B+3 and addresses B+4 to B+7 are in the same column in the tag memory 40 and their data corresponds to the data memory 50. Since the latches 70, 71, 72 .
The values read in 73 are B+2. B+3. X
.

It becomes X+1. Values X, X stored in latches 72.73
+1 is an incorrect value because the comparison result of the comparator 66 does not match.

In this case, similar to FIG. 2, the readout process is performed again, and the latches 72 and 73 are respectively
, A+5 are read.

For simultaneous writing of a plurality of words, the data memory is selected in the same manner, and the data given to the latches 70° 71, 72, 73 by the arithmetic unit is written into the data memory 50.

Although one embodiment of the first to third inventions has been described above, the present invention is not limited only to this embodiment, and includes the number of columns, the number of data in a block, the presence or absence of latches, and the data in the data memory. Even if the implementation means, such as the arrangement order, etc., are different, the basic implementation method remains the same.

〔Effect of the invention〕

According to the present invention, reading and writing of multiple words having consecutive addresses can be performed simultaneously, so it is possible to speed up operations such as saving/restoring registers to consecutive areas and updating caches.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the first invention;
FIG. 3 is a block diagram showing an embodiment of the second invention, FIG. 3 is a block diagram showing an embodiment of the third invention, and FIG. 4 is a diagram showing an example of the internal states of the tag memory and data memory. be. 10... Address register, 20.3.0... Decoder, 40... Tag memory, 50... Data memory, 61.62.63, 64, 66.66.87°68.
...Comparator? 0.71, 72.73...Latch, 8
0...Data exchanger, 90...Control device, 100.
...Latch, ito, 115...Adder, 120...
·selector.

Claims (1)

[Claims] 1. Consisting of an address register that holds addresses for reading or writing data, and N columns of memory, N words of data at the same location in each column and N consecutive
A data memory that can simultaneously read and write N words of data whose addresses and column positions are all different from each other within a single address, and a memory with N columns that allows simultaneous reading of N words at the same address. a tag memory that holds a part of the address of data stored in the data memory; a comparator that compares a value read from the tag memory with a part of the value of the address register; an address decoder that decodes the value of the address register with respect to the data memory and the tag memory; and an address decoder that decodes the value of the address register for the data memory and the tag memory;
a data exchanger for changing the order of word data;
1. A cache memory device comprising: a control device that performs overall control. 2. Consists of an address register that holds addresses for reading or writing data, and N columns of memory, including N words of data at the same location in each column and N consecutive
A data memory that can simultaneously read and write N words of data whose addresses and column positions are all different from each other within a single address, and a memory with N columns that allows simultaneous reading of N words at the same address. A tag memory that holds part of the address of the data stored in the data memory, an adder that adds the value stored in the address register, and a value read from the tag memory. a comparator that compares part of the values of the address register; an address decoder that decodes the values of the address register and the adder with respect to the data memory and the tag memory; and a comparator that performs simultaneous reading from the data memory. 1. A cache memory device comprising: a data exchanger for changing the order of data of N words; and a control device for controlling the entire cache memory device. 3. Consists of an address register that holds addresses for reading or writing data, and N columns of memory, including N words of data at the same location in each column and N consecutive
It consists of a data memory that can simultaneously read and write N words of data whose addresses and column positions are all different from each other within an address, and a memory that can read M words of N columns at the same time. Stored M
* A tag memory that can read N words of data simultaneously and holds a part of the address of the data stored in the data memory, and an adder that adds the values stored in the address register. , a comparator that compares a value read from the tag memory and a part of the value of the address register; a comparator that compares the value read from the tag memory and the value of the adder; an address decoder that decodes the values of the address register and the adder for the data memory and the tag memory;
a data exchanger for changing the order of word data;
A cache memory device characterized by including a control device that performs overall control. 4. In the cache device according to claim 3, when updating data, if values at addresses consecutive to the value to be newly stored are already stored, those addresses are stored in the same address in the tag memory. A cache memory device characterized by having a cache memory update method that prioritizes storing data in a data memory column according to the position of the column.