JP2564942B2 - Selective associative memory device and control method thereof - Google Patents

Description

The present invention relates to an associative memory device for storing and retrieving symbol codes, and more particularly to an address translation system, a computer monitor and a debugger, and diagnostics by storing knowledge information. The present invention relates to a selective associative memory device which is useful for an expert system which performs a task and its control method.

(Prior Art) Generally, an associative memory device stores some symbol codes and enables retrieval. That is, with respect to the input of the symbol code as the search data, the symbol code and the stored symbol code are compared, and if there is a match, the address of the matched symbol is output together with the match signal. If the capacity of such an associative memory device can be increased, it can be widely applied to knowledge information processing.

However, increasing the capacity of the associative memory device has the following problems.

1. The memory cells that have been conventionally used in associative memory devices have a comparison function inside to search in word parallel and bit parallel. Generally speaking, general-purpose RAM
The area is about four times larger than the cell.

2. Also, in the priority encoder that outputs a matching address in response to multiple matches, the circuit becomes abruptly complicated each time the output increases by 1 bit, and the processing time there becomes longer. Things are hard to make.

Therefore, in order to solve these problems, Japanese Patent Application No. 63-11
9830, "Selective Associative Memory Device and Control Method Therefor", presents a method of selectively searching the stored contents using a general-purpose RAM matrix.

In the present invention, in order to solve the above-mentioned problem 1, the memory cell of the associative memory device is configured by one general-purpose RAM cell by providing the comparison function outside the cell.
As a result, the area of the cell can be significantly reduced as compared with the case of using the memory cell of the conventional associative memory device. To solve problem 2 above, the memory matrix is divided into several areas and the priority encoder is shared by these divided areas.
By this, even if the storage capacity of the associative memory is increased,
By increasing the number of divided areas, the circuit scale of the priority encoder can be kept constant.

It should be noted that this method has a problem that it is not possible to search all the stored contents at the same time and only one area can be searched at the same time. However, this problem is solved by a method of classifying the searched data by, for example, the first few bits, and registering the data in each area according to the classification. This is because the search only needs to be performed for one area, and it is not necessary to search for another area.

(Problems to be Solved by the Invention) The above problem 2 has been solved by the above invention. However, as to the problem 1, although the problem of the cell area has been solved, a comparison circuit must be added as compared with the general-purpose RAM. The comparison circuit is almost 3 when converted to RAM cells.
Since the area for the cell is required, there is a drawback that an extra area is required for this amount. Therefore, there is a problem that it is difficult to increase the capacity. An object of the present invention is to solve this problem.

(Means for Solving the Problem) A selective associative device of the present invention includes a plurality of RAM matrices, a writing means connected to each bit line in the row direction of the RAM matrix, and a write means connected to each bit line. ,
A reading / comparing means which is an integrated reading means and a comparing means; a row-direction common line connecting the plurality of writing means and the reading / comparing means; and a column-direction common line pair connecting the writing means and the reading / comparing means. , Row decoding means connected to the plurality of row-direction common lines, and each of the RAs
Column decoding means connected to word lines of the M matrix, masking means connected to the column-direction common line pair, row-direction comparison result reading common lines connected to the plurality of reading / comparing means, And an encoding means connected to the comparison result reading common line, and the control method includes at least a write mode, a read mode and a search mode, and in the write mode, an area where writing is performed by the column decoding means. In the selected area, the data is written to the RAM cell selected by the row decoding means from the column-direction common line pair, and in the read mode, the area to be read by the column decoding means is selected. Selected and selected by the row decoding means in the selected area The data is read from the column direction common line pair from the selected RAM cell, and in the search mode, the area to be searched by the column decoding means is selected, and the data of all the RAM cells in the selected area and the The comparison with the search data given to the column-direction common line pair is performed, and the comparison result is read from the comparison result reading common line. Particularly, when performing the masking operation for the search, the masking is performed regardless of the given data. By means, 0 is given to the column-direction common line pair to perform masking.

(Function) 1. In an associative memory device, the encoding means and address decoding means around it are larger than the memory matrix, and the ratio increases as the memory matrix becomes larger, so it is difficult to increase the storage capacity. Met. Therefore, if you divide the memory matrix into several areas and selectively drive one of them,
The memory matrix can be enlarged without enlarging the surrounding encoding means and decoding means.

2. Highly integrated RAM by not only putting the comparison function out of the memory cell but also by integrating it with the reading circuit
The matrix can be used as it is for an associative memory device, and an associative memory device can be constructed with almost no increase in area.

According to the above-mentioned item (2), it is possible to realize a large-capacity associative memory device as a general-purpose RAM.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a selective associative memory device according to the present invention. In the figure, the selective associative memory device includes address input terminals 101 and 102 and a mask signal input terminal 1
03, a data input terminal 104, a data output terminal 105, a match address output terminal 106, a plurality of RAM matrices 110 composed of an array of RAM cells 116, and their bit lines.
A write circuit 120 connected to 112, a read / comparison circuit 130 connected to the bit line 112, a plurality of write circuits 120 and a column-direction common line pair 180 connected to the read / comparison circuit 130, and a plurality of write circuits A row-direction common line 190 connected to 120 and a plurality of reading / comparing circuits 130, a comparison result reading common line 195 connected to a plurality of reading / comparing circuits 130, and a comparison result reading circuit 1 for controlling the same.
96, a column decoder 150 connected to the word line 114 of the RAM matrix 110, and a row decoder connected to the row-direction common line 190.
160, a masking means connected to the column-direction common line pair 180, and an encoder 170 connected to the comparison result reading common line 195.

Below, the configuration of each part and the control method thereof will be described in order for the embodiment shown in FIG. After that, the overall control method will be summarized.

First, the RAM matrix 110 will be described. The RAM matrix 110 is commonly used in most chips of the semiconductor LSI memory. This RAM matrix 1
In FIG. 10, a memory cell 116 such as a dynamic (D) RAM cell, a static (S) RAM cell, or an electrically erasable read only memory (EEPROM) is provided with a bit line 112 in a row direction and a word line in a column direction. It is located at the intersection of 114.

A common usage of RAM matrix 110 is the word line
An address code is given to the input terminal 102 of the column decoder 150 (often called a row decoder) connected to 114, and all the RAM cells 116 along the selected word line are read / written (hereinafter abbreviated as R / W). Enable it. Only the cells selected by the row decoder 160 from among them are subjected to the data R / W operation through the bit line 112.

In the present invention, since the RAM matrix 110 is used as an associative memory device, the bit line 112 of the RAM matrix 110,
A writing circuit 120 and a reading / comparing circuit 130 in which a reading circuit and a comparing circuit are integrated are connected. RAM matrices are prepared for the number of bits per word, and each RAM matrix 110 stores one bit of one word. For example, if one word has 8 bits, eight RAM matrices 110 are arranged. Each RAM matrix 11
0 is divided into several areas, one of which is selected to perform data read (R), write (W), and search operations. The area is selected by inputting an area selection code from the input terminal 102 and selecting the word line 114 by each column decoder 150. When performing R / W operation, select the area and select the row decoder 16
Give an address code to 0 to specify the address in the area. The write circuit 120 performs a data write operation on the designated address, or the read / comparison circuit 130 reads the data at the designated address. In the case of a search operation, the comparison of all stored data in the selected area with the search data is performed by the read / comparison circuit.
130, the comparison result reading common line 195, and the comparison result reading common circuit 196. The search can be done in word-parallel bit-parallel for the selected area, as described in detail below. Unlike the conventional associative memory device, you cannot search all areas in parallel. For this reason, the associative memory device according to the present invention is called a selective associative device.

In this way, RAM is used as a selective associative device.
Matrix 110 is used in an unusual way.
In this usage, the number of word lines per RAM matrix 110 corresponds to the number of divided areas and the number of bit lines corresponds to the word lines per area. One word is divided and stored in each RAM matrix bit by bit.

FIG. 2 shows a circuit configuration example of the read / comparison circuit 130 according to the present invention together with the RAM cell 116.
In FIG. 2, the write circuit in FIG. 1 is shown for simplicity.
120 is omitted. The write circuit 120 may be the same as the write circuit in a general-purpose RAM. In this configuration example, a static RAM cell is used as the RAM cell 116. First,
The reading using this circuit will be described. When the word line 114 becomes high level, the data of the SRAM cell 116 is read to the bit line pair 201. If the row-direction common line 190 of FIG. 2 is selected by the decoder 160 of FIG. 1, the row-direction common line is at a high level, so that the transistor 204 is turned on and the data of the bit line pair 201 is turned on. Are amplified by the transistors 202 and 203 forming a differential pair and read out to the column-direction common line pair 180. Next, at the time of search, the word line 114 becomes high level, the data of the SRAM cell 116 is read to the bit line pair 201, and at the same time, the column direction common line pair 180
The search data is given to the transistor 202 and the transistor 2
At 03, the exclusive OR (EXOR) is taken between the data of the bit line pair 201 and the data of the column direction common line pair 180. This time,
The comparison result reading common line 195 needs to be precharged to a high level by using the comparison result reading common circuit 196 of FIG. Further, at the time of search, all the row-direction common lines are always fixed to the low level. If the data on the bit line pair 201 and the data on the column-direction common line 180 do not match,
The gate voltage of the transistor 205 goes to a high level and the charge on the comparison result reading common line 195 is pulled out to read out the mismatch. In this way, the read / comparison circuit can be configured with a small circuit by integrating the differential pair used for reading and the EXOR gate used for comparison.

FIG. 3 shows a configuration example of the masking circuit 140 in the present invention. When the mask signal input terminal 103 becomes high level, both the column-direction common line pair 180 become low level by the AND gate 302 regardless of the data given from the data input terminal 104. As a result, in FIG. 2, the gate voltage of the transistor 205 goes to a low level regardless of the data read to the bit line pair 201, and the extraction of the charge of the comparison result reading common line 195 does not occur, so that they match. Will be judged.

With such a configuration, at least three-mode operations of reading data from each area (R), writing data to each area (W), and searching stored data in each area are performed. Hereinafter, each operation mode will be described in detail. The description will be given based on FIG.

The write operation is performed as follows. An area selection code is given to the input terminal 102 of each column decoder 150 to selectively drive the word line 114, whereby an area is selected. At the same time, an address code is given to the input terminal 101 of the column decoder 160 to select the row-direction common line 180, and the write circuit 120 connected thereto is driven. As a result, the address is selected. Data is written to the RAM cell 116 designated by the selected area and address.

The reading operation is performed as follows. An area selection code is given to the input terminal 102 of each column decoder 150 to selectively drive the word line 114. Thereby, the area is selected. At the same time, an address code is applied to the input terminal 101 of the row decoder 160 to select the row-direction common line 180, and the read / comparison circuit 130 connected thereto is set to the read state. As a result, the address is selected. Data is read from the RAM cell 116 designated by the selected area and address. In the above two modes,
Since each RAM matrix 110 stores one bit of one word and data is input / output in parallel to each RAM matrix, the same word serial bit parallel R / W operation as that of a general-purpose RAM can be performed.

The search operation is performed as follows. An area selection code is given from the input terminal 102 to select an area to be searched.
The data of all RAM cells in the selected area is the bit line 112.
To the read / comparison circuit 130 and is compared with the search data provided from the data input terminal 104 through the column-direction common line pair 180. The output of each reading / comparing circuit 130 connected to the same comparison result common line 195 is ANDed by the comparison result reading common line 195 and the comparison result reading common circuit 196. The output terminal 106 of the encoder 170 outputs the address of the stored data that matches the search data.
When a mask signal is applied from the input terminal 103 of the masking circuit 140, the output of the read / comparator circuit 130 connected to the masking circuit 140 always shows a match. This makes it possible to search for data ignoring some bit differences.

In the above, the search data is input in word serial bit parallel. The input data word is compared in parallel with all the words in the selected area and the result is input in parallel to the encoder.

(Effects of the Invention) As described in detail above, the present invention makes it possible to easily realize a large capacity associative memory device. This is due to the following effects of the present invention.

1. By dividing the associative memory device into several areas and selectively using them, the storage capacity can be increased without enlarging the peripheral circuits such as the encoder.

2. Not only sharing the comparison circuit in multiple areas, but also by integrating this comparison circuit with the reading circuit,
It has become possible to construct an associative memory device with almost the same configuration as general-purpose RAM. For example, in the configuration example shown in FIG. 2, the reading / comparing circuit is different from the reading circuit of a general-purpose RAM only in that a transistor 205 and a comparison result reading common line 195 are added. These are so large that they can be ignored in the structure of the entire memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is an explanatory view of an example of a configuration of a read / comparison circuit in the first embodiment, and FIG. 3 is a masking in the first embodiment. It is explanatory drawing of the structural example of a circuit.

Claims (2)

(57) [Claims] 1. A writing means which has a plurality of RAM matrices formed by arranging RAM cells in a matrix and is connected to each pit line in the row direction of the RAM matrix, and which writes data in the RAM cells. Reading / comparing means connected to each of the pit lines and integrating a reading means for reading the data of the RAM cell and a comparing means for comparing the stored data of the RAM cell with the search data, and the plurality of writes Means and the plurality of reading / comparing means, and connecting to the plurality of writing means and the plurality of reading / comparing means, and a row-direction common line that controls the writing means or the reading / comparing means during writing or reading. , A common line pair in the column direction for inputting / outputting data and a plurality of common line lines in the row direction for writing or reading At the same time, row decoding means for selecting the row-direction common line, each column decoding means connected to the word line of each RAM matrix and selecting the word line, and masking means connected to the column-direction common line pair And a comparison result reading common line in the row direction which is connected to the plurality of reading / comparison result means and outputs a comparison result, and a comparison result showing a match as a comparison result, which is connected to the plurality of comparison result reading common lines. A selective associative memory device comprising: an encoding unit that indicates a position of a read common line. 2. The control method for the selective associative memory device according to claim 1, comprising at least a write mode, a read mode and a search mode, and in the write mode, an area for writing by the column decoding means. Data is written to the RAM cells selected by the row decoding means in the selected area from the column direction common line pair, and is read by the column decoding means in the read mode. The area to be performed is selected, and data is read from the RAM cell selected by the row decoding means in the selected area from the column-direction common line pair, and in the search mode, the column decoding means is selected. Select the area to be searched by and select the data of all the RAM cells in the selected area. And the search data given to the column-direction common line pair are compared, the comparison result is read from the comparison result reading common line, and when masking the search, the masking means is used to perform the masking regardless of the search data. A method for controlling a selective associative memory device, wherein masking is performed by giving 0 to a column-direction common line pair.