JP2590701B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a readable / writable random access semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional semiconductor memory device of this type described in Japanese Patent Application Laid-Open No. 1-241093. As shown in the figure, in the conventional semiconductor memory device, the memory cells in the memory cell array 1 is connected to the divided bit line 12, the divided bit line 12, the clock phi _1,
The main bit line 11 is connected to a column amplifier 13 via a selection transistor 15 selected by φ ₂ , and the output terminal of the column amplifier 13
Select transistor 1 selected by column decoder
6 is connected to a data input / output amplifier 14.

Next, the operation of the conventional semiconductor memory device will be described. At the time of reading, one memory cell in memory cell array 1 is selected, and its storage data is output to divided bit line 12. Furthermore, the clock φ
₁ or φ ₂ divides bit line 12 into main bit line 1
1, and the output stored data is input to the column amplifier 13 and amplified. The amplified stored data is
Select transistor 1 selected by column decoder
6, and is input to the data input / output amplifier 14 and output to the outside.

Next, at the time of writing, contrary to the above, write data is input to the data input / output amplifier 15 and output to the column amplifier 13 via the selection transistor 16 selected by the column decoder. Further, it is output to the main bit line 11. This write data is stored in one of the memory cells in the memory cell array via the divided bit line 12 selected by the selection transistor 15.

[0005]

In the above-described conventional semiconductor memory device, input / output data always passes through the main bit line 11. Thus, the main bit line is laid from end to end of the memory cell array, and has a considerable stray capacitance. When reading / writing data, the floating capacitance must be charged / discharged. Therefore, the conventional semiconductor memory device has a problem that power consumption is increased.

[0006]

According to the present invention, there is provided a memory cell array in which a plurality of memory cells are arranged in a matrix, and a word line of the memory cell array. , A read / write buffer (4a) arranged for each memory cell column, receiving output data from the memory cells in the column and outputting the write data, and a bit line of the memory cell array. Switch means (3a) connected between the pair (7, 8) and the read / write buffer;
In the semiconductor memory device comprising a, a column decoder (5) for selectively conducting said switch means, said Lee
Lengths against the memory cells arranged in the same column of the same side for de write buffer schematic k / n (where, n is 2
(7, 8) is provided with n pairs of bit lines in proportion to the above integers, k = 1, 2 ,.
The read line is approximately (k-
1) Distance that is approximately proportional to k / n from a distance that is proportional to / n
A memory cell existing between the read / write buffers, and the column decoder selectively turning on the switch means to connect any bit line pair to the read / write buffer. An apparatus is provided.

[0007]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of one embodiment of the present invention. As shown in FIG. 1, the semiconductor memory device of this embodiment includes a memory cell array 1 in which a plurality of memory cells are arranged in a matrix, a row decoder 6 for selecting a word line 2 of the memory cell array,
A read / write buffer group 4 including the entire read / write buffer arranged for each memory cell column, and a selection including the entire selection transistor connected between the bit line pair of the memory cell array and the read / write buffer. A transistor group 3 and a column decoder 5 for selecting and conducting a specific transistor from the selected transistor group
And

As will be described later, a plurality of pairs of bit lines having different lengths are formed for memory cells in the same column in the memory cell array 1, and a specific one of the bit line pairs is selected by the column decoder 5. One of the read / write buffers 4 through the read transistor
Connected to write buffer. At the time of reading or writing, the specific bit line pair is charged to a precharge potential by a precharge means (not shown).

At the time of reading or writing, a set of memory cells is selected by the column decoder 5 and the row decoder 6. In this case, the column decoder 5 selects the memory cells to be selected for the memory cells in the same column. Select the bit line pair to which the cell is connected. At the time of reading, the read data output to the selected bit line pair is input to the read / write buffer (4) and output to the outside via the buffer. At the time of writing, write data is input to the read / write buffer (4), and the write data output from the buffer is transferred to the memory cell selected by the row decoder 6 via the bit line pair selected by the column decoder 5. Written.

FIG. 2 is a circuit diagram showing a circuit configuration for one column of memory cells of the semiconductor memory device of this embodiment. As shown in the figure, a bit line pair A7 and a bit line pair B8 each connected to a plurality of memory cells 1a are connected to a read / write buffer 4a via a selection transistor 3a. The wiring of the bit line pair A7 is the bit line pair B8
Shorter than the wiring. The bit line pair A is connected to the memory cell 1a which is short from the read / write buffer 4a, and the bit line pair B is connected to the read / write buffer 4a.
Is connected only to the memory cell 1a located far from the memory cell 1a. The selection signal of the column decoder 5 is input to the gate of the selection transistor 3a. The memory cell 1a connected to the bit line pair A, B is selected by the row decoder 6. The input / output terminal of the read / write buffer 4a is connected to a power supply _VDD via a transistor 9 controlled by a precharge signal.

In the semiconductor memory device configured as described above, the stray capacitance for the bit line pair is equivalently reduced, and as a result, current consumption is reduced. Now, the bit line pair A7
Is half the wiring length of the bit line pair B8, and the same number of memory cells are connected to both bit line pairs. Assuming that the stray capacitance at the time of one bit line pair is C, the stray capacitance of the bit line pair A7 is ・ · C and the stray capacitance of the bit line pair B8 is negligible, if the stray capacitance applied to the connected memory cell is ignored. The capacity is C. Here, assuming that the memory cells are uniformly selected, the equivalent stray capacitance C _E
Is C _E = (（· C + C) ÷ 2 = 3 ・ · C. The current consumption when there is one bit line pair is
f · C · V (f: operating frequency, V: power supply voltage)
However, in the case of the present embodiment, it is 3/4 · f · C · assuming that the memory cells are evenly selected. Since only half the memory cells of one bit line pair are connected to each bit line pair A and B, the stray capacitance actually applied to the bit line pairs A and B is ２. C, smaller than C

Next, the operation of the circuit of this embodiment will be described. FIG. 3 is a timing chart for explaining the operation of the circuit shown in FIG. Now, it is assumed that the selected memory cell 1a is connected to the bit line pair A7. When the precharge signal becomes "L", the transistor 9 turns on. At this time, the output of the column decoder 5 also changes, and the selection transistor 3a connected to the bit line pair A7 turns on. H '.
At this time, the bit line pair B8 holds the immediately preceding data, and there is no change. Since the output of the row decoder 6 is "L", each memory cell 1a is closed.

Next, when the precharge signal becomes "H", the transistor 9 is turned off. Since the output of the column decoder 5 does not change, the bit line pair A7 is connected to the read / write buffer 4a. At this time, the row decoder 6 selects one of the word lines 2 and thereby the bit line pair A7
Is opened.

Assuming that the data is present at the time of reading, data stored in the selected memory cell 1a is input to the read / write buffer 4a via the bit line pair A7, and output to the outside via the buffer. At the time of writing, the write data is transferred to the read / write buffer 4a.
And the write data output from the buffer is stored in the memory cell 1a selected by the row decoder 6 via the bit line pair A7. During these series of operations, all the memory cells 1a connected to the bit line pair B8 are in a closed state, and the bit line pair B8 continues to hold the previous data. The operation is the same when the bit line pair B8 is selected by the column decoder 5. In this case,
Although a state change occurs in the bit line pair B8, the bit line pair A
7 keeps the immediately preceding data, and no state change occurs.

Although the preferred embodiment has been described above,
The present invention is not limited to the above embodiments,
Various modifications are possible within the gist of the present invention described in the claims. For example, in the embodiment, the bit line pair is divided into two, but this can be divided into three or more. If a plurality of bit line pairs are formed in different wiring layers, an increase in the chip area due to the implementation of the present invention can be suppressed.

[0016]

As described above, in the semiconductor memory device of the present invention, the bit line pairs are divided and each bit line pair is connected via the selection transistor immediately before the read / write buffer. The stray capacitance of the connected bit line pair of the memory cell closer to the read / write buffer is reduced, and accordingly, the equivalent capacitance including the connected bit line pair of the memory cell farther from the read / write buffer is reduced. Small stray capacitance is reduced. Therefore, according to the present invention, current consumption during data writing and data reading can be reduced.

For example, when two bit line pairs are used as compared with a single bit line pair, the equivalent floating capacitance and current consumption can be reduced to ／ or less.
When the number of bit line pairs is three, the stray capacitance when one bit line pair is C is defined as C, and the equivalent stray capacitance C _E is: C _E = (１ ／ · C + 2/3 · C + C) ÷ 3 = 2/3
C and the equivalent stray capacitance and current consumption can be reduced to 2/3 or less.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration for one memory cell column in one embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a conventional example.

[Explanation of symbols]

 Reference Signs List 1 memory cell array 1a memory cell 2 word line 3 selection transistor group 3a selection transistor 4 read / write buffer group 4a read / write buffer 5 column decoder 6 row decoder 7 bit line pair A 8 bit line pair B 9 transistor 11 main bit line 12 Divided bit line 13 Column amplifier 14 Data input / output amplifier 15, 16 Select transistor

Claims (3)

(57) [Claims] 1. A memory cell array in which a plurality of memory cells are arranged in a matrix, a row decoder for selecting a word line of the memory cell array, and output data from a memory cell in each memory cell column. , A read / write buffer that outputs the write data, a bit line pair of the memory cell array, and the read / write buffer.
In the semiconductor memory device comprising: a switch means connected between the write buffer, a column decoder for selectively conducting the switching means, wherein the read-La
Lengths against the memory cells arranged in the same column of the same side with respect to site buffer schematic k / n (where, n is 2 or more
N pairs of bit lines proportional to an integer, k = 1, 2,..., N)
And the bit line whose length is proportional to k / n is
From the write buffer is approximately proportional to (k-1) / n
A memo that exists between the distance and a distance approximately proportional to k / n
A semiconductor memory device wherein a recell is connected, and the switch means is selectively turned on by the column decoder to connect any bit line pair to the read / write buffer. 2. A method according to claim 1, wherein one precharge means is provided for said plurality of pairs of bit lines, and said switch means is connected between said precharge means and said plurality of pairs of bit lines. 2. The semiconductor memory device according to claim 1, wherein: 3. The semiconductor memory according to claim 1, wherein one or a plurality of bit line pairs among the plurality of bit line pairs are formed by wiring of a different layer from the other bit line pairs. apparatus.