JPH01155594A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To miniaturize a substrate and to reduce circuit parts by composing the title device of a PROM having 2<n>-type capacity, an address register having a PROM structure, and a comparing circuit to output a chip selecting signal for the PROM. CONSTITUTION:The device has a 2<n>-type capacity PROM 7 connected to (n) (n: positive integers)-bit address input terminals A0-A13 and a PROM structural address register 5 connected to the (n)-bit address input terminals A0-A13 and (m) (m: positive integers)-bit address input terminals A14 and A15 added besides A0-A13. Further, the device is composed of a comparing circuit 6 to compare address values from the (m)-bit additional address input terminals A14 and A15 with address values obtained from the address register 5 and to output the chip selecting signal for the PROM 7. Moreover, this comparing circuit 6 can be provided in the external part of the PROM 7. Thus, a circuit substrate can be miniaturized, and the number of the parts can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory circuit having a chip select function for performing address decoding of a PROM.

[Conventional technology]

Conventionally, when address decoding is performed in a semiconductor memory circuit consisting of a PROM, a chip select circuit is used separately from the PROM.

FIG. 3 is a connection circuit diagram of a PROM constituting a semiconductor memory circuit for explaining a conventional example.

As shown in FIG. 3, this memory circuit includes an external chip select circuit 9 separate from a PROM (16K bytes) 7 connected to the CPU 2 via a first address bus 3a and a data bus 4. There is. When four PROMs 7 are connected as in this example, the upper two bits of the address are decoded in the chip select circuit 9, as shown by the two second address buses 3b, and the four chip select signal lines A select signal was generated at 10.

[Problem that the invention seeks to solve]

The conventional semiconductor memory circuit described above uses PROM
Since the chip select circuit is configured externally, there is a drawback that extra mounting space and circuit components are required.

An object of the present invention is to provide a semiconductor memory circuit that does not require an external chip select circuit when using such a PROM.

[Means for solving problems]

The semiconductor memory circuit of the present invention includes a 2fi byte capacity PROM connected to an n (n+positive integer) bit address input terminal, and an m (m: positive integer) added to the n bit address input terminal. The address register of the PROM structure connected to the address input terminal of the m-bit (integer) bits is compared with the address value obtained from the address register and the address value from the m-bit additional address input terminal, and the address value obtained from the address register is The device includes a comparison circuit that outputs a chip select signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a connection configuration diagram of a semiconductor memory circuit for explaining the present invention in detail.

As shown in FIG. 1, a semiconductor memory circuit 1 is connected to a CPU 2 by an address bus 3 and a data bus 4, and here, 16 byte PROMs are used in the semiconductor memory circuit 1. The address register (not shown) of the upper semiconductor memory circuit 1 is "o ob", and the address register (not shown) of the lower semiconductor memory circuit 1 is "1".
0b++. In this case, the memory map for the upper memory circuit is 0 to 3FFFH, and the lower memory circuit is 80 to 3FFFH.
008~BFFFFM.

FIG. 2 is a single conductor memory circuit for explaining one embodiment of the present invention.

As shown in FIG. 2, such a semiconductor memory circuit 1 has an AO
The address register 5 connected to the 16-bit address input terminals up to A15 compares the address value from the upper 2-bit address input terminals (A14 to A15) with the address value obtained from the address register 5. A comparison circuit 6 that outputs a chip select signal 8, and AO to A1
3 (14 bits) address input terminal and DO~D7 (
PROM7 connected to the 8-bit) data bus terminal.
It has The capacity of this PROM7 is 16K (2”
) byte, and the address input terminal is 16 bits as described above.

Address register 5 is located at the next address of PROM 7 and is written using the same writing method as PROM 7. In this case, the address register 5 selects the upper two bits of the address input terminals AO-A15, that is, A14. A15 can be stored in PROM in advance.
The upper two bits of address A14.7. 'If A15 is written, the address stored in the address register 5 by the comparison circuit 6 and the address input terminals AO to A1
The upper two bits of the address input from A14. A1
5 is compared. As a result, if they match, the chip select signal 8 is output with valid logic, thereby
ROM7 is selected as 3u.

〔Effect of the invention〕

As explained above, the semiconductor and memory circuit of the present invention have P
Since a chip select circuit can be provided outside the ROM, it is possible to miniaturize the circuit board and reduce the number of parts.

[Brief explanation of the drawing]

FIG. 1 is a connection configuration diagram of a semiconductor memory circuit for explaining the present invention in detail, FIG. 2 is a semiconductor memory circuit diagram for explaining an embodiment of the present invention, and FIG. 3 is a conventional example. FIG. 3 is a connection circuit diagram of PROMs forming a semiconductor memory circuit for the purpose of implementing the present invention. 1... Semiconductor memory circuit, 2... CPU, 3...
・Address bus, 4...Data bus, 5...Address register, 6...Comparison circuit, 7...PROM (1
6 byte), 8...Chip select signal line, Δ0~
A15...address input terminal, DO~D7...data bus terminal.

Claims (1)

[Claims] A PROM with a capacity of 2n bytes connected to an n (n: positive integer) bit address input terminal, and an m (m: positive integer) added to the n-bit address input terminal. integer)
A PROM-structured address register connected to the bit address input terminal compares the address value from the m-bit additional address input terminal with the address value obtained from the address register, and generates a chip select signal for the PROM. 1. A semiconductor memory circuit comprising: a comparison circuit that outputs .