JPH05128327A - Ic card - Google Patents

Abstract

PURPOSE:To prevent an idle area from existing in a memory area at the time of mounting plural semiconductor storage elements different by storage capacities. CONSTITUTION:This IC card is provided with an 2M-bit semiconductor storage element 1, a 1M-bit semiconductor storage element 2, a 512k-bit semiconductor storage element 3, a 512K-bit address decoder 5 which decodes the address signal, and AND circuits 26 and 27 which obtain AND of signals, which are outputted from the address decoder 5 and specify the memory area, in accordance with the storage capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card equipped with a plurality of semiconductor memory devices having different storage capacities.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing a configuration of a main part of a conventional IC card in which a plurality of semiconductor memory elements having different storage capacities are mounted. The address decoder 5, which is a 2-Mbit decoder, includes a card enable signal 13, a high-order address signal 14 (A ₁₈ ) and a high-order address signal 15.
(A ₁₉ ) is input. The chip select signals 16, 17 and 18 output from the address output terminals #Y ₀ , #Y ₁ and #Y _{2 of the} address decoder are 2M bit semiconductor memory elements (hereinafter referred to as memory elements) 1 and 1M bit semiconductor memory elements ( Chip select terminals #CS, #CS, and #CS of 2 and 512 Kbit semiconductor memory elements (hereinafter referred to as memory elements) 3 are separately provided.

The address bus buffer 4 receives an address signal 7 (A ₀ to A0-) via an 18-line address bus 18L.
A ₁₇ ) is given. From the address bus buffer 4 to the address input terminals AD _{0 to} AD ₁₇ of the storage element 1 via the 18-line address bus 18L, the internal address signal 8 (A ₀ to
A ₁₇ ) is supplied to the address input terminals AD _{0 to} AD ₁₆ of the storage element 2 via the 17-line address bus 17L, and the internal address signal 9 (A _{0 to} A ₁₆ ) is supplied to the 16-line address bus 16L. Address input terminal AD of storage element 3 via
Internal address signals 10 (A _{0 to} A ₁₅ ) are applied to _{0 to} AD ₁₅ .

An output enable signal 20 is input to the control input buffer 19, and an internal output enable signal 21 output from the control input buffer 19 is output enable signal terminals #OE, #OE of the storage elements 1, 2, and 3. #O
It is given to both E and #OE. The data 11, 11, 11 output from the memory elements 1, 2, 3 respectively is an 8-line data bus.
8L, 8L, 8L are separately provided to the data bus buffer 6, and the data 12 output from the data bus buffer 6 is 8
It is given to the data bus 8L of the line.

Next, the operation of this IC card will be described. When the address signal 7 (A _{0 to} A ₁₇ ) is input to the address bus buffer 4, the internal address signal 8 (A _{0 to} A ₁₇ ) is supplied to the 2M-bit storage element 1 and the internal address signal 8 (A _{0 to} A ₁₇ ) is supplied to the 1M-bit storage element 2. An address signal 9 (A _{0 to} A ₁₆ ) is applied, and an internal address signal 10 (A _{0 to} A ₁₅ ) is applied to the 512 Kbit storage element 3.

On the other hand, when the output enable signal 20 is input to the control input buffer 19, the storage elements 1, 2, 3
Apply to the output enable pins #OE, #OE, and #OE, respectively. As a result, the storage elements 1, 2, 3 are ready to output data. The card enable signal 13 is the upper address signal 14 (A ₁₈ ) and the uppermost address signal 15 (A ₁₉ ).
Is decoded by. Then, the memory elements 1, 2, 3 are selected by the chip select signals 16, 17, 18 output from the address decoder 5.

In this way, the upper address signal 14 (A ₁₈ ),
When the address decoder 5 decodes the highest-order address signal 15 (A ₁₉ ) with 2M bits, the unit of the block of the decoded chip select signal becomes 2M bits. Therefore, the memory area of the IC card is 0h to 3FFFFh as the address of the memory area M ₁ of the 2M-bit memory element 1 as shown in the conceptual diagram of the memory area shown in FIG. Address of area M ₂ is 40000h
To 5FFFFh, and the address address of the memory area M ₃ of the 512 Kbit storage element 3 is from 80000h to 8FFFFh. Therefore, in the memory element 2, the address address is 60000h.
To 7FFFFh are in the airspace, and in storage element 3, 8FFFFh and beyond are in the airspace.

[0008]

As described above, the conventional IC card cannot effectively use the entire memory area of all semiconductor memory elements because an empty area is generated in the memory area of a particular semiconductor memory element. There's a problem. Further, in order to use the generated air space, it is necessary to incorporate a command for jumping the address address of the air space into a program for reading and writing data, which causes a problem that the program becomes complicated. The present invention has been made in view of the above problems, and an object thereof is to provide an IC card in which even if semiconductor memory elements having different storage capacities are mounted, no air space is generated in the memory area.

[0009]

An IC card according to the present invention decodes an input address signal to form a memory area in units of a common divisor of storage capacities of a plurality of semiconductor storage elements mounted therein. A decoder that outputs a specific signal,
An AND circuit for obtaining the logical product of the signals output by the decoder according to the storage capacity of the semiconductor memory element is provided.

[0010]

The decoder to which the address signal has been input decodes the address signal and outputs a signal for specifying a memory area in units of the common divisor of the storage capacities of semiconductor storage elements having different storage capacities. The signal output from the decoder is input to the AND circuit according to the storage capacity of the semiconductor memory element, the logical product is obtained, and the semiconductor memory element is selected by the output of the AND circuit. As a result, the output of the AND circuit for which the logical product is obtained becomes according to the storage capacity of the semiconductor memory element selected by this, and no air space is generated in the memory area of the semiconductor memory element.

[0011]

The present invention will be described in detail below with reference to the drawings showing the embodiments thereof. FIG. 3 is a block diagram showing the configuration of the IC card according to the present invention. It is equipped with a 2M bit semiconductor memory element (hereinafter referred to as memory element) 1 having a different memory capacity, a 1M bit semiconductor memory element (hereinafter referred to as memory element) 2, and a 512K bit semiconductor memory element (hereinafter referred to as memory element) 3. There is. Further, the address bus buffer 4 and the storage elements 1, 2,
The 512K-bit address decoder 5, which is the same as the minimum storage capacity of 512K bits, the data bus buffer 6, the control input buffer 19, and the AND circuits 26, 2
7 and.

A card enable signal 13, an upper address signal 14 (A ₁₈ ), an address signal 22 (A ₁₇ ), and an address signal 23 (A ₁₆ ) are input to the address decoder 5. Is decoded address output terminal #Y ₀ by the address decoder 5, # Y _1, # Y _2, the first chip select signal 4 input AND circuit 26 which is output from the # Y _3, second, third, fourth Is input to each of the input terminals, and its output signal is given to the chip select terminal #CS of the storage element 1.

The chip select signals output from the address output terminals #Y ₄ and #Y ₅ are input to the AND circuit 27, and the output signals are applied to the chip select terminal #CS of the storage element 2. Further, the chip select signal output from the address output terminal #Y ₆ is the chip select terminal #C of the storage element 3.
Given to S. The address signal 7 is input to the address bus buffer 4 via the address bus 16L consisting of 16 lines, and the address signal 22 (A ₁₇ ) and the address signal 23 (A ₁₆ ) are also input.

The internal address signal 24 (A ₁₇ ) output from the address bus buffer 4 is an address input terminal of the storage element 1.
The internal address signal 25 (A ₁₆ ) given to AD ₁₇ receives the address input terminal AD ₁₆ and the address input terminal of the storage element 2.
Given to AD ₁₆ . The address signal 10 (A _{0 to} A ₁₅ ) output from the address bus buffer 4 is given to each address input terminal AD _{0 to} AD ₁₅ of the storage elements 1, 2 and 3 via the 16-line address bus 10. ..

The output enable signal 20 is input to the control input buffer 19, and the internal output enable signal 21 output from the control input buffer 19 is stored in the storage element 1,
Output enable input pins #OE and #OE of 2 and 3
Given to #OE. The internal data output from each of the storage elements 1, 2 and 3 is input to the data bus buffer 6 through the 8-line data buses 11, 11 and 11 separately, and the data output from the data bus buffer 6 is 8 lines. Data bus 12 of. The operation mode of the address decoder 5 described above has the contents shown in Table 1.

[0016]

[Table 1]

Next, the operation of the IC card thus configured will be described with reference to FIG. 4, which is a conceptual diagram of the memory area. Table 1
As shown in FIG. 5, the address decoder 5 decodes in units of 512 Kbits and outputs a chip select signal which is a signal for specifying the memory area. Now, when selecting the memory element 1 of 2M bits, for the storage capacity of 2M bits are needed, the address output terminal _{#Y 0, # Y 1, #} Y 2, a chip select signal output from the # Y ₃ AND circuit 26 finds the logical product of.

That is, address output terminals #Y ₀ , #Y ₁ , #
When either Y ₂ or #Y ₃ is selected at the “L” level, the storage element 1 is selected by the “L” level output of the AND circuit 26. Further, the address signal 10 (A _{0 to} A ₁₅ ) and the address signal 24 output from the address bus buffer 4
(A ₁₇ ) and the address signal 25 (A ₁₆ ) are applied to the address input terminals AD _{0 to} AD ₁₅ , AD ₁₇ and AD ₁₆ of the storage element 1 to determine the address of the memory area of the storage element 1. The address address of the memory area M ₁ determined by this address signal is from 0h to 3FFFFh as shown in FIG.

Next, when the 1-Mbit storage element 2 is selected, a 1-Mbit capacity is required. Therefore, the logical product of the chip select signals output from the address output terminals #Y ₄ and #Y ₅ is ANDed. 27, and when either of the address output terminals #Y ₄ and #Y ₅ is selected at the “L” level, the storage element 2 is selected by the “L” level output of the AND circuit 27. Further, the address signal 10 (A _{0 to} A ₁₅ ) and the address signal 25 (A ₁₆ ) output from the address bus buffer 4 are given to the address input terminals AD _{0 to} AD ₁₅ and AD ₁₆ of the storage element 2, and the storage element 2 Determine the address of the memory area of.
The memory area M determined by this address signal
The address address of ₂ is 40000h to 5FFF as shown in Fig. 4.
Up to Fh.

Next, when the storage element 3 of 512 Kbits is selected, since a capacity of 512 Kbits is required, the storage element 3 is generated by the "L" level chip select signal 18 output from the address output terminal #Y _6. Select. Further, the address signal 10 (A _{0 to} A output from the address bus buffer 4)
₁₅ ) is applied to the address input terminals AD _{0 to} AD ₁₅ of the storage element 3 to determine the address of the memory area of the storage element 3. The address address of the memory area M ₃ determined by this address is from 60000h to 6FFFFh.

Therefore, in the memory area M ₁ of the address addresses 0h to 3FFFFh, the storage element 1 starts from the address address 40000h.
The memory element 2 occupies the memory area M ₂ up to 5FFFFh, and the memory element 3 occupies the memory area M ₃ from the address address 60000h to 6FFFFh. Absent. Then, as described above, when any one of the storage elements 1, 2 and 3 is selected, the output enable signal 20 is set to the control input buffer.
19 and then the internal output enable signal
By outputting 21 to the output enable terminals #OE of the storage elements 1, 2, and 3, the data in the memory area of the selected storage element is output to the data bus 12 via the data bus buffer 6. ..

FIG. 5 is a block diagram showing the configuration of an IC card which is another embodiment of the present invention. Address decoder 5
The chip select signals output from the address output terminals #Y ₀ and #Y ₁ of the memory element 2 are input to the AND circuit 27, and the output is given to the chip select terminal #CS of the storage element 2. Address output terminal _{#Y 3, # Y 4, #} Y 5, the first chip select signal to 4-input AND circuit 26 which is output from the # Y _6, second, third, and enter into the fourth input terminal And outputs the output signal to the chip select terminal #CS of the memory element 1.

The chip select signal 18 output from the address output terminal #Y ₂ is the chip select terminal of the storage element 3.
It is given to #CS. And the other structure is as shown in FIG.
The IC card is the same as the IC card shown in, and the same components are denoted by the same reference numerals. The IC card, the address output terminal #Y ₀ of the address decoder 5, the storage element 2 of 1M bit is selected by the output signal of the AND circuit 27 obtains a logical product of a chip select signal output from the # Y _1, As shown in FIG. 6, the address address of the memory area M ₁ is from 0h to 1FFFFh.
Up to

Further, the 512 Kbit memory element 3 is selected by the chip select signal output from the address output terminal #Y _2, and the address address of the memory area M ₃ is 20000 h.
To 2FFFFh. Address output terminals #Y ₃ and #Y
_4, # Y _5, being selected memory element 1 of 2M bits by the output signal of the AND circuit 26 obtains a logical product of a chip select signal output from the # Y _6, address number of the memory area M ₁ is 30000h To 6FFFFh. That is, the storage element 2 addresses from address 0h to 1FFFFh
Storage element 3 from 0h to 2FFFFh, address address 30000h
From 6 to 6FFFFh will be occupied, and no airspace will occur in this case as well.

In this embodiment, 512 Kbits is used as the unit of the minimum storage capacity, but any common divisor of 512K may be used and the unit is not limited to 512K bits. Further, although the same type of semiconductor memory elements are mounted in the present embodiment, it is needless to say that different types of semiconductor memory elements can be mounted as long as the same method of inputting an address signal is used.

[0026]

As described above in detail, according to the present invention, even if semiconductor memory devices having different storage capacities are mounted, the memory areas can be made continuous and no air space is generated in the memory areas. Therefore, the entire memory area can be used effectively.
Also, it is not necessary to use a complicated program that incorporates a command to jump the address address of the air space into the program.
It has an excellent effect of providing an IC card.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a conventional IC card.

FIG. 2 is a conceptual diagram of a memory area of a semiconductor memory element in the IC card shown in FIG.

FIG. 3 is a block diagram showing a configuration of a main part of an IC card according to the present invention.

FIG. 4 is a conceptual diagram of a memory area of a semiconductor memory element in the IC card shown in FIG.

FIG. 5 is a block diagram showing a main configuration of an IC card showing another embodiment of the present invention.

6 is a conceptual diagram of a memory area of a semiconductor memory element in the IC card shown in FIG.

[Explanation of symbols]

 1 2 Mbit semiconductor memory element 2 1 Mbit semiconductor memory element 3 512 Kbit semiconductor memory element 4 Address bus buffer 5 Address decoder 6 Data bus buffer 19 Control input buffer 26 4 input AND circuit 27 AND circuit

[Procedure amendment]

[Submission date] June 22, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

In this way, the upper address signal 14 (A ₁₈ ),
When the address decoder 5 decodes the highest-order address signal 15 (A ₁₉ ) with 2M bits, the unit of the block of the decoded chip select signal becomes 2M bits. Therefore, the memory area of the IC card is 0h to 3FFFFh as the address of the memory area M ₁ of the 2M-bit memory element 1 as shown in the conceptual diagram of the memory area shown in FIG. Address of area M ₂ is 40000h
To 5FFFFh, and the address address of the memory area M ₃ of the 512 Kbit storage element 3 is from 80000h to 8FFFFh. Therefore, in the memory element 2, the address address is 60000h.
From until 7FFFFh becomes airspace.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

Next, the operation of the IC card thus configured will be described with reference to FIG. 4, which is a conceptual diagram of the memory area. Table 1
As shown in FIG. 5, the address decoder 5 decodes in 512 Kbit units and outputs a chip select signal which is a signal for specifying a memory area. Now, when selecting the memory element 1 of 2M bits, for the storage capacity of 2M bits are needed, the address output terminal _{#Y 0, # Y 1, #} Y 2, a chip select signal output from the # Y ₃ AND circuit of AND circuit 26
Ask in.

[Procedure 3]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (1)

[Claims] 1. An IC card in which a plurality of semiconductor memory elements having different storage capacities are mounted, and the semiconductor memory element is selected by an address signal, the address signal is decoded to store the semiconductor memory element. The semiconductor memory is provided with a decoder that outputs a signal that specifies a memory area in units of the common divisor of capacity, and an AND circuit that obtains a logical product of the signals according to the memory capacity of the semiconductor memory element. An IC card characterized by being configured to select elements.