KR920006849A - Extended Memory Addressing System - Google Patents

Extended Memory Addressing System Download PDF

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Publication number
KR920006849A
KR920006849A KR1019900014393A KR900014393A KR920006849A KR 920006849 A KR920006849 A KR 920006849A KR 1019900014393 A KR1019900014393 A KR 1019900014393A KR 900014393 A KR900014393 A KR 900014393A KR 920006849 A KR920006849 A KR 920006849A
Authority
KR
South Korea
Prior art keywords
addressing system
bus
extended memory
memory
address
Prior art date
Application number
KR1019900014393A
Other languages
Korean (ko)
Inventor
고재찬
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019900014393A priority Critical patent/KR920006849A/en
Publication of KR920006849A publication Critical patent/KR920006849A/en
Priority to KR2019930007202U priority patent/KR930004906Y1/en

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Abstract

내용 없음No content

Description

확장메모리의 주소지정시스템Extended Memory Addressing System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명 확장메모리의 주소지정시스템을 설명하기 위한 도면,1 is a view for explaining an addressing system of an extended memory of the present invention;

제2도는 제1도에 도시한 모우드레지스터의 동작을 설명하기 위한 도면.2 is a view for explaining the operation of the mode register shown in FIG.

Claims (1)

n비트의 어드레스버스를 갖는 중앙처리부(1)와 유효주소발생부(2)및 n+m비트로 확장된 어드레스버스를 갖는 메모리부(6)로 이루어진 반도체메모리의 주소지정시스템에 있어서, 중앙처리부(1)와는 데이타버스(20)및 제어신호버스(30)로 연결되며, 상기 메모리부(6)와는 확장된 어드레스버스(10;An∼An+m-1,11)로 연결되는 모우드레지스터(5)를 구비하여 확장된 메모리의 주소를 지정하는 것을 특징으로 하는 메모리의 주소지정시스템.In the addressing system of a semiconductor memory comprising a central processing unit 1 having an n-bit address bus, an effective address generator 2, and a memory unit 6 having an address bus extended to n + m bits, the central processing unit ( 1) is connected to the data bus 20 and the control signal bus 30, and the memory register 6 is connected to the extended address bus (10; A n ~ A n + m- 1,11) And (5) to designate an address of the expanded memory. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900014393A 1990-09-12 1990-09-12 Extended Memory Addressing System KR920006849A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019900014393A KR920006849A (en) 1990-09-12 1990-09-12 Extended Memory Addressing System
KR2019930007202U KR930004906Y1 (en) 1990-09-12 1993-05-01 Address assignment system in extended memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900014393A KR920006849A (en) 1990-09-12 1990-09-12 Extended Memory Addressing System

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR2019930007202U Division KR930004906Y1 (en) 1990-09-12 1993-05-01 Address assignment system in extended memory

Publications (1)

Publication Number Publication Date
KR920006849A true KR920006849A (en) 1992-04-28

Family

ID=67542765

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900014393A KR920006849A (en) 1990-09-12 1990-09-12 Extended Memory Addressing System

Country Status (1)

Country Link
KR (1) KR920006849A (en)

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