JP3060812B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus (hereinafter referred to as " information processing apparatus" ).
In particular, the present invention relates to a microcomputer having an improved address output function.

[0002]

2. Description of the Related Art As a technique for increasing the speed of a microcomputer, it is generally practiced to increase a bus width for accessing an external memory. For example, by changing the bus width from an 8-bit length to a 16-bit length, it is possible to obtain at most twice the bus performance.

However, if the bus width is increased, the number of components for controlling the bus is increased, and the number of wiring patterns is increased, and the system cost is increased. Moreover, memories with a large bus width are expensive and difficult to obtain. Therefore, microcomputers with built-in bus sizing functions are provided by various companies so that a large bus width can be selected in a high-performance system and a small bus width can be selected in a low-cost system.

An example of such a microcomputer having a built-in bus sizing function is disclosed in Japanese Patent Application No. 4-235782.
It is described in.

[0005] The microcomputer described in Japanese Patent Application No. 4-235782 divides an address space in which an external memory is arranged into a plurality of areas, and accesses a plurality of flags that determine the word length of each area and the state of the flags. Means is provided for selecting the word length on the external data bus terminal according to the address.

The internal structure of this conventional microcomputer will be described with reference to the drawings.

Referring to FIG. 6 which is a block diagram showing the configuration of a conventional microcomputer, the microcomputer of this embodiment has an 8-bit lower address and data time division bus terminal (hereinafter referred to as AD (7-0)). 2)
An 8-bit upper address and data time division bus terminal (hereinafter, referred to as AD (15 to 8)) 3, an address latch timing signal terminal (hereinafter, referred to as ASTB) 4, and a read signal terminal (hereinafter, referred to as ASTB). (Referred to as inverted RD)
5 and a write signal terminal to an even address (hereinafter, inverted LWR)
6) and a write signal terminal to an odd address (hereinafter, referred to as an odd address)
7, an upper data bus 32, a lower data bus 33, an upper address bus 34, a lower address bus 35, and a bus width designation flag 3.
6, the address comparator 37, and the data selector 3
9, multiplexers 641 and 642, and a timing generation circuit 643.

The CPU 31 outputs an address at the time of memory access to the upper address bus 34 and the lower address bus 35, inputs and outputs data to the upper data bus 32 and the lower data bus 33, and supplies an external signal to the timing generation circuit 643. It outputs a memory selection signal 45, a read signal 46, a write signal 47, and a clock 48.

The upper address bus 34 is connected to the ADs (15 to 8) 3 via a multiplexer 641 and supplies an address to an address comparator 37.

The lower address bus 35 is connected to the multiplexer 6
It is connected to AD (7-0) 2 via 42.

The upper data bus 32 is connected to the multiplexer 6
It is connected to AD (15 to 8) 3 via 41 and to AD (7 to 0) 2 via data selector 39 and multiplexer 642.

The lower data bus 33 is connected to the data selector 3
9. Connected to the AD (7-0) 2 terminal via the multiplexer 642, and supplies setting data to the bus width designation flag 36.

The bus width designation flag 36 is a flag writable by the CPU 31 via the lower data bus 33. The address comparator 37 compares the bus width designation flag with the upper address and supplies the bus width designation signal 44 to the data selector 39 and the timing generation circuit 643.

The timing generation circuit 643 supplies time division timing to the multiplexers 641 and 642, and also outputs ASTB4, RD5, LWR6, H
Generate WR7.

Next, the operation inside the microcomputer will be described.

First, the CPU 31 performs writing to the bus width designation flag 36 via the lower data bus 33 in order to designate the word length of the externally connected memory.

In this embodiment, bit 0 of the bus width designation flag 36 corresponds to the address area 0000H to 7FFFFH, and bit 1 corresponds to the address area 8000H to FFFFH.

When the bus width designation flag 36 is at a high level, AD (7 to 0) is used when a corresponding area is accessed.
2, AD (15 to 8) 3 has a bus width of 16 bits, and has an 8-bit length in the case of a low level.

After executing the instruction to set the bus width designation flag 36, an arbitrary address area can be accessed by the program.

When an access to the external memory occurs, C
The PU 31 outputs an address of the external memory to the upper address bus 34 and the lower address bus 35, and inputs / outputs data to / from the upper data bus 32 and the lower data bus 33.
It also outputs one of a read signal 46 and a write signal 47, an external memory selection signal 45 and a clock 48.

The address comparator 37 generates a bus width designation signal 44 from the address on the upper address bus 34 and the state of each flag of the bus width designation flag 36, and outputs the signal to the timing generation circuit 634 and the data selector 39.

The timing generation circuit 643 performs an AST based on the bus width designation signal 44, the read signal 46, the write signal 47, the external memory selection signal 45, and the clock 48.
The timing and input / output of B4, RD5, LWR6 and HWR7 are controlled. At the same time, the timing generation circuit 643 controls the multiplexers 641 and 64
2 time division timing control.

The data selector 39 receives the bus width designation signal 4
4 to select whether to input / output one of the upper data bus 32 and the lower data bus 33 to / from AD (7-0) 2.

AD (7-0) 2 and AD (15-8)
3 outputs an address while ASTB4 is at a high level, and inputs / outputs data while one of RD5, LWR6 and HWR7 is at a low level.

ASTB4 has AD (7-0) 2, AD
(15-8) The latch timing signal of the address output by 3 is output. The RD5, LWR6, and HWR7 output a read request signal to the external memory, a write request signal from the upper bus, and a write request signal from the lower bus, respectively.

Next, the configuration of a system in which a memory is connected to the outside of a conventional microcomputer will be described.

FIG. 7 shows a configuration in which a RAM having a word length of 8 bits and a ROM having a word length of 16 bits are connected. Referring to FIG. 8, the AD (7-0) 2 of the microcomputer 701 is connected to the ROM 15 and the RAM 16 via the lower bus 10 and the address latch 8.

AD (7-0) 2 is stored in ROM 15 and R
When accessing the AM 16, the lower 8 bits of the address to be accessed are output, and 8-bit data is input / output when accessing an even address. However, when the bus width is 8 bits long, AD (7 to 0) 2 inputs and outputs data both when accessing an odd address and when accessing an even address.

The ADs (15 to 8) 3 are supplied to the ROM 15 and the RAM 16 via the upper bus 11 and the address latch 9.
Connected to The ADs (15 to 8) 3 output the upper 8 bits of the address and input / output 8-bit data of odd addresses. However, if the bus width is 8 bits, AD (15
8) 3 only outputs the upper address.

The ASTB 4 is connected to the address latches 8 and 9 and indicates that it goes to a high level at the timing of latching the address output by AD (15 to 8) 3 and AD (7 to 0) 2.

The RD5 is connected to the ROM 15 and the RAM 16 and goes low when data is read. The inverted LWR 6 is connected to the RAM 16. Since the bus width of the RAM 16 is 8 bits, nothing is connected to the inverted HWR 7.

LWR6 and HWR7 indicate the timing of writing data to the even and odd addresses of the memory, respectively. However, when the bus width is 8 bits, the write timing at which the inverted LWR 6 becomes the low level is shown both when writing to an odd address and when writing to an even address.

The address decoder 13 is an address decoder for selecting one of the ROM 15 and the RAM 16.
The selection signal is output to the OM 15 and the RAM 16.

The ROM 15 is an RO having a bus width of 16 bits.
The M and RAM 16 are RAMs having a bus width of 8 bits.

The conventional AD (15 to 8) 3, AD (7 to
0) 2 is based on the premise that the output address is latched in the address latches 8 and 9, and only the setup and hold for the ASTB 4 is guaranteed. Has become.

Referring to FIG. 9 showing a system configuration in which only a memory having a word length of 8 bits is connected to a conventional microcomputer, a ROM 315 is a ROM having a word length of 8 bits. 9, lower bus 10, address decoder 13, and RD5. The difference from the configuration of FIG.
15 is an 8-bit memory, so that it is not connected to the upper bus for data output.

The reason why the address latch needs 16 bits is that AD (15-8) 3 and AD (7-0) 2 are ASTB
This is because there is a possibility that the address is output only at timing 4.

[0038]

In a conventional microcomputer having a bus sizing function, the output of the address and data time division bus terminals during a period in which no external memory is accessed is not guaranteed, so that a bus having a long word length is not provided. It was necessary to provide an external address latch corresponding to the above. If an address latch is not provided, the address input of the memory changes even during memory access with a short word length, causing malfunction, and the address input may float and a large current may flow. For this reason, the number of parts has been increased.

When a product having upward compatibility is developed especially for a microcomputer to which only a memory having a short word length can be connected, the external connection should also be compatible. There is a problem that the compatibility with the conventional configuration of the additional system is lost.

In the microcomputer according to the present invention, when the address bus and the data bus are separated from each other as a part of access means for an external memory, the data bus terminal inputs / outputs data to / from the memory in a time-division manner. An address and data time-division bus terminal to divide the address space in which the memory is arranged into a plurality of regions, and select a word length of the data bus terminal for each region. When accessing the area where the short word length is selected ,
Means are characterized in that, among the certain address and data time division bus terminals, there is provided a means for continuously outputting an address from the input / output terminal not used as a data bus so that a memory input is not in an indeterminate state during an access period.

Further, during a period in which no access to the memory of the outer section, supra fill in some or all of said address and data time sharing bus terminal is an input-output terminal
Ru can have a means for outputting a high-level constant fixed value from the force terminal.

[0042] Furthermore, during a period in which no access to the memory of the external part, some or all of the front of said address and data time sharing bus terminal is an input-output terminal
Having means for outputting an address from the entry / output terminal
Ru can also.

[0043] Further, a built-in means for storing an address accessed the memory of the external during the time not access the memory of the external unit, the address and data time sharing bus terminal is an input-output terminal some or all of the input and output terminals of out, Ru can also have a means for outputting an address said memory means holds.

[0044]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the main part of the internal configuration of the microcomputer according to the first embodiment.

Referring to FIG. 1, the difference from the conventional example shown in FIG. 6 is that an address latch 38 and an address selector 40 are newly added. That is, in the conventional example CPU31 of AD (7 to 0) has been is connected to a multi-press support 41 directly by high-order address bus 34, in this embodiment, the add in the middle of the high-order address bus 34
A selector 40 is inserted, one input terminal of which is connected to the upper address bus 34, the other input terminal is connected to the upper address bus 34 via the address latch 38, and the output terminal of which is connected to the multiplexer 41. It is connected to the.

The address latch 38 and the address selector 40 are controlled by an external memory selection signal 45, and the multiplexer 41 is controlled by a control signal 50 supplied from a timing generation circuit 43.

The other structure is the same as that of the conventional example, and the components 41 and 641, 42 and 642 and 43 and 64
3 correspond to each other, and the same reference numerals are given to other same components, and the description of the configuration is omitted.

The address latch 38 has a function of holding an address on the upper address bus 34 in synchronization with the external memory selection signal 45, and supplies the held address to the address selector 40.

The address selector 40 outputs the address held by the address latch 38 to the multiplexer 41 while the external memory is not being accessed, and outputs the address on the upper address bus 34 while the external memory is being accessed. Output.

The timing generation circuit 43 responds to the bus width designation signal 44, the external memory selection signal 45, the read signal 46, the write signal 47 and the clock 48 by using the control signal 4.
9 and 50 control the time-division operation and the input / output operation of the multiplexers 41 and 42.
TB4, RD5, and LWR7 are generated.

Next, the operation will be described with reference to FIG. 2 showing a timing chart at the time of memory access according to the first embodiment. AD (7-0) 2 and AD (15-8) 3 Outputs an address during a period when ASTB4 is at a high level, and outputs RD5 and LWR6.
And one of the inverted HWRs 7 inputs and outputs data during a low level period.

During a period in which the CPU 31 does not access an external memory, the address latch 38 holds the data in synchronization with the external memory selection signal 45 and the address selector 40 selects the address in response to the external memory selection signal 45. The address of the address AD (15 to
8) Output to 3. This address is the external memory address accessed immediately before.

When accessing an external memory, if the access word length (bus width) is 8 bits, AD (15
8) 3 continues to output the upper address during the access period, and if the bus width is 16 bits, the upper address and the data at the odd address are input / output in a time division manner as in the conventional example.

Therefore, the AD (15 to 8) 3 always outputs or holds the upper address except during the access period to the memory having the bus width of 16 bits.

Next, a memory having a word length of 8 bits and 1
When a memory having a word length of 6 bits is mixedly connected, the microcomputer 1 of the present embodiment also uses a 16-bit bus width to access AD (15 to 15) similarly to the conventional example.
8) Since 3 performs the time division operation, a 16-bit address latch is required. Therefore, the configuration of the system in this case is the same as that of the conventional example, and the description is omitted here.

A case where only a memory having a word length of 8 bits is connected to the microcomputer 1 of this embodiment will be described. Referring to FIG. 3 showing the configuration of a main part of a system using the microcomputer 1 of the present embodiment, the difference from the conventional example is that the ADs (15 to 8) 3 do not pass through the address latch 9 of the conventional example. That is, they are directly connected to the ROM 115 and the address decoder 13, respectively.
The other configuration is the same as that of the conventional example, and the same components are denoted by the same reference numerals and description of the configuration will be omitted.

When accessing a memory having a word length of 8 bits, the AD (15 to 8) 3 outputs the upper address during the access, and outputs the upper address during a period when no external memory is accessed. Since the data is held and output, even if the AD (15 to 8) 3 is directly connected to the ROM 115 and the address decoder 13, a malfunction or a through current due to floating of the address does not occur.

Therefore, the configuration in the case where an 8-bit memory is connected to the present embodiment can reduce the number of address latches as compared with the conventional example.

The output of the AD (15 to 8) 3 holds the address up to the next access when the external memory is accessed. As a result AD
(15-8) The switching current generated in (3) can be reduced.

Next, referring to FIG. 4, which is a block diagram showing the main part of the internal configuration of the microcomputer 1 of the second embodiment, the difference from the first embodiment is that the address latch 38 is omitted. It is. That is, the input terminal to which the output of the address latch 38 of the address selector 40 is connected is fixed at a high level by removing the address latch 38.

The other configuration is the same as that of the first embodiment, and the same components are denoted by the same reference numerals and description of the configuration will be omitted.

By fixing the input terminal to the high level, the address selector 40 outputs one of the address on the upper address bus 34 and the high level fixed value to the multiplexer 41.

Referring also to FIG. 5 showing a timing chart at the time of memory access in the second embodiment,
The timing generation circuit 43 outputs the high level generated by the address selector 40 to the AD (15 to 15) via the multiplexer 41 at the timing when the external access is not executed.
8) Generate a control signal to output to (3).

When accessing an external memory, if the external bus width is specified as 8 bits, AD (15 to
8) 3 keeps outputting the upper address during the access period.

When the bus width is 16 bits, A
D (15 to 8) 3 inputs / outputs data of an upper address and an odd address in a time-sharing manner as in the first embodiment.

Therefore, AD (15 to 8) 3 always outputs one of the high level and the upper address except when the bus width is 16 bits.

When a memory having a word length of 8 bits and a memory having a word length of 16 bits are connected together, the microcomputer 1 of the present embodiment has a bus width similar to that of the first embodiment. AD (15 to
8) Since 3 performs time division operation, a 16-bit address latch is required.

Therefore, the configuration of the system is the same as that of the first embodiment, and the description of the configuration is omitted.

Next, when only a memory having a word length of 8 bits is connected to the microcomputer 1 of the present embodiment, the terminal configuration and memory connection of the microcomputer of the first embodiment are the same. The description of the configuration is omitted.

When accessing a memory having a word length of 8 bits, AD (15 to 8) 3 outputs an upper address during an access period, and outputs a high level during a period when no external memory is accessed. Output.

Therefore, AD (15-8) 3 is directly converted to R
Even if the OM 115 and the address decoder 13 are directly connected, a through current does not occur due to a malfunction or floating address.

[0073]

The microcomputer of the present invention outputs at least one of an address, a high level and a low level from an address not used as a data bus and a data bus terminal during a period in which a memory having a long word length is not accessed. Providing the means has the effect of reducing the number of externally connected address latches in a system using only short word length memories.

In particular, in a microcomputer developed for the purpose of replacing a low-end microcomputer to which only a memory having a short word length can be connected, only the microcomputer can be replaced as it is by the system configuration of the low-end microcomputer. In addition, there is an effect that an efficient system development can be realized, for example, a new system is constructed by sharing a substrate and the like.

The first embodiment also has the effect of reducing the switching current at the address and data time division bus terminals.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main part of an internal configuration of a microcomputer according to a first embodiment.

FIG. 2 is a timing chart at the time of memory access according to the first embodiment;

FIG. 3 is a block diagram showing a configuration of a main part of a system using the microcomputer of the first embodiment.

FIG. 4 is a block diagram illustrating a main part of an internal configuration of a microcomputer according to a second embodiment.

FIG. 5 is a timing chart at the time of memory access according to the second embodiment.

FIG. 6 is a block diagram showing a main part of an internal configuration of a conventional microcomputer.

FIG. 7 is a block diagram showing a system configuration when a conventional 8-bit word-length RAM and a 16-bit word-length ROM are connected.

FIG. 8 is a timing chart at the time of memory access in a conventional example.

FIG. 9 is a block diagram showing a system configuration when only an 8-bit word-length memory is connected to a conventional microcomputer.

[Explanation of symbols]

 1,701 microcomputer 2 AD (7-0) 3 AD (15-8) 4 ASTB 5 inverted RD 6 inverted LWR 7 inverted HWR 8,9 address latch 10 lower bus 11 upper bus 13 address decoder 15,115 ROM 16 RAM 31 CPU 32 Upper data bus 33 Lower data bus 34 Upper address bus 35 Lower address bus 36 Bus width designation flag 37 Address comparator 38 Address latch 39 Data selector 40 Address selector 41, 42, 741, 742 Multiplexer 43, 743 Timing generation circuit 44 Bus width designation signal 45 External memory selection signal 46 Read signal 47 Write signal 48 clock

Claims (4)

(57) [Claims] When an address bus and a data bus are separately provided as a part of an access means for an external memory, the data bus terminal inputs and outputs data to and from the memory in a time-division manner. An information processing device having a divided bus terminal, dividing an address space in which the memory is arranged into a plurality of regions, and having a unit for selecting a word length of the data bus terminal for each region. when accessing to the selected region, of the address and data time sharing bus terminal is an input-output terminal, before not used as a data bus entry
From the output terminal, the memory input is undefined during the access period
An information processing apparatus comprising means for continuously outputting an address so as not to output the address. During wherein not access the memory of the external period, from some or all of the input and output ends <br/> terminal of said address and data time sharing bus terminal is an input-output terminal 2. The information processing apparatus according to claim 1, further comprising means for outputting a fixed high-level fixed value . During wherein not access the memory of the external period, from some or all of the input and output ends <br/> terminal of said address and data time sharing bus terminal is an input-output terminal 2. The information processing apparatus according to claim 1, further comprising means for outputting an address. 4. A built-in means for storing an address accessed the memory of the external during the time not access the memory of the external unit, the address and data time sharing bus terminal is an input-output terminal Some or all of them
2. The information processing apparatus according to claim 1, further comprising a unit that outputs an address held by the storage unit from the input / output terminal.