JP2002342105A - System for writing to flash memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flash memory writing system capable of writing a program to a flash memory even though the flash memory is employed at a start address. SOLUTION: Even though a first memory space in the vicinity of the start address is assigned to the flash memory 3 when a main substrate 1 is started with nothing connected to a connector 4 for an expansion bus, the first memory space in the vicinity of the start address is assigned to a ROM 12 and a ROM 13 when the main substrate 1 is started with a flash boot substrate 10 connected to the connector 4 for an expansion bus, the flash memory 3 is assigned to a second memory space different from the first memory space, and therefore, a program to be stored in the ROM 13 can be written to the flash memory 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a flash memory writing system for writing a program to be executed by a CPU into a flash memory as a main memory.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 03-139720 discloses that
A technique for restarting a CPU is disclosed.
In a system using flash memory as the main memory,
Using this technique, the flash memory is not allocated to the first memory space near the start address where the CPU first accesses after the reset, and the pull-up / down resistors
Creates a byte JMP instruction, jumps the execution address to the address of the flash memory at the time of normal startup, and writes the program to the flash memory.
The ROM storing the program to be written to the flash memory is allocated to the start address, and the flash memory writing program is operated.

However, in recent CPUs, there are many items that need to be set at the time of initialization. For example, it is necessary to set the bus width and type of the memory. There is something to do.

[0004]

As described above, in a conventional system using a flash memory as a main memory, the flash memory has not been developed at the start address. However, some recent CPUs have a problem in that the memory bus width and type must be set, and some flash memories must be developed at the start address.

An object of the present invention is to provide a flash memory writing system capable of writing a program to a flash memory even if the flash memory is developed at a start address.

[0006]

In order to solve the above-mentioned problems, a flash memory writing system according to the present invention comprises:
At the time of reset, a CPU for setting a bus width for accessing a first memory space near a start address to be accessed first, and a bus of a predetermined width are connected to the CPU and allocated to the first memory space. A flash memory writing system for writing a first program executed by the CPU to the flash memory, wherein the flash memory is stored in a second memory separate from the first memory space. It is also allocated to the memory space, and when the CPU is reset, the first
And a memory storing a second program for writing the first program into the flash memory is connected to the bus via an expansion bus connector for expanding the bus. The second program is executed by making the flash memory writable, allocating the second program to the first memory space, and executing the second program.

In the flash memory writing system of the present invention, when writing a program to the flash memory, the flash memory is allocated to a second memory space different from the first memory space near the start address, A second program for writing the program in the flash memory is allocated to the first memory space. With this configuration, the second program can be executed after the CPU is reset, and the first program can be written to the flash memory. Therefore, in the flash memory writing system of the present invention, a program can be written to the flash memory even if the flash memory is assigned to the start address.

In another flash memory writing system according to the present invention, at the time of reset, a CPU in which a bus width is set when accessing a first memory space near a start address to be accessed first, and a CPU having a predetermined width. A flash memory connected to the CPU by a bus and allocated to the first memory space, wherein the flash memory writing system for writing a first program executed by the CPU to the flash memory; When the CPU is reset, the memory storing the first program and the second program for writing the first program in the flash memory is:
When the flash memory is connected to the bus via an expansion bus connector for expanding the bus, the flash memory is writable, and the memory allocation of the flash memory is changed to a second memory space different from the first memory space. And executes the second program by allocating the second program to the first memory space.

In the flash memory writing system of the present invention, the memory allocation of the flash memory is completely switched between the normal start-up and the first program writing. Since both memory spaces are not occupied, the efficiency of memory allocation can be improved.

In the flash memory writing system according to the present invention, the bus width of the memory is smaller than the predetermined bus width, and the memory is connected to the bus via the expansion bus connector when the CPU is reset. If so, the bus width of the memory is set in the CPU as the bus width for accessing the first memory space near the start address to be accessed first.

In the flash memory writing system of the present invention, the number of pins of the expansion bus connector can be reduced by making the bus width of the program writing memory smaller than the predetermined bus width.

[0012]

Next, a flash memory writing system according to an embodiment of the present invention will be described in detail with reference to the drawings. In all the drawings, the components denoted by the same reference numerals all indicate the same components.

(First Embodiment) First, a flash memory writing system according to a first embodiment of the present invention will be described. FIG. 1 is a block diagram illustrating a configuration of a flash memory writing system according to the present embodiment. As shown in FIG. 1, a main board 1 includes a CPU 2, a flash memory 3, an extended memory connector 4, an OR circuit 5,
And an AND circuit 6. The CPU 2 and the flash memory 3 are connected by a 32-bit bus.

The main board 1 includes an extended memory connector 4.
, The flash memory boot substrate 10 can be attached. The flash memory boot board 10 is RO
M12 and M13 are provided. The ROM 13 stores a program written in the flash memory 3 and executed by the CPU 2, that is, a first program.
M12 stores a program for writing a program stored in the ROM 13 into the flash memory 3, that is, a second program. ROM 12, 13
Is a 16-bit bus and a lower 16-bit bus of the 32-bit bus of the main board 1 and an extension bus connector 4
Can be connected via.

Output terminal of CPU 2 / BANK0- / BA
NK2 is an output terminal for switching the memory space accessed by the CPU2. CPU2 has an output terminal / B
The memory space to be accessed is switched by setting only a signal output from any one of the output terminals of ANK0 to / BANK2 to a low level (hereinafter, L). For example, when trying to access the memory space near the start address, that is, the first memory space, the CPU 2 sets the signal output from the output terminal / BANK0 to L. That is, after inputting the reset signal / RES,
The CPU 2 first sets the signal output from the output terminal / BANK0 to L, and accesses the start address. Note that the memory space accessed when the signal output from the output terminal / BANK1 is L is defined as a second memory space.

In the CPU 2, input terminals 16/32
Is high level (hereinafter, H), the bus width when accessing the first memory space is 16 bits, and when L is L, it is 32 bits. When the write protect signal input to the input terminal / WP of the flash memory 3 is L, the flash memory 3 is write-protected (disabled), and when it is H, write is enabled (enable).
Becomes

The signal output from the output terminal / BANK0 of the CPU 2 is supplied to the expansion bus connector 4 and the OR circuit 5.
Is input to The input terminal 16/32 of the CPU 2, the input terminal / WP of the flash memory, and the other input of the OR circuit 5 are connected to each other, are pulled down by a resistor R, and are connected via the extension bus connector 4. A signal can be input. When the main board 1 is started up by connecting the flash boot board 10 to the expansion bus connector 4, the input terminal 16/32 of the CPU 2, the input terminal / WP of the flash memory, and another input of the OR circuit 5 are connected. The input signal becomes H.

The output of the AND circuit 6, which receives the output of the output terminal / BANK1 of the CPU 2 and the output of the OR circuit 5, is supplied as a chip enable signal to the flash memory 3.
Input terminal / CE. The signal output from the output terminal / BANK0 of the CPU 2 is also input as a chip enable signal to the input terminals / CE of the ROMs 12 and 13 of the flash boot board 10 via the expansion bus connector 4. I have.

Here, it is assumed that the main board 1 is started up without connecting the flash boot board 10 to the expansion bus connector 4. When the main board 1 is started by inputting a reset signal to the input terminal / RES of the CPU 2 without connecting the flash boot board 10, the input terminal 16
Since the signal input to / 32 is L, the bus width when accessing the first memory space is set to 32 bits, and the flash memory 3 is write-protected.
The first memory space and the second memory space are allocated to the flash memory 3.

However, when the flash boot board 10 is connected to the expansion bus connector 4 and the main board 1 is started up, it is input to the input terminal 16/32 of the CPU 2 and the input terminal / WP of the flash memory 3. The signal becomes H. Therefore, the bus width when accessing the first memory space is 16 bits, and writing to the flash memory 3 is enabled. Further, when the CPU 2 sets the output terminal / BANK0 to L, the chip enable signal input to the input terminal / CE of the flash memory 3 becomes H, and the ROM 12 of the flash boot board 10
The chip enable signal input to the 13 input terminals / CE becomes L. When trying to access the flash memory 3, the CPU 2 sets the signal output from the output terminal / BANK1 to L. Note that the CPU 2 accesses the second memory space for three times separately from the first memory space.
Two-bit access can be used.

With the above-described configuration, when the main board 1 is started up by connecting the flash boot board 10 to the expansion bus connector 4, the CPU 2 executes the second program stored in the ROM 12 with 16-bit data. Then, the first program stored in the ROM 13 is written into the flash memory 3.

As described above, in the flash memory writing system of the present embodiment, when writing the first program into the flash memory 3, the flash memory 3 is stored in a different memory from the first memory space near the start address. Second
And a second program for writing the first program to the flash memory 3 is allocated to the first memory space. By doing so, the second program can be executed after the CPU 2 is reset, and the first program can be written to the flash memory 3. Therefore, in the flash memory writing system according to the present embodiment, the first program can be written in the flash memory 3 even if the flash memory 3 is assigned to the start address.

In the flash memory writing system of the present embodiment, the bus width of the flash boot board 10 is 16 bits, which is smaller than the bus width of the main board 1, so that the number of pins of the extension bus connector 4 is reduced. It can be reduced.

(Second Embodiment) Next, a flash memory writing system according to a second embodiment of the present invention will be described. FIG. 2 is a block diagram illustrating a configuration of the flash memory writing system according to the present embodiment.

As shown in FIG. 2, the flash memory writing system of the present embodiment differs from the flash memory writing system of the first embodiment in that a main substrate 21 is provided instead of the main substrate 1. I have.
In the flash memory writing system according to the present embodiment, the memory space accessed when the signal output from the output terminal / BANK2 is set to L is the second memory space.

The main board 21 is newly provided with the logic circuit 7, and a signal output from the output terminal / BANK 2 is an input of the logic circuit 7. Output terminal / BANK2
Are also output to the expansion bus connector 4. Another input signal of the logic circuit 7 is the CPU 2
, The input terminal 16/32 of the flash memory 3, and the other input of the OR circuit 5. The AND circuit 6 receives the output of the OR circuit 5 and the output of the logic circuit 7 as inputs.

By doing so, in the flash memory writing system of the present embodiment, when the flash boot board 10 is connected to the expansion bus connector 4 and the main board 21 is started, the first memory space is The flash memory is allocated to the second memory space, but when the main board 21 is started without connecting anything to the extension bus connector 4, the flash memory is allocated to the first memory space. Only the first memory space is provided.

In the flash memory writing system of this embodiment, the memory allocation of the flash memory 3 is
Since the operation is completely switched between the normal start-up and the first program writing, the flash memory 3 does not occupy both the first memory space and the second memory space. Can be planned.

As shown in FIG. 2, an option board 11 can be connected to the expansion bus connector 4 instead of the flash boot board 10. When the option board 11 is connected to the expansion bus connector 4 and the main board 21 is started up, the flash memory 3 is allocated to the first memory space, and the second memory space is
The RAM 14 and the I / O 15 of the option board 11 are allocated.

[0030]

As described above, in the flash memory writing system of the present invention, when writing a program to the flash memory, the flash memory is stored in the second memory separate from the first memory space near the start address. A second program for writing the first program to the flash memory is also allocated to the first memory space. With this configuration, the second program can be executed after the CPU is reset, and the first program can be written to the flash memory. Therefore, in the flash memory writing system of the present invention, a program can be written to the flash memory even if the flash memory is assigned to the start address.

In the flash memory writing system according to the present invention, the number of pins of the expansion bus connector can be reduced by making the bus width of the program writing memory smaller than a predetermined bus width.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a flash memory writing system according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a flash memory writing system according to a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main board 2 CPU 3 Flash memory 4 Expansion bus connector 5 OR circuit 6 AND circuit 7 Logic circuit 10 Flash boot board 11 Option board 12, 13 ROM 14 RAM 15 I / O

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B025 AD00 AD04 AE00 5B060 BB09 MM02 5B076 EB03

Claims (3)

[Claims] At reset, a CPU for setting a bus width for accessing a first memory space near a start address to be accessed first, and a bus having a predetermined width, the CPU being connected to the CPU, A flash memory allocated to the memory space of the above, and a flash memory writing system for writing a first program executed by the CPU to the flash memory, wherein the flash memory is the first memory space. Allocating to another second memory space, upon resetting the CPU, the first program,
When a memory for storing the second program for writing the first program to the flash memory is connected to the bus via an expansion bus connector for expanding the bus, the flash memory , And the second program is allocated to the first memory space, and the second program is executed. 2. A reset method comprising: a CPU having a bus width set for accessing a first memory space near a start address to be accessed first at the time of reset; and a bus having a predetermined width connected to the CPU; A flash memory allocated to the memory space of the flash memory, and a flash memory writing system for writing a first program to be executed by the CPU to the flash memory, wherein the first program and ,
When a memory for storing the second program for writing the first program to the flash memory is connected to the bus via an expansion bus connector for expanding the bus, the flash memory , The memory allocation of the flash memory is changed to a second memory space different from the first memory space, and the second program is allocated to the first memory space. Flash memory writing system that executes a program. 3. The bus width of the memory is smaller than the predetermined bus width, and when the memory is connected to the bus via the expansion bus connector at the time of resetting the CPU, the memory is accessed first. 3. The flash memory writing system according to claim 1, wherein a bus width of the memory is set in the CPU as a bus width when accessing a first memory space near a start address to be executed. 4.