JP2010266987A - Cpu address map switching - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of switching a CPU address map loaded on a computer system having a plurality of printed boards and configured by connecting each of the print boards through a bus signal using a bus connector, which reduces the size and cost and increases productivity without mounting an unnecessary ROM or connector for connecting to a dedicated tool that writes a system program into a flash memory. <P>SOLUTION: A CPU address MAP switching method is provided with: a CPU that starts with an address 0 (0H); a flash memory (R) connected to the data bus of the CPU, and installed outside the CPU; and a detachable ROM module with a ROM mounted thereon for storing a program to write a system program in the flash memory. The CPU address MAP switching method is configured to change an address map seen from the CPU between in a normal state or in a boot operation, execute the boot program of the ROM during boot, include the method of writing the system program in the flash memory, and remove the ROM module after the end of writing the system program in the flash memory. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for switching a CPU address map of a flash memory mounted on a computer system having a plurality of printed boards and each printed board connected by a bus connector through a bus signal.

  Conventionally, as the memory for storing the system program of the embedded control device, EPROM that has to be erased by irradiating ultraviolet rays and electrically erasable EEPROM have been the mainstream. Flash memories that can be electrically written and erased are used and are becoming mainstream.

  The flash memory can be electrically written and erased, and is a small SOP (Small Out-line Package) or TSOP (Thin SOP) package with a lot of very thin pins, so it is mounted on a computer system. In many cases, it is necessary to write a system program after implementation.

  Conventionally, when writing to the flash memory, a ROM (Read Only Memory) that stores the program for writing the system program to the flash memory must be mounted in addition to the flash memory or written to the flash memory using a dedicated tool. It was.

JP-A-6-222924

  In the conventional method described above, a normally unnecessary ROM is mounted, or a normally unnecessary connector that is connected to a dedicated tool for writing a system program in the flash memory is mounted, which increases the cost.

  It is an object of the present invention to provide a flash memory mounted on a computer system having a plurality of printed boards without connecting normally unnecessary EPROMs and connectors, and connecting each printed board with a bus connector through a bus signal. The object is to provide a method for switching a CPU address map in which a system program can be written.

  In order to achieve the above object, a CPU starting from address 0 (0H) and a flash memory provided outside the CPU connected to the data bus of the CPU can be attached and detached, and a system program is stored in the flash memory. A ROM module with a ROM storing a program for writing, and changing the address map seen from the CPU at the normal time and at the time of booting to write the system program, the boot program of the ROM is executed at the time of booting, A method of writing a system program to a flash memory is provided, and the ROM module is removed after the writing is completed.

  According to the present invention, there is no need to mount a normally unnecessary ROM or a normally unnecessary connector for connecting to a dedicated tool for writing a system program in the flash memory, and it is possible to reduce the size, cost and productivity. Can be improved.

Embodiment 1 block diagram of CPU address map switching according to the present invention Embodiment 2 block diagram of CPU address map switching according to the present invention

  Examples of the present invention will be described below.

  A first embodiment of a flash memory writing method by CPU address map switching according to the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing Embodiment 1 according to the present invention. The computer system shown in Fig. 1 has multiple printed boards, each of which is connected via a bus signal through a bus connector. In addition to the printed board with a CPU, a removable ROM module for booting Is shown.

  The removable ROM module is equipped with a ROM that stores a program for writing a system program in the flash memory. It is installed when the system program is not written in the flash memory or when the system program is modified. It is usually removed. The ROM module may be provided with a valid / invalid switch, etc., and may remain attached during normal operation.

  CPU 1 is connected to address bus 2 and data bus 3, and 26-bit addresses A0 to A25 (A25 is the most significant bit), 32-bit data D0 to D31 (D31 is the most significant bit), and LOW enables writing This is a CPU that inputs / outputs the read signal RD, which enables read when the write signal WE, becomes LOW, and the reset signal RESET 100, where reset becomes valid when LOW, and starts from address 0H when the reset signal RESET becomes HIGH.

  The flash memory 4 is selected by the chip enable signal CE which becomes valid at LOW decoded by the memory map switching logic circuit unit 5 when the lower 22 bits of the address A0 to A21 of the CPU 1 are input from the address bus 2 and is selected from the CPU 1 When the read signal RD is LOW, it is output to the data bus 3.

  In addition, when the write signal WE from CPU 1 is LOW, data is input from data bus 3 and written. The memory map switching logic unit 5 selects the memory map at the time of booting, and all the selectors 7 to 9 are switched to the boot side. During normal operation, the normal memory map is selected and all selectors 7 to 9 are switched to the normal operation side. The ROM module 10 is output at the time of booting, and the 3-state circuit 12 outputs HIGH indicating that the ROM module is installed on the data bus 3 that is pulled down to LOW when the RESET signal is LOW. The latch circuit 6 of the switching logic unit 5 latches the signal that the ROM module is installed.

  Next, operations at the time of booting and rewriting the system program of the computer system of FIG. 1 will be described. It is assumed that the flash memory 4 is not written at boot time and the old system program is written at system program rewrite. The operator first inserts the ROM module 10 into the bus connector of the computer system and then turns on the power.

  When the power supply rises and the reset signal RESET 100 becomes LOW, which is valid, HIGH is output from the 3-state circuit 12 of the ROM module 10, which means that the ROM module 10 is installed. It is transmitted to the circuit unit 5.

  The memory map switching logic circuit unit 5 latches HIGH, which means that the ROM module 10 is mounted, in the latch circuit 6 inside, and switches the selectors 7 to 9 to the boot side.

  A chip in which the memory map at boot is selected when selector 7 switches to the boot side, and ROM 11 of ROM module 10 is enabled when the address from CPU 1 is 0H to 3FFFFFH when selector 9 is switched to the boot side When the enable signal CE is output and the selector 8 is switched to the boot side, the boot operation preparation is completed in which the chip enable signal CE for enabling the flash memory 4 with the address from the CPU 1 of 400000H to 7FFFFFH is output.

  When power is turned on and reset signal RESET 10 becomes HIGH after several tens of milliseconds, CPU 1 outputs 0H to address bus 2 and the computer system starts. At boot time, since address 0H is the area of ROM 11, ROM 11 is selected, and CPU 1 reads the data at address 0H of ROM 11 and starts writing the system program to flash memory 4. Since the address of the flash memory 4 is 400000H to 7FFFFFH, the system program is written in that area.

  In the computer system shown in Fig. 1, the method of transmitting HIGH, which means that the ROM module 10 is installed, to the memory map switching logic circuit unit 5 through the data bus 3, was shown. There is also a method in which a memory map switching signal is provided in the bus connector and transmitted directly without using the three-state circuit 12.

  Next, the normal operation of the computer system of FIG. 1 will be described. The operator writes the system program in the flash memory 4 by the above method, then turns off the power, removes the ROM module 10 from the computer system, and turns on the power.

  When the power is turned on and the reset signal 100 becomes valid LOW, the ROM module is not installed, so it means that the ROM map 10 is not installed in the memory map switching logic circuit 5 internal latch circuit 6. Latch LOW and switch selectors 7 to 9 to the normal side.

  Chip enable signal CE that selects the normal memory map when selector 7 switches to the normal side, and enables the flash memory 4 when the address from CPU 1 is 0H to 3FFFFFH when selector 8 switches to the normal side Is ready to be output. When power is turned on and reset signal RESET 10 becomes HIGH after several tens of milliseconds, CPU 1 outputs 0H to address bus 2 and the computer system starts.

  A second embodiment of the flash memory writing method by CPU address map switching according to the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing a second embodiment according to the present invention. The difference from the first embodiment is that the information that the ROM module 10 is installed is output from the three-state circuit 12 in the first embodiment, and the signal is latched by the latch circuit 6 of the memory map switching logic unit 5 On the other hand, in the second embodiment, the serial communication circuit is changed to have more versatility than the first embodiment.

  If more information can be transmitted using serial communication, a flash memory other than the computer system can be attached to the bus connector for writing.

  Since only the serial communication circuit unit is changed from the first embodiment, only the serial communication circuit unit will be described below. Operations at the time of booting and rewriting the system program of the computer system of FIG. 2 will be described.

  Conditions are the same as in Example 1. When the power is turned on, the power is turned on, and the reset signal RESET 100 becomes LOW, which is valid, the serial communication circuit B 14 of the ROM module 10 outputs serial data meaning that the ROM module 10 is installed, and the data bus 3 is sent to the memory map switching logic circuit unit 5.

  Memory map switching logic circuit 5 Internal serial communication circuit A recognizes that ROM module 10 is installed, switches selectors 7 to 9 to the boot side, and simultaneously notifies reception completion to serial communication circuit B 14 of ROM module 10 To complete the boot operation preparation. Since the reset signal RESET 10 becomes HIGH after the power is turned on after several tens of milliseconds, the description is omitted because it is exactly the same as in the first embodiment.

1 CPU
2 Address bus
3 Data bus
4 Flash memory
5 Memory map switching logic circuit
6 Latch circuit
7-9 selector
10 ROM module
11 ROM
12 3-state circuit
13 Serial communication circuit A
14 Serial communication circuit B
100 RESET signal

Claims (3)

A CPU that starts from address 0 in the embedded controller;
A flash memory (registered trademark) provided outside the CPU connected to the data bus of the CPU;
A memory map switching logic circuit unit having a function of changing an address map viewed from the CPU;
A detachable ROM module with a ROM that stores a program for writing system programs to flash memory,
The address map seen from the CPU is changed during normal and boot times, and the boot program of the ROM is executed at boot time, and the system program is written to the flash memory. Characteristic CPU address map switching method.
In the memory map switching logic circuit section,
A latch circuit or serial communication circuit for switching between an address map at normal time and an address map at boot time;
2. The CPU address map switching method according to claim 1, further comprising a selector.
  2. The CPU address map switching method according to claim 1, wherein the ROM module includes a three-state circuit or a serial communication circuit that outputs information indicating that the ROM module is mounted.

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