JP2011013949A - Data processing apparatus, data processing method and data processing program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively use a conventionally unused portion in an expansion memory when the expansion memory having a bus width larger than a bus width of a resident memory is connected to a CPU connected with the resident memory.SOLUTION: In an image processor, a bus width when accessing a memory can be performed with a changeover between a 32-bit bus width and a 64-bit bus width. When a DMM (Dual Inline Memory Module) having the 64-bit bus width is connected to the CPU connected with the resident memory having the 32-bit bus width (S101: YES), the image processor compares memory capacity capable of being accessed by the CPU by use of the 32-bit bus width and memory capacity capable of being accessed by the CPU by use of the 64-bit bus width (S104), the image processor determines to use the bus width wherein the memory capacity capable of being accessed by the CPU is large of the 32-bit bus width and the 64-bit bus width based on the result of the comparison (S107, S105).

Description

  The present invention relates to a data processing device, a data processing method, and a data processing program. The present invention particularly relates to a data processing device, a data processing method, and a data processing program for controlling memory access when a memory is added.

  There is a CPU that can switch the bus width when accessing a memory within the range of the maximum bus width (see Patent Document 1).

  For example, in a circuit including a CPU and a memory that can switch the bus width within the range of the maximum bus width of 64 bits, when a memory with the same capacity is mounted, the number of memories decreases as the memory capacity increases. As a result of the configuration of the elements, the bus width for accessing the memory must be narrowed. This is advantageous in terms of memory mounting space, power consumption, and cost because a memory can be configured with a minimum number of memory elements. On the other hand, in terms of performance, the following restrictions arise. .

  For example, when configuring a memory capacity of 256 MB (M bytes), it is configured with four 512 Mbit memory elements (bus width 16 bits), and the CPU can access the memory using a 64-bit bus width. . However, when a memory device with a capacity of 1 Gbit (bus width of 16 bits) becomes mainstream with an increase in the capacity of the memory, when a 256 MB memory capacity is configured, a resident memory is not configured with two 1 Gbit memory devices. I do not get. Therefore, the bus width for accessing the memory is a 32-bit bus width corresponding to two memory elements (bus width 16 bits). For this reason, it becomes impossible to match the maximum bus width (64 bits) of the CPU, and the data transfer speed is halved compared with the case of accessing with the maximum bus width.

  When expanding the memory in such a situation, a commercially available DIMM (Dual Inline Memory Module) is generally used.

  However, DIMMs having a 64-bit bus width are currently mainstream, and the DIMM bus width is larger than the 32-bit bus width of a resident memory mounted in advance. Therefore, when the resident memory and the DIMM as the additional memory are accessed in accordance with the smaller bus width for easy access, the memory corresponding to the remaining 32-bit width in the DIMM (64-bit bus width). There was a problem that the part could not be used.

  On the other hand, Patent Document 1 discloses a technology in which one or a plurality of memory elements having a 16-bit bus width can be connected to a CPU that can be switched between a 32-bit bus width and a 16-bit bus width during operation. Has been proposed. However, the technique described in Patent Document 1 is merely a technique for making it possible to add a memory element having a bus width smaller than the maximum bus width and reducing the area occupied by the memory. That is, the technique described in Patent Document 1 does not provide a technique for dealing with a situation in which an unused portion of a DIMM occurs when a DIMM is added to the resident memory.

JP-A-10-124386

  The present invention has been made in view of the above-described problems, and an object of the present invention is to connect an additional memory having a bus width larger than the bus width of the resident memory to the CPU to which the resident memory is connected. In this case, it is an object to provide a data processing device, a data processing method, and a data processing program capable of effectively utilizing a conventionally unused portion in an expansion memory.

  The above object of the present invention is achieved by the following means.

  (1) A CPU capable of switching a bus width for accessing a memory between a first bus width and a second bus width larger than the first bus width, and the first bus connected to the CPU When a first memory having a width and a second memory having a second bus width are connected to the CPU, a memory capacity accessible to the CPU using the first bus width and the memory Comparing means for comparing the memory capacity accessible to the CPU using a second bus width, and the first bus width and the second bus width based on the result of comparison by the comparing means And a determining means for determining to use a bus width having a larger memory capacity accessible to the CPU.

  (2) When using the first bus width, the CPU uses the first bus width to access the first memory and the second memory, and uses the second bus width. In this case, the CPU accesses the second memory using the second bus width. The data processing apparatus according to (1), wherein the CPU accesses the second memory.

  (3) Determination means for determining whether or not the access speed of the second memory is an access speed that can be set by the CPU when the determination means determines to use the second bus width. When the determination means determines that the access speed of the second memory is an access speed that can be set by the CPU, the CPU sets the access speed of the second memory to the second memory. The data processing apparatus according to (1) or (2), further comprising setting means for setting the speed for access.

  (4) The data processing apparatus according to any one of (1) to (3), wherein the second bus width is twice the first bus width.

  (5) The data processing apparatus according to any one of (1) to (4), wherein the data processing apparatus is an image processing apparatus that executes image processing.

  (6) A first memory having a first bus width which can be switched between a first bus width and a second bus width larger than the first bus width when accessing the memory. When a second memory having the second bus width is connected to the CPU to which the CPU is connected, the memory capacity accessible by the CPU using the first bus width and the second memory Comparing the memory capacity accessible to the CPU using the bus width, and the first bus width and the second bus based on the result of the comparison in the step (a) And (b) deciding to use a bus width which has a larger memory capacity accessible to the CPU among the widths.

  (7) When using the first bus width, the CPU uses the first bus width to access the first memory and the second memory, and uses the second bus width. In this case, the data processing method according to (6), wherein the CPU accesses the second memory using the second bus width.

  (8) If it is determined in step (b) that the second bus width is to be used, it is determined whether the access speed of the second memory is an access speed that can be set by the CPU. In step (c) and step (c), when it is determined that the access speed of the second memory is an access speed that can be set by the CPU, the CPU determines the access speed of the second memory. The data processing method according to (6) or (7), further comprising a step (d) of setting as a speed for accessing the second memory.

  (9) The data processing method according to any one of (6) to (8), wherein the second bus width is twice the first bus width.

  (10) The data processing method according to any one of (6) to (9), wherein the data processing method is used in an image processing apparatus that executes image processing.

  (11) A first memory having a first bus width which can be switched between a first bus width and a second bus width larger than the first bus width when accessing the memory. When a second memory having the second bus width is connected to the CPU to which the CPU is connected, the memory capacity accessible by the CPU using the first bus width and the second memory The procedure (a) for comparing the memory capacity accessible to the CPU using the bus width, and the first bus width and the second bus based on the comparison result in the procedure (a) A data processing program for causing a computer to execute data processing having a procedure (b) for determining to use a bus width having a larger memory capacity accessible to the CPU.

  (12) When using the first bus width, the CPU uses the first bus width to access the first memory and the second memory, and uses the second bus width. In this case, the data processing program according to (11), wherein the CPU accesses the second memory using the second bus width.

  (13) If the data processing is determined to use the second bus width in the procedure (b), is the access speed of the second memory an access speed that can be set by the CPU? A step (c) for determining whether or not the access speed of the second memory in the step (c) is an access speed that can be set by the CPU. The data processing program according to (11) or (12), further comprising: a step (d) for setting the CPU as a speed when the CPU accesses the second memory.

  (14) The data processing program according to any one of (11) to (13), wherein the second bus width is twice the first bus width.

  (15) The data processing program according to any one of (11) to (14), wherein the computer is an image processing apparatus that executes image processing.

  (16) A computer-readable recording medium on which the data processing program according to any one of (11) to (15) is recorded.

  According to the present invention, when an additional memory as a second memory having a bus width larger than the bus width of the resident memory is connected to the CPU to which the resident memory as the first memory is connected, It is possible to effectively utilize a conventionally unused portion in the memory. That is, it is possible to effectively use memory resources that have been discarded without being used.

1 is a block diagram illustrating an overall configuration of an image forming system to which an image processing apparatus according to an embodiment of the present invention is applied. FIG. 2 is a block diagram illustrating a configuration of a main part of a printer controller. It is a figure which shows the detailed structure of RAM with CPU. 6 is a flowchart illustrating a control procedure related to memory access when a memory is added in the printer controller.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing the overall configuration of an image forming system to which an image processing apparatus according to an embodiment of the present invention is applied.

  The image forming system according to the present embodiment includes a PC 1 as a client device that generates a print job in accordance with a user instruction, and an MFP 2 as an image forming device that executes printing based on a print job received from the PC 1. These are connected via a network 5 so that they can communicate with each other. Note that the PC 1 and the MFP 2 may be directly connected (locally connected) between devices without going through the network 5.

  Here, the MFP 2 is based on the printer controller 3 as an image processing apparatus that executes various image processing such as rasterization processing on the print job received from the PC 1, and the image processed image data transferred from the printer controller 3. And a printer engine 4 as a printing apparatus that executes printing. However, the printer controller 3 as the image processing apparatus may be a single apparatus independent of the MFP 2 instead of the apparatus included in the MFP 2 as in the present embodiment.

  FIG. 2 is a block diagram illustrating a configuration of a main part of the printer controller 3.

  As shown in FIG. 2, the printer controller 3 stores various programs and data such as a CPU 31 for controlling the entire apparatus and various arithmetic processes, a RAM 32 for temporarily storing programs and data as a work area, and a BOOT program. It has a ROM 33 that is a nonvolatile memory for storing, a hard disk 39 as an external storage device for storing various programs and data, and a printer engine interface 34 for communicating with the printer engine 4.

  The printer controller 3 has a LAN connector 36 for physically connecting to the network 5. The printer controller 3 can communicate with the PC 1 on the network 5 via the PHY interface 35. For example, the printer controller 3 receives a print job from the PC 1.

  The printer controller 3 includes a USB device connector 37 for physically connecting to a USB device through an external serial bus, and a USB host connector 38 for physically connecting to a USB host through an external serial bus. is doing. Examples of the USB device include an external memory, a maintenance device, and a keyboard. Moreover, a PC etc. are mentioned as a USB host.

  The CPU 31 can switch the bus width for accessing the memory within the range of the maximum bus width (here, 64 bits). In the present embodiment, the CPU 31 can switch the bus width for accessing the memory between a 32-bit bus width (32-bit width) and a 64-bit bus width (64-bit width).

  The RAM 32 is composed of a memory element called DDR2 of the DRAM, and is used as a work area for loading a program from the ROM 33 and the hard disk 39, storing received data, and image processing.

  FIG. 3 is a diagram showing a detailed configuration of the RAM 32 together with the CPU 31.

  The RAM 32 has a resident memory 321 that is preinstalled in the printer controller 3 as a standard. In the present embodiment, the resident memory 321 includes two memory elements (bus width 16 bits) 3211 and 3212. A total of 32 data pins of both memory elements 3211 and 3212 are connected to the data pins D0 to D31 of the CPU 31.

  In addition, the printer controller 3 includes a memory slot 323 into which a DIMM 322 is inserted on a motherboard (not shown) for adding memory.

  The DIMM 322 includes four memory elements (bus width 16 bits) 3221 to 3224. By inserting the DIMM 322 into the memory slot 323, a total of 64 data pins of the four memory elements 3221 to 3224 are connected to the data pins D0 to D63 of the CPU 31 as shown in FIG. Yes.

  The DIMM 322 also includes an SPD (Serial Presence Detection) 3225. The SPD 3225 stores information such as the memory capacity and access speed of the DIMM 322. By inserting the DIMM 322 into the memory slot 323, the SPD 3225 is connected to a pin (I2C) of the CPU 31.

  Next, with reference to FIG. 4, a description will be given of control related to memory access when the memory in the printer controller 3 is expanded. The algorithm shown in the flowchart of FIG. 4 is stored as a program in a storage unit such as the ROM 33 of the printer controller 3, and the program is read onto the RAM 32 by the CPU 31 and executed.

  When the power is turned on, the CPU 31 first determines whether or not the DIMM 322 is mounted on the printer controller 3, that is, whether or not the DIMM 322 is connected to the CPU 31 (S101). Specifically, the CPU 31 determines whether or not the SPD 3225 provided on the DIMM 322 can be accessed.

  If it is determined that the DIMM 322 is not installed (S101: NO), the CPU 31 determines to access the resident memory 321 using a 32-bit bus width (S102).

  Subsequently, in step S103, the CPU 31 sets the access speed of the resident memory 321 as the speed for accessing the memory.

  On the other hand, if it is determined that the DIMM 322 is installed (S101: YES), the memory capacity of the expanded DIMM 322 (hereinafter also referred to as “DIMM capacity”) is the memory capacity of the resident memory 321 (hereinafter referred to as “resident capacity”). It is determined whether or not it is twice or more (also referred to as “)” (S104). Here, the DIMM capacity is acquired when the CPU 31 accesses the SPD 3225 provided on the DIMM 322.

  In step S104, the capacity of the memory accessible by the CPU 31 using the 32-bit bus width is compared with the capacity of the memory accessible by the CPU 31 using the 64-bit bus width. It is determined whether or not the capacity of the memory accessible by the CPU 31 is larger using the width.

  When it is determined that the DIMM capacity is less than twice the resident capacity (S104: NO), the CPU 31 determines to access the resident memory 321 and the DIMM 322 using the 32-bit bus width (S105). In this case, DIMM capacity <(DIMM capacity / 2 + resident capacity) is established. That is, the memory capacity (DIMM capacity / 2 + resident capacity) accessible to the CPU 31 using the 32-bit bus width is larger than the memory capacity (DIMM) accessible to the CPU 31 using the 64-bit bus width. Capacity).

  Subsequently, in step S106, the CPU 31 sets the access speed of the resident memory 321 as the speed for accessing the memory.

  On the other hand, when it is determined that the memory capacity of the DIMM 322 is more than twice the memory capacity of the resident memory 321 (S104: YES), the CPU 31 determines to access the DIMM 322 using a 64-bit bus width. (S107). In this case, DIMM capacity ≧ (DIMM capacity / 2 + resident capacity) is established. In other words, the memory capacity accessible to the CPU 31 using the 64-bit bus width (DIMM capacity) is larger than the memory capacity accessible to the CPU 31 using the 32-bit bus width (DIMM capacity / 2 + resident). Capacity).

  More specifically, for example, a case where a DIMM (64-bit width) is added to a resident memory (capacity 256 MB, 32-bit width) is considered. If a DIMM with a capacity (512MB or more) more than twice the resident capacity (256MB) is added, DIMM capacity ≥ (DIMM capacity / 2 + resident capacity) is established. Therefore, it is better to use a DIMM with a 64-bit bus width. Therefore, the memory capacity accessible to the CPU 31 is larger than that using a resident memory and DIMM with a bus width of 32 bits. Moreover, when the resident memory and DIMM are used with a bus width of 32 bits and the access clock frequency is 267 MHz, the transfer speed is 267 × 2 × 32/8 = 2136 MB / S = 2.136 GB / On the other hand, when a DIMM is used with a 64-bit bus width, it can be transferred with a 64-bit width, which is doubled to 4.272 GB / S. Therefore, when a DIMM having a capacity of twice or more the resident capacity is added, it is advantageous to use the DIMM with a 64-bit bus width.

  On the other hand, if a DIMM with a capacity less than twice the resident capacity (256 MB) (less than 512 MB) is added, DIMM capacity <(DIMM capacity / 2 + resident capacity) is satisfied, so the resident memory and DIMM with a 32-bit bus width. The memory capacity that can be accessed by the CPU 31 is larger when the memory card is used than when the DIMM is used with a 64-bit bus width. In this case, it is more advantageous to use a resident memory and a DIMM with a 32-bit bus width in order to increase the memory capacity because there is an intention to increase the memory capacity.

  In step S108, it is determined whether or not the access speed of the DIMM 322 is an access speed that can be set by the CPU 31. Here, the access speed of the DIMM 322 is acquired when the CPU 31 accesses the SPD 3225 provided on the DIMM 322.

  When it is determined that the CPU 31 can set the access speed of the DIMM 322 (S108: YES), the CPU 31 sets the access speed of the DIMM 322 as the access speed to the memory (S109).

  In other words, if it is within the access speed that has been confirmed to be set in advance, it is possible to transfer data at a higher speed by using the increased access speed of the added DIMM 322 specification.

  On the other hand, when it is determined that the CPU 31 cannot set the access speed of the DIMM 322 (S108: NO), the CPU 31 selects the access speed closest to the access speed of the DIMM 322 from the settable access speeds. (S110).

  As described above, in this embodiment, the bus width for accessing the memory can be switched between the 32-bit bus width and the 64-bit bus width, and the CPU 31 connected to the resident memory 321 having the 32-bit bus width is connected. On the other hand, when a DIMM 322 having a 64-bit bus width is connected, the printer controller 3 uses the memory capacity accessible by the CPU 31 using the 32-bit bus width and the CPU 31 using the 64-bit bus width. Comparing with the accessible memory capacity, based on the result of the comparison, of the 32-bit bus width and 64-bit bus width, the bus width with the larger memory capacity accessible by the CPU 31 is used. decide.

  Therefore, according to the present embodiment, when an expansion memory having a bus width larger than that of the resident memory is connected to the CPU to which the resident memory is connected, the previously unused portion of the expansion memory is validated. It becomes possible to utilize it. That is, it is possible to effectively use memory resources that have been discarded without being used.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims.

  For example, although the MFP is used as the image forming apparatus in the above embodiment, other image forming apparatuses such as a printer and a copying machine may be used in the present invention.

  In the above embodiment, the case where the resident memory 321 has a bus width of 32 bits and the DIMM 322 has a bus width of 64 bits has been described. However, the present invention is not limited to this, and the bus width of the DIMM 322 is resident. The present invention can be easily applied to other cases where the bus width of the memory 321 is twice. Furthermore, the present invention can be applied to various cases where the bus width of the DIMM 322 is larger than the bus width of the resident memory 321.

  In the above embodiment, the case where the present invention is applied to the printer controller 3 as an image processing apparatus (data processing apparatus) that executes image processing has been described. The printer controller 3 is preferable for applying the present invention because it requires a large amount of data processing when executing various image processing such as rasterization processing, but the present invention is not limited to this. However, the present invention can be applied to other data processing apparatuses.

  The means and method for performing various processes in the image processing apparatus according to the present embodiment can be realized by either a dedicated hardware circuit or a programmed computer. The program may be provided by a computer-readable recording medium such as a flexible disk or a CD-ROM, or may be provided online via a network such as the Internet. In this case, the program recorded on the computer-readable recording medium is usually transferred to and stored in a storage unit such as a hard disk. The program may be provided as a single application software, or may be incorporated into the software of the apparatus as a function of the image processing apparatus.

1 PC,
2 MFP,
3 Printer controller (image processing device),
31 CPU,
32 RAM,
321 resident memory (first memory),
322 DIMM (second memory),
33 ROM,
4 Printer engine,
5 Network.

Claims (16)

A CPU capable of switching a bus width when accessing a memory between a first bus width and a second bus width larger than the first bus width;
A first memory connected to the CPU and having the first bus width;
When a second memory having the second bus width is connected to the CPU, the memory capacity accessible by the CPU using the first bus width and the second bus width are used. A comparing means for comparing the memory capacity accessible by the CPU;
Based on the result of the comparison by the comparison means, it is determined to use the bus width of the first bus width and the second bus width, which has a larger memory capacity accessible to the CPU. A determination means;
A data processing apparatus comprising:   When using the first bus width, the CPU accesses the first memory and the second memory using the first bus width, and uses the second bus width. The data processing apparatus according to claim 1, wherein the CPU accesses the second memory using the second bus width. A determination unit that determines whether the access speed of the second memory is an access speed that can be set by the CPU when the determination unit determines to use the second bus width;
When the determination means determines that the access speed of the second memory is an access speed that can be set by the CPU, the CPU accesses the second memory as the access speed of the second memory. Setting means to set as the speed at the time,
The data processing apparatus according to claim 1, further comprising:   The data processing apparatus according to claim 1, wherein the second bus width is twice the first bus width.   The data processing apparatus according to claim 1, wherein the data processing apparatus is an image processing apparatus that executes image processing. A bus width for accessing the memory can be switched between a first bus width and a second bus width larger than the first bus width, and a first memory having the first bus width is connected. When a second memory having the second bus width is connected to the CPU, the memory capacity accessible by the CPU using the first bus width and the second bus width are set. Using (a) comparing the memory capacity that is accessible to the CPU;
Based on the result of the comparison in the step (a), the bus width of the first bus width and the second bus width that increases the memory capacity accessible by the CPU is used. Determining step (b);
A data processing method characterized by comprising:   When using the first bus width, the CPU accesses the first memory and the second memory using the first bus width, and uses the second bus width. The data processing method according to claim 6, wherein the CPU accesses the second memory using the second bus width. If it is determined in step (b) that the second bus width is to be used, the step of determining whether or not the access speed of the second memory is an access speed that can be set by the CPU (c) )When,
If it is determined in step (c) that the access speed of the second memory is an access speed that can be set by the CPU, the CPU sets the access speed of the second memory to the second memory. A step (d) of setting as a speed for accessing;
The data processing method according to claim 6 or 7, further comprising:   The data processing method according to claim 6, wherein the second bus width is twice the first bus width.   The data processing method according to claim 6, wherein the data processing method is used in an image processing apparatus that executes image processing. A bus width for accessing the memory can be switched between a first bus width and a second bus width larger than the first bus width, and a first memory having the first bus width is connected. When a second memory having the second bus width is connected to the CPU, the memory capacity accessible by the CPU using the first bus width and the second bus width are set. A procedure (a) for using and comparing the memory capacity accessible by the CPU;
Based on the result of the comparison in the step (a), of the first bus width and the second bus width, the bus width with the larger memory capacity accessible by the CPU is used. Determining procedure (b);
A data processing program for causing a computer to execute data processing having   When using the first bus width, the CPU accesses the first memory and the second memory using the first bus width, and uses the second bus width. The data processing program according to claim 11, wherein the CPU accesses the second memory using the second bus width. The data processing is
If it is determined in step (b) that the second bus width is to be used, a step (c) for determining whether the access speed of the second memory is an access speed that can be set by the CPU (c) )When,
When it is determined in step (c) that the access speed of the second memory is an access speed that can be set by the CPU, the access speed of the second memory is set to the second memory. Step (d) to set as speed for access,
The data processing program according to claim 11, further comprising:   The data processing program according to claim 11, wherein the second bus width is twice the first bus width.   The data processing program according to claim 11, wherein the computer is an image processing apparatus that executes image processing.   The computer-readable recording medium which recorded the data processing program of any one of Claims 11-15.

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