CN117524288A - Flash memory device - Google Patents

Abstract

The present disclosure relates to flash memory devices. Flash memory devices include flash memory having an array of non-volatile memory cells and volatile memory. The flash memory interface is disposed external to the flash memory, and the first communication bus couples the flash memory interface to the array of memory cells. The second communication bus couples the flash memory interface to the volatile memory.

Description

Flash memory device

Cross Reference to Related Applications

The present application claims priority from french application No.2208087 filed on 4, 8, 2022, which is incorporated herein by reference.

Technical Field

The present disclosure relates generally to devices including flash memories and methods of operating the same.

Background

Flash memory is a mass memory with a rewritable semiconductor. They typically include an array of memory cells. Flash memory can be implemented in a number of devices such as, inter alia, memory cards, computers, smart phones or vehicles. Flash memory includes operating programs that may need to be modified or benefit from modification.

Disclosure of Invention

It is necessary or desirable to have a device that includes one or more flash memories, the operating program of which can be modified.

The present disclosure provides one or more embodiments that overcome all or part of the disadvantages of known flash memories.

In at least one embodiment, a flash memory device is provided that includes a flash memory including an array of non-volatile memory cells and a volatile memory. The flash memory interface is disposed external to the flash memory. The first communication bus couples the flash memory interface to the array of non-volatile memory cells. The second communication bus couples the flash memory interface to the volatile memory.

In some embodiments, the flash memory device includes coupling circuitry configured to couple an output line of processing circuitry external to the flash memory device to an access line of a volatile memory of the flash memory.

In some embodiments, the coupling circuitry is a bus addressed array.

In some embodiments, the flash memory further includes a nonvolatile memory storing at least one of a program for controlling the write/program controller or a parameter for setting the nonvolatile memory cell array. The write/program controller may be configured to perform programming, erasing, and verifying of the memory data.

In some embodiments, the flash memory device includes coupling circuitry configured to couple output lines of processing circuitry external to the flash memory device to access lines of the volatile memory and access lines of the non-volatile memory.

In some embodiments, the flash memory interface includes a write/read interface configured to write data to and read data from an array of non-volatile memory cells of the flash memory.

In some embodiments, the second communication bus is a synchronous bus.

In some embodiments, the flash memory includes at least one register that stores at least one of a configuration value of the flash memory or a parameter for setting the array of non-volatile memory cells.

In some embodiments, the flash memory device includes coupling circuitry configured to couple an output line of processing circuitry external to the flash memory device to an access line of the at least one register.

In some embodiments, the array of non-volatile memory cells is configured to store configuration values and program patches of the volatile memory in an access protected control area of the flash memory.

In some embodiments, the non-volatile memory cell array is configured to store a program patch, and the flash memory interface includes a finite state machine configured to control obtaining the program patch from the non-volatile memory cell array via the second communication bus and transferring the program patch to the volatile memory.

In some embodiments, the flash memory interface includes virtual address translation circuitry configured to translate virtual addresses to physical addresses.

In at least one embodiment, a method is provided for accessing flash memory in a flash memory device using a flash memory interface, the flash memory disposed external to the flash memory. Flash memory includes an array of non-volatile memory cells and volatile memory. The method comprises the following steps: accessing data stored in the non-volatile memory cell array via a first communication bus coupling the flash memory interface to the non-volatile memory cell array; and accessing data stored in the volatile memory via a second communication bus coupling the flash memory interface to the volatile memory.

In some embodiments, the method comprises: the output line of the processing circuit means located outside the flash memory device is coupled to the access line of the volatile memory of the flash memory by the coupling circuit means.

In some embodiments, the method comprises: at least one of a program for controlling the write/program controller or a parameter for setting the nonvolatile memory cell array is stored in the nonvolatile memory of the flash memory.

In some embodiments, the method comprises: in a nonvolatile memory cell array, configuration values and program patches of a volatile memory are stored in an access protection control area of a flash memory.

In some embodiments, the method comprises: storing a program patch in the array of non-volatile memory cells; and obtaining a program patch from the array of non-volatile memory cells via the second communication bus and transferring the program patch to the volatile memory through a finite state machine control of the flash memory interface.

In at least one embodiment, a method of booting a flash memory in a flash memory device using a flash memory interface disposed external to the flash memory is provided. The flash memory includes a nonvolatile memory cell array and a volatile memory, and the memory cell array is configured to store configuration values and program patches of the volatile memory. The method comprises the following steps: obtaining a configuration value of the volatile memory between a power-up and a start-up procedure of the flash memory device via the first communication bus through the flash memory interface; and obtaining a program patch from the flash memory via the second communication bus based on the configuration values of the volatile memory, and loading the program patch into the volatile memory of the flash memory.

In at least one embodiment, a method includes: the output line of the processing circuit means located outside the flash memory device is coupled to the access line of the volatile memory of the flash memory by the coupling circuit means.

In at least one embodiment, a method includes: at least one of a program for controlling the write/program controller or a parameter for setting the nonvolatile memory cell array is stored in the nonvolatile memory of the flash memory.

Drawings

For a more complete understanding of one or more embodiments of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 schematically illustrates an example of a flash memory device according to an embodiment of the present disclosure;

FIG. 2 schematically illustrates the flash memory and flash memory interface of FIG. 1, in accordance with an embodiment of the present disclosure;

FIG. 3 schematically illustrates the flash memory and flash memory interface of FIG. 1 according to another embodiment of the present disclosure;

FIG. 4 is a flow diagram illustrating a method of booting the flash memory of FIG. 2 or 3 in accordance with one or more embodiments;

FIG. 5 is a flow chart illustrating an example of an implementation of the steps of the method of FIG. 4;

fig. 6 schematically illustrates an example of a flash memory device according to another embodiment of the present disclosure;

FIG. 7 is a block diagram illustrating an example of an implementation of a method of accessing flash memory of the apparatus of FIG. 6 in accordance with one or more embodiments;

FIG. 8 is a block diagram illustrating an example of an implementation of a method of reading from flash memory of the apparatus of FIG. 6 in accordance with one or more embodiments;

FIG. 9 is a timing diagram illustrating an example of an implementation of a method of writing into flash memory of the apparatus of FIG. 6 in accordance with one or more embodiments; and

FIG. 10 is a timing diagram illustrating an example of an implementation of a method of reading from flash memory of the device of FIG. 6 in accordance with one or more embodiments.

Detailed Description

Like features are denoted by like reference numerals throughout the various figures. In particular, structural and/or functional features common in the various embodiments may have the same reference numerals and may be provided with the same structural, dimensional, and material characteristics.

For clarity, only the steps and elements useful for understanding the embodiments described herein are shown and described in detail.

Unless otherwise indicated, when referring to two elements being connected together, this means that there is no direct connection of any intermediate element other than a conductor, and when referring to two elements being connected together, this means that the two elements may be connected or they may be coupled via one or more other elements.

In the following disclosure, when referring to absolute positional qualifiers, such as the terms "front", "rear", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "upper", "lower", etc., or orientation qualifiers, such as "level", "vertical", etc., reference is made to the orientation of the drawings unless otherwise indicated.

Unless otherwise indicated, the expressions "about", "substantially" and "on the order of …" mean within 10%, preferably within 5%.

Fig. 1 shows an example of an apparatus 100 comprising a flash memory 104 (flash memory) in communication with a flash memory interface 106 (flash memory interface) and configured to write data to the flash memory 104 or read data from the flash memory 104.

The flash memory interface 106 is configured to, for example, specifically ensure management of writing data to the flash memory 104 and reading data from the flash memory 104.

The device 100 also includes, for example, processing circuitry 110 (which may be referred to herein as a processing unit 110) (CPU). The processing circuitry 110 may include any circuitry suitable for performing the various functions described herein with respect to the processing circuitry 110. In some embodiments, processing circuitry 110 may include one or more processors under the control of instructions stored in instruction memory 112 (INSTR MEM). The instruction memory 112 is, for example, a random access type (random access memory, RAM). The processing unit 110 and the memory 112 communicate, for example, via a system bus 140. The flash memory 104 is coupled to the system bus 140, for example, via the flash memory interface 106 and via a communication bus 114 that couples the flash memory interface 106 to the flash memory 104. In one example, the apparatus 100 further includes an input/output interface 108 (I/O interface) coupled to the system bus 140.

Fig. 2 schematically illustrates the flash memory 104 and the flash memory interface 106 of fig. 1 in more detail according to another embodiment of the present disclosure.

According to the example of fig. 2, flash memory 104 includes, for example, an array of non-volatile memory cells 208. Flash memory 103 also includes, for example, volatile memory 206 (RAM), such as the type of RAM. The array 208 of non-volatile memory cells is configured, for example, to store a RAM configuration value 202 (configuration bit), which is formed, for example, from one or more bits. The RAM configuration value 202 may be in the form of one or more bits that indicate whether a program PATCH 204 (PATCH) of flash memory is available for an application. The patch 204 is stored, for example, in a non-volatile memory cell array 208.

Program patch 204 is, for example, code for correcting an operating program of flash memory 104. The operation program of the flash memory 104 is stored in, for example, a nonvolatile memory 212 (ROM) of the flash memory 104. The nonvolatile memory 104 also includes parameters for setting the memory cell array 208, for example. Patch 204 can, for example, modify execution of an operating program of flash memory 104. According to an example, patch 204 is stored on a plurality of rows or columns of the memory cell array.

In an example not shown, configuration values 202 and/or program patches 204 are stored in one or more non-volatile registers of flash memory 104 outside of memory cell array 208.

The communication bus 114 allows data communication between the flash memory interface 106 and at least a portion of the flash memory 104. According to one example, the communication bus 114 is configured to be able to communicate with the RAM206. According to one example, the communication bus 114 is a synchronous bus, which provides simplicity of implementation. According to another embodiment, the communication bus 114 is of an asynchronous type. The bus comprises, for example, a selection Signal (SEL) and/or a signal (WEN) capable of activating writing data to the flash memory 104 and/or a signal (ADD) containing a physical address of the flash memory 104 and/or a data input and output signal (DIN/DOUT) and/or a clock signal (HCLK).

The flash memory interface 106 is arranged, for example, outside the flash memory 104. In this case, this enables the memory interface 106 and the flash memory 104 to be designed in different ways. The flash memory interface 106 forms part of a system on a chip (SOC), for example.

According to the example of fig. 2, the flash memory interface includes, for example, address translation circuitry 232 (which may be referred to herein as an address translation module 232) (address translation module) for translating virtual addresses to physical addresses of the flash memory 104, and/or interface 238 for writing/reading (W/R) data to be written to the memory cell array 208 of the flash memory 104 and to be read from the memory cell array 208 of the flash memory 104.

According to the example of fig. 2, the universal communication bus 214 enables, for example, communication between the flash memory interface 106 and the flash memory 104, wherein data is to be written into the non-volatile memory cell array 208 of the flash memory 106 via the write/read interface 238 and/or data is to be read from the non-volatile memory cell array 208 of the flash memory 106 via the write/read interface 238.

According to one example, flash memory interface 106 is configured to restore program patch 204 from flash memory 104. According to one example, after the flash memory interface has read and interpreted the configuration values 202 stored in the flash memory 104, a retrieval of the patch 204 is obtained. The flash memory interface 106 is further configured to load the patch 204 into the RAM206 of the flash memory 104 via the communication bus 114, for example.

According to an example, the flash memory interface is configured to obtain the RAM configuration value 202 between power-on (POWERUP) and BOOT process (BOOT) of the device 100 and prior to BOOT-up of the flash memory. This enables the patch 204 to be applied before the flash memory 104 begins its operating program.

According to the example of fig. 2, the configuration values 202 and patches 204 are stored, for example, in a control area 210 of the flash memory, which control area 210 is an area reserved to store configuration parameters and to have access to protected, for example, only profiles with administrative rights.

Fig. 3 schematically illustrates the flash memory 104 and the flash memory interface 106 of fig. 1 according to another embodiment of the present disclosure.

In the example of fig. 3, the memory cell array, the program patches, the configuration values, the RAM and ROM memory, and the control areas of the flash memory are for example similar to those described in connection with fig. 2. In the example of fig. 3, the flash memory interface is, for example, similar to that described in connection with fig. 2, except that the flash memory interface also includes a finite state machine 330 (FSM). In the example of fig. 3, communication buses 114 and 214 are, for example, similar to the communication bus of fig. 2.

In the example of fig. 3, a position counter 322 (counter row) is arranged in the memory cell array 208. In an example not shown, the position counter 322 of the memory cell array 208 is disposed outside the memory cell array 208. The location counter 322 follows the last location, particularly the last location to be refreshed, of a column of memory cells, such as the array 208 of memory cells that have been refreshed. The location counter 322 is used, for example, by a write/program controller 320 (PEC), the write/program controller 320 being configured to implement a control program stored in the ROM non-volatile memory 212 of the flash memory 104. The control program includes, for example, the steps of programming, erasing, and verifying memory data, such as algorithms for programming/erasing memory cells of the array 208. The algorithm, for example, determines the fastest and most qualitative way to program and/or erase the memory cells of the array 208. The verification step is further implemented, for example, by the algorithm. In one example, the control program forms all or part of the operating program of the flash memory 104.

According to the example of fig. 3, the flash memory further includes a register 324 (REGS) that stores configuration values of the flash memory 104 and/or stores parameters for setting the memory cell array 208. The register 324 may also include, for example, redundant information. The register 324 is formed, for example, with a T-type flip-flop in particular.

According to the example of fig. 3, finite state machine 330 (FSM) of flash memory interface 106 is configured to manage the retrieval of program patch 204 from flash memory 104 over communication bus 114 and return it to RAM206. This enables, for example, restoration of patch 204 without using software that uses flash memory that is only operational after the boot process of device 100. This also enables the patch 204 to be transferred to the RAM206 of the flash memory 104 without using software of the flash memory that is operable only after the start-up of the device 100, and this is done prior to the start-up procedure of the device 100.

Fig. 4 illustrates a method of starting the flash memory of fig. 2 or 3. The method is implemented, for example, by the flash memory interface 106.

At step 402 (read dedicated flash configuration bits after power-up and prior to start-up), flash memory interface 106 reads flash memory configuration values 202, for example. This step 402 occurs after power-up but prior to the boot process of the device 100 and flash memory 104. This step may be implemented, for example, by finite state machine 330.

At step 404 (patch available. If yes (branch Y), then step 406 is performed (the patch is restored from the flash macro). If not (branch N), the method ENDs, for example, with a method END step 410 (END).

During step 406, the flash memory interface 106 restores all or part of the patch 204, for example, via the finite state machine 330. The patch 204 is then stored in the flash memory interface 106, for example.

In the remainder of step 406 (loading path in RAM), patch 204 is returned to communication bus 114, for example, using finite state machine 330. The communication bus 114 then passes the patch 204 to the RAM206 of the flash memory 104. The patch 204 may then be implemented by the flash memory 104 to correct or replace the control program stored in the non-volatile memory 212 before the boot process of the non-volatile memory 212 begins.

Fig. 5 shows an example of an implementation of step 406 of the method of fig. 4.

At step 506 (setting the first row of the patch), the patch 204 is scanned, for example, at a level corresponding to the portion of the patch 204 of its first row.

At a next step 508 (transferring patch rows from the flash macro), for example, the portion of the patch 204 restored at step 506 is restored by the flash memory interface 106.

At a next step 510 (loading the patch in RAM), the portion of the patch 204 recovered at step 508 is transferred to the communication bus 114 and stored in RAM206.

At step 514 (patch end. In the case of branch Y, step 410 is performed. In the case of branch N, step 512 (increment flash row) is performed. At this step 512, another portion of the patch 204 is read, for example, by incrementing the index corresponding to the row of the patch 204. After step 512, steps 508, 510 and 514 are again implemented to enable, for example, reading of the entire 204.

Fig. 6 schematically illustrates an example of a flash memory device 600 according to another embodiment of the disclosure.

In the example of fig. 6, flash memory device 600 is similar to, for example, the devices of fig. 1,2, and 3. In particular, the various elements of the apparatus 600 are identical to the elements 100 of fig. 1,2 and 3, and these elements are denoted by the same reference numerals and will not be described in detail.

The flash memory device 600 further includes a coupling circuit device 606 (which may be referred to herein as a coupling module 606) that couples the output lines of the processing unit 110 to the access lines of the flash memory interface 106. The link ensured by the coupling module 606 allows the processing unit 110 to access the RAM206 via the flash memory interface 106, for example. In one example, the coupling module 606 includes a bus addressing array that takes as input a bus, e.g., of the AHB (advanced high performance bus) type, including output lines of the processing unit 110. The coupling module 606 includes, for example, at its output, an output bus 604, such as an AHB-type, that is coupled to the second bus 114, for example, via the flash memory interface 106. The coupling module 606 is, for example, hard coded. In an example, the coupling module 606 couples output lines of the processing unit 110 to access lines of the non-volatile memory 212, for example, via the flash memory interface 106 and the second bus 114. In another example, the coupling module 606 couples output lines of the processing unit 110 to access lines of the registers 324, e.g., via the flash memory interface 106 and the second bus 114.

Fig. 7 schematically illustrates an example of an implementation of a method of accessing a flash memory of the apparatus of fig. 6.

At step 702 (address verification), the processing unit 110 sends, for example, one or more requests to an address of the flash memory 104, which is transcribed into an address corresponding to the register 324 and/or the RAM206 and/or the ROM212 via the coupling module 606 and the virtual address translation module 232. At the output of the coupling module 606, the request is passed on to the flash memory interface 106 via the bus 604. The request for example comprises a known control signal according to the AHB bus protocol: hsel, htrans, hready, hprot or haddr. The requested address is parsed, for example, by flash memory interface 106 to be verified. If the address corresponds to an address of one of the memories 206 or 212 or to an address of the register 324, the address is verified.

In step 704 (storing address phases in registers), when an address is verified, it is stored in one or more registers of flash memory interface 106. The clock signal hclk is used, for example, to store an address into a register.

At step 706 (access RAM, ROM, REG), an instruction to set the flash memory to test mode (testmode) is sent to, for example, flash memory 104. The request for accessing the memory 206, 212 or register 324 of the flash memory 104 is then, for example, via the bus 114 with, for example, known control signals: sel, wen, dataout and/or addr, and is implemented using the address stored in the flash memory interface 106 at step 704, and is converted, for example, by the virtual address conversion module 232.

Fig. 8 shows in block form an example of an implementation of a method of reading from the flash memory of the device of fig. 6.

At step 808 (retrieving data from RAM, ROM, REG to flash memory interface), the data from memory 206 or 212 or from register 324 is sent to flash memory interface 106, e.g., via bus 114, e.g., via data bus datain of bus 114.

At step 810 (send retrieved data to the GPU), the obtained data is redirected to the processing unit 110, e.g., via the bus 604, e.g., via the data bus rdata of the bus 604.

The methods of fig. 7 and 8 facilitate access to data of the flash memory, for example, during a test mode, and facilitate repair and/or setup of the flash memory.

Fig. 9 shows in timing diagram form an example of an implementation of a method of writing into the flash memory of the device of fig. 6. FIG. 9 specifically illustrates an example of access to RAM by a set of signals generated internally by flash memory interface 106 based on signals present on bus 604:

-a signal for selecting the bus hselr_ram;

-address signal hadrrr;

-a transmission signal HTRANSr indicating a current transmission type, wherein, for example: "00" indicates that no transmission is in progress: idle; "01" indicates an ongoing transmission: busy; '10' represents the first data of a data transmission or data burst: NONSEQ; "11" indicates data transmission in a data burst: SEQ (SEQ);

-a write enable signal HWRITEr;

-an access size signal HSIZEr;

-a signal HREADYOUTr indicating that transfer on the bus has ended and a signal HREADYr indicating that previous transfer has ended;

-a write data bus HWDATAr;

-read data bus HRDATAr; and

-response signal HRESPr.

Further, fig. 9 shows a set of signals sent to flash memory via bus 114: -a clock signal HCLK;

-a bus select signal sel_regs;

-address signals ADDREGS;

-a write enable signal wen_regs;

-a data output signal dousegs; and

-a data input signal dimregs.

The bus 604 is inactive until a time t1 corresponding to the rising edge of the selection signal hselr_ram and the rising edge of the clock signal HCLK. For example, the signal on bus 604 has, for example, the following values, whereas bus 604 is inactive from a writing point of view (all digital values in fig. 9 are represented, for example, in hexadecimal fashion): hselr_ram=low level, haddrr=0000, htransr=0, hwriter=low level, hsizeer=0, hreadult=high level, hreadyr=high level, hwdatar=000000000000, hrdatar=000000000, hrespr=low level. Similarly, prior to time t1, bus 114 is also inactive from a write standpoint, and the signals passed by the flash memory interface to bus 114 to the flash memory are, for example: sel_regs=low level, addregs=fff, wen_regs=high level, dousegs=0001, dimregs=3f80.

A write instruction is received on bus 604 between time t1 and time t2, which correspond to an address phase. The write operation includes an address phase during a first clock cycle HCLK between time t1 and time t2 and a data phase during a second clock cycle between time t2 and time t 3.

During the addressing phase, bus 114 remains inactive and the next signal is modified, for example, due to the signal present on bus 604: hselr_ram=high level, hadsrr=0004, htransr=2, hwriter=high level, hsizeer=1. In this example, these signals correspond to writing 16 bits to a virtual address having 0004 as the least significant bits. When the signal hselr_ram switches to a high level, this enables, for example, the selection of an address corresponding to the RAM206 of the flash memory 104. For example, the flash memory interface detects that signal HSEL is active on bus 604, and that address HADDR on bus 604 corresponds to the address of a register of RAM206, and thus activates select signal hselr_ram. For example, the flash memory interface 106 decodes the address passed by the processing unit 110 and stores it on the value HADDRr, e.g., 0004 herein. When htransr=2, this enables the address of the register of RAM206 to be calculated during the data phase. When HWRITEr is high, this means that the operation is to write to the register specified by the virtual address. When HSIZEr is equal to 0, the size of data to be written is equal to 8 bits, for example. When HSIZEEr is equal to 1, the size of the data to be written is equal to 16 bits, for example. When HSIZEEr is equal to 2, the size of the data to be written is equal to, for example, 32 bits.

The data phase is triggered by the rising edge of clock signal HCLK at time t 2. Between time t2 and time t3, bus 604 becomes inactive again, for example, and the following signals are modified, for example, as follows: hselr_ram=low level, haddrr=1fec, htransr=0, hwriter=low level. The signal HSIZEr is inactive, for example, during the data phase. Between time t2 and time t3, the signal sel_regs is set to a high level, which enables selection of the register in which data is written. Between time t2 and time t3, signal ADDRESS switches to the value of the physical address of RAM206, e.g., 082. In practice, the virtual address translation module 232 of the flash memory interface 106 is configured, for example, to translate virtual addresses 0004 known to the processing unit 110 into physical addresses 082 in the RAM206. The signal WEN REGS is set low, for example, which activates, for example, writing. Between time t2 and time t3, the signal DINREGS containing data from the HWDATAr to be written, e.g. here 0002, is written, e.g. by reducing the number of bits provided on bus 604 to only 16 least significant bits.

After time t3, buses 604 and 114 become inactive, for example. The following signals are modified, for example, as follows: haddrr=0000, hsizeer=0, hwdatar=00000000, sel_regs=low, addregs=fff, wen_regs=high, dimregs=3f80. In the example shown, the fact that signals addrogs and dimregs have values FFF and 3F80 before t2 and after t3, respectively, is independent of the data writing process.

Fig. 10 shows in timing diagram form an example of an implementation of a method of reading from the flash memory of the device of fig. 6. Fig. 10 shows in particular the same signals as shown in fig. 9, but for the case of a read operation.

Before time t5, which corresponds to the rising edge of clock signal HCLK and signal hselr_ram, the signal of bus 604 has, for example, the following values: hselr_ram=low level, haddrr=0000, htransr=0, hwriter=low level, hsizer=0, hreadult=high level, hreadyr=high level, hwdatar=000000000000, hrdatar=000000000, hrespr=low level. Before time t5, the signals on bus 114 towards the flash memory interface are set to, for example, the following levels: sel_regs=low level, addregs=fff, wen_regs=high level, dousegs=0001, dimregs=3f80.

Between time t5 and time t6, which correspond to the rising edge of clock signal HCLK, for example shifted by one clock cycle with respect to t5, the following values are modified, for example: hselr_ram=high level, haddrr=0004, htransr=2, hsizer=1, sel_regs=high level, addrregs=082, wen_regs=high level, dimregs=0000. This enables the address of the RAM206 requested by the processing unit 110 to be translated into a physical address, here physical address 082, of a register of the RAM206 of the flash memory 104 to be read.

Between time t6 and time t7, which correspond to the rising edge of clock signal HCLK, for example shifted by one clock cycle with respect to t6, the following signals are modified, for example: hadrrr=0000, htransr=0, hsizer=0, hwdatar=00000002, hrdatar=00000002, sel_regs=low level, addregs=fff, dousegs=0002, dinregs=3f80. This enables the data stored in the registers of the RAM206 of the flash memory 104, for example 0002 herein, to be read via the signal dousegs over the bus 114 and sent over the bus 604, where they are for example contained in the signal HRDATAr. In the example of fig. 10, data derived from dousegs=0002 is sent to HRDATAr, which becomes 00020002. In this example, data 0002 encoded on 16 bits in the dousegs is copied onto the 16 most significant bits and 16 least significant bits of HRDATAr. In another example, one skilled in the art can leave the data of the dousegs on the most significant bit or the least significant bit.

After time t7, the following signals are modified, for example:

HRDATAr＝00000000，HWDATAr＝00000000。

in the example shown, the fact that signals addrogs and dimregs have values FFF and 3F80 before t5 and after t6, respectively, is independent of the data reading process.

An aspect of the present disclosure provides a flash memory device (100) including:

a flash memory (104) comprising an array of non-volatile memory cells (208) and a volatile memory (206);

a first communication bus (214) coupling the flash memory interface (106) and the memory cell array (208); and

a second communication bus (114) coupling the flash memory interface (106) and the volatile memory (206);

the array of memory cells (208) is configured to store at least one configuration value and a program patch (204) of the volatile memory (206), the method comprising:

obtaining, by the flash memory interface (106), the configuration value of the volatile memory (206) between a power-up and a start-up procedure of the device (100) via the first bus, and

according to the configuration values of the volatile memory (206), a program patch (204) is obtained from the flash memory (104) and loaded into the volatile memory (206) of the flash memory (104) via the second communication bus (114).

Another aspect of the present disclosure provides a method for accessing a flash memory (104) in a flash memory device (100) by using a flash memory interface (106) disposed outside the flash memory (104), the flash memory comprising an array of non-volatile memory cells (208) and a volatile memory (206), the method comprising:

-accessing data stored in the memory cell array (206) via a first communication bus coupling the flash memory interface (106) and the memory cell array (208); and

-accessing data stored in the volatile memory (206) via a second communication bus (114) coupling the flash memory interface (106) and the volatile memory (206);

the array of memory cells (208) is configured to store at least one configuration value and a program patch (204) of the volatile memory (206), the method comprising:

-obtaining, by the flash interface (106), the configuration value of the volatile memory (206) between a power-on and a start-up procedure of the device (100) via the first bus, and

according to the configuration values of the volatile memory (206), a program patch (204) is obtained from the flash memory (104) and loaded into the volatile memory (206) of the flash memory via the second communication bus (114).

Various embodiments and modifications have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined and that other variations will occur to those skilled in the art. In particular, although the examples mention implementation of configuration values 202 for flash memory 104, one skilled in the art may implement a plurality of configuration values, for example in the form of a plurality of configuration bits. The type of bus 604 is, for example, an AHB bus type. In this case, the corresponding instructions may be encoded differently from those described in the examples of fig. 9 and 10. The addresses of the registers, RAM and ROM memories of the flash memory are, for example, different from those given as examples in fig. 9 and 10.

Finally, based on the functional indications given above, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art.

Claims (20)

1. A flash memory device, comprising:

a flash memory including a nonvolatile memory cell array and a volatile memory;

a flash memory interface disposed outside the flash memory;

a first communication bus coupling the flash memory interface to the array of non-volatile memory cells; and

a second communication bus couples the flash memory interface to the volatile memory.

2. The flash memory device of claim 1, further comprising coupling circuitry configured to couple an output line of processing circuitry located external to the flash memory device to an access line of the volatile memory of the flash memory.

3. The flash memory device of claim 2, wherein the coupling circuit means is a bus addressed array.

4. The flash memory device of claim 1, wherein the flash memory further comprises a non-volatile memory storing at least one of a program for controlling a write/program controller configured to enable programming, erasing, and verifying of memory data or parameters for setting the array of non-volatile memory cells.

5. The flash memory device of claim 4, further comprising coupling circuitry configured to couple output lines of processing circuitry located external to the flash memory device to access lines of the volatile memory and access lines of the non-volatile memory.

6. The flash memory device of claim 1, wherein the flash memory interface comprises a write/read interface configured to write data to and read data from the array of non-volatile memory cells of the flash memory.

7. The flash memory device of claim 1, wherein the second communication bus is a synchronous bus.

8. The flash memory device of claim 1, wherein the flash memory further comprises at least one register storing at least one of a configuration value of the flash memory or a parameter for setting the array of non-volatile memory cells.

9. The flash memory device of claim 8, further comprising coupling circuitry configured to couple an output line of processing circuitry located external to the flash memory device to an access line of the at least one register.

10. The flash memory device of claim 1, wherein the array of non-volatile memory cells is configured to store configuration values and program patches of the volatile memory in an access protection control area of the flash memory.

11. The flash memory device of claim 1, wherein the array of non-volatile memory cells is configured to store a program patch, and the flash memory interface comprises a finite state machine configured to control the obtaining of the program patch from the array of non-volatile memory cells via the second communication bus and the passing of the program patch to the volatile memory.

12. The flash memory device of claim 1, wherein the flash memory interface comprises virtual address translation circuitry configured to translate virtual addresses to physical addresses.

13. A method for accessing flash memory in a flash memory device using a flash memory interface, the flash memory interface disposed external to the flash memory, the flash memory comprising an array of non-volatile memory cells and a volatile memory, the method comprising:

accessing data stored in the non-volatile memory cell array via a first communication bus coupling the flash memory interface to the non-volatile memory cell array; and

data stored in the volatile memory is accessed via a second communication bus coupling the flash memory interface to the volatile memory.

14. The method of claim 13, further comprising:

an output line of processing circuitry located external to the flash memory device is coupled to an access line of the volatile memory of the flash memory by coupling circuitry.

15. The method of claim 13, further comprising:

at least one of a program for controlling a write/program controller or a parameter for setting the nonvolatile memory cell array is stored in a nonvolatile memory of the flash memory.

16. The method of claim 13, further comprising:

in the nonvolatile memory cell array, the configuration values and the program patches of the volatile memory are stored in an access protection control area of the flash memory.

17. The method of claim 13, further comprising:

storing a program patch in the array of non-volatile memory cells; and

the program patch is obtained from the array of non-volatile memory cells via the second communication bus and transferred to the volatile memory by finite state machine control of the flash memory interface.

18. A method of booting a flash memory in a flash memory device using a flash memory interface, the flash memory interface disposed external to the flash memory, the flash memory comprising an array of non-volatile memory cells and a volatile memory, wherein the array of memory cells is configured to store configuration values and program patches for the volatile memory, the method comprising:

obtaining the configuration value of the volatile memory between a power-up and a start-up procedure of the flash memory device via a first communication bus through the flash memory interface; and

a program patch is obtained from the flash memory via a second communication bus based on the configuration value of the volatile memory, and the program patch is loaded into the volatile memory of the flash memory.

19. The method of claim 18, further comprising:

an output line of processing circuitry located external to the flash memory device is coupled to an access line of the volatile memory of the flash memory by coupling circuitry.

20. The method of claim 18, further comprising:

at least one of a program for controlling a write/program controller or a parameter for setting a nonvolatile memory cell array is stored in a nonvolatile memory of the flash memory.