KR920018547A - Ladder Instruction Processing Unit - Google Patents

Ladder Instruction Processing Unit Download PDF

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Publication number
KR920018547A
KR920018547A KR1019910004711A KR910004711A KR920018547A KR 920018547 A KR920018547 A KR 920018547A KR 1019910004711 A KR1019910004711 A KR 1019910004711A KR 910004711 A KR910004711 A KR 910004711A KR 920018547 A KR920018547 A KR 920018547A
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KR
South Korea
Prior art keywords
ladder
instruction
ladder instruction
arithmetic
processing unit
Prior art date
Application number
KR1019910004711A
Other languages
Korean (ko)
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KR940000221B1 (en
Inventor
김영기
Original Assignee
안시환
삼성항공산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 안시환, 삼성항공산업 주식회사 filed Critical 안시환
Priority to KR1019910004711A priority Critical patent/KR940000221B1/en
Publication of KR920018547A publication Critical patent/KR920018547A/en
Application granted granted Critical
Publication of KR940000221B1 publication Critical patent/KR940000221B1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts

Abstract

내용 없음No content

Description

래더 명령 처리장치Ladder Instruction Processing Unit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 래더 다이어그램의 일예를 나타낸 도,1 is a view showing an example of a ladder diagram,

제 2 도는 (A) 및 (B)는 래더명령어와 이를 처리하는 컴퓨터의 머신 코드와의 대응관계를 나탄내 도,2 (A) and (B) show a correspondence relationship between ladder instructions and machine code of a computer processing the same;

제 3 도는 본 발명에 따른 하드웨어 구성도,3 is a hardware diagram according to the present invention,

제 4 도는 제3도에 래더명령 해독 연산 처리부에 대한 상세도.4 is a detailed view of the ladder instruction decoding operation processing unit in FIG.

Claims (2)

래더 명령어에 의해 프로그램 제어되는 제어시스템의 래더 명령어 처리수단은, 데이타 버스와 어드레스 버스로 상호 연결되는 중앙처리장치(1)와, ROM 및 RAM 구성의 기억장치(28)를 포함하고, 명령어에 의해 지정된 어드레스에 따라 상기 데이타 버스의 비트값을 선택 출력하는 데이타 버스 선택 출력 수단(5)과, 선택된 비트 및 지정 어드레스에 대응하여 명령어 해독과 연산을 수행하는 다수의 논리소자로 구성되는 사용자 래더 명령 해독 연산처리수단(6)과, 연산결과를 저장 또는 출력하는 스택(7), (8)으로 상호 연결구성됨을 특징으로 하는 래더 명령 처리장치.The ladder instruction processing means of the control system program-controlled by the ladder instructions includes a central processing unit 1 interconnected by a data bus and an address bus, and a storage unit 28 of a ROM and RAM configuration, User ladder instruction decryption comprising a data bus select output means 5 for selectively outputting a bit value of the data bus in accordance with a designated address, and a plurality of logic elements for performing instruction decryption and operation corresponding to the selected bit and the designated address. And a stack (7) and (8) for interconnecting arithmetic processing means (6) and storing or outputting arithmetic results. 제 1 항에 있어서, 상기 래더 명령 해독 연산 처리수단(6)은 제4도와 같이 명령선택신호(A7~A10)를 받아 명령해독을 행하는 명령해독 디코더(10)와, 각 명령어에 대응하는 디코더 출력과 데이타 비트 선택된 신호(D1)와 더불어 레더 명령어에 대한 연산을 행하도록 다수의 AND 및 OR게이트로 구성되는 레더 명령 연산처리부(27)와, 이 처리부(27)의 결과를 스택에 저장 또는 데이타 이동을 행하도록 클럭 발생부(9)가 연결구성됨을 특징으로 하는 래더 명령 처리장치.2. The ladder decoding apparatus according to claim 1, wherein the ladder instruction decoding operation processing means (6) receives instruction selection signals (A 7 to A 10 ) as shown in FIG. A ladder instruction arithmetic unit 27 consisting of a plurality of AND and OR gates to perform arithmetic on a ladder instruction together with a decoder output and a data bit selected signal D1, and storing the result of the processing unit 27 on a stack or Ladder instruction processing apparatus, characterized in that the clock generator (9) is connected to perform data movement. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019910004711A 1991-03-25 1991-03-25 Ladder command processor apparatus KR940000221B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910004711A KR940000221B1 (en) 1991-03-25 1991-03-25 Ladder command processor apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910004711A KR940000221B1 (en) 1991-03-25 1991-03-25 Ladder command processor apparatus

Publications (2)

Publication Number Publication Date
KR920018547A true KR920018547A (en) 1992-10-22
KR940000221B1 KR940000221B1 (en) 1994-01-12

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910004711A KR940000221B1 (en) 1991-03-25 1991-03-25 Ladder command processor apparatus

Country Status (1)

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KR (1) KR940000221B1 (en)

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Publication number Publication date
KR940000221B1 (en) 1994-01-12

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