JPS5541565A - Address modification system - Google Patents

Address modification system

Info

Publication number
JPS5541565A
JPS5541565A JP11527178A JP11527178A JPS5541565A JP S5541565 A JPS5541565 A JP S5541565A JP 11527178 A JP11527178 A JP 11527178A JP 11527178 A JP11527178 A JP 11527178A JP S5541565 A JPS5541565 A JP S5541565A
Authority
JP
Japan
Prior art keywords
modification
signals
index
base
logical operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11527178A
Other languages
Japanese (ja)
Inventor
Masanori Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP11527178A priority Critical patent/JPS5541565A/en
Publication of JPS5541565A publication Critical patent/JPS5541565A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make address modification high-speed by using a two-input adder to omit one of the number of addition times in case that one of base modification and index modification or both of them are not required.
CONSTITUTION: Decoding logical operation circuit 53 decodes bit patterns of base register number designation part 8 and index register number designation part 9 and discriminates that one of the base modification and index modification or both of them are not subjected to address modification and applies signals to control logical operation circuit 54. Fundamental clocks, start signals, base modification signals and index modification signals are applied to control circuit 54 from decoding logical operation circuit 53, and circuit 54 outputs control signal 45 to 50 and end signal 51.
COPYRIGHT: (C)1980,JPO&Japio
JP11527178A 1978-09-20 1978-09-20 Address modification system Pending JPS5541565A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11527178A JPS5541565A (en) 1978-09-20 1978-09-20 Address modification system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11527178A JPS5541565A (en) 1978-09-20 1978-09-20 Address modification system

Publications (1)

Publication Number Publication Date
JPS5541565A true JPS5541565A (en) 1980-03-24

Family

ID=14658525

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11527178A Pending JPS5541565A (en) 1978-09-20 1978-09-20 Address modification system

Country Status (1)

Country Link
JP (1) JPS5541565A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6079431A (en) * 1983-10-06 1985-05-07 Hitachi Ltd Programmable controller
JPS60176152A (en) * 1984-02-23 1985-09-10 Fujitsu Ltd Prefix area access control system
JPS6386032A (en) * 1986-09-30 1988-04-16 Toshiba Corp Effective address calculating device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6079431A (en) * 1983-10-06 1985-05-07 Hitachi Ltd Programmable controller
JPH024010B2 (en) * 1983-10-06 1990-01-25 Hitachi Ltd
JPS60176152A (en) * 1984-02-23 1985-09-10 Fujitsu Ltd Prefix area access control system
JPS6386032A (en) * 1986-09-30 1988-04-16 Toshiba Corp Effective address calculating device

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