JPS56149120A - Programmable logical array - Google Patents
Programmable logical arrayInfo
- Publication number
- JPS56149120A JPS56149120A JP5247580A JP5247580A JPS56149120A JP S56149120 A JPS56149120 A JP S56149120A JP 5247580 A JP5247580 A JP 5247580A JP 5247580 A JP5247580 A JP 5247580A JP S56149120 A JPS56149120 A JP S56149120A
- Authority
- JP
- Japan
- Prior art keywords
- independently
- array
- data latch
- clock input
- attains
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To realize an asynchronous logical circuit which attains an expected logical purpose, by supplying clock inputs to J-KFF and a data latch from an OR array independently of each other. CONSTITUTION:Clock input CK to J-KFF10 is supplied from OR array 2 independently, and clock input CK to data latch 11 is also supplied from array 2 independently. Consequently, each clock input is programmable freely and independently, so the FF and data latch can be operated asynchronously. Then, every tim input data 3 changes, a succession of cascaded changes occurs internally, so that the asynchronous logical circuit can be obtained which attains the expected logical purpose.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5247580A JPS56149120A (en) | 1980-04-21 | 1980-04-21 | Programmable logical array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5247580A JPS56149120A (en) | 1980-04-21 | 1980-04-21 | Programmable logical array |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56149120A true JPS56149120A (en) | 1981-11-18 |
JPS6234183B2 JPS6234183B2 (en) | 1987-07-24 |
Family
ID=12915740
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5247580A Granted JPS56149120A (en) | 1980-04-21 | 1980-04-21 | Programmable logical array |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56149120A (en) |
-
1980
- 1980-04-21 JP JP5247580A patent/JPS56149120A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6234183B2 (en) | 1987-07-24 |
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