JPS5776927A - Counter circuit - Google Patents

Counter circuit

Info

Publication number
JPS5776927A
JPS5776927A JP15193380A JP15193380A JPS5776927A JP S5776927 A JPS5776927 A JP S5776927A JP 15193380 A JP15193380 A JP 15193380A JP 15193380 A JP15193380 A JP 15193380A JP S5776927 A JPS5776927 A JP S5776927A
Authority
JP
Japan
Prior art keywords
type flip
flop
output
stage
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15193380A
Other languages
Japanese (ja)
Inventor
Susumu Kawakami
Takashi Totoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15193380A priority Critical patent/JPS5776927A/en
Publication of JPS5776927A publication Critical patent/JPS5776927A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/58—Gating or clocking signals not applied to all stages, i.e. asynchronous counters
    • H03K23/588—Combination of a synchronous and an asynchronous counter

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To obtain a stable output synchronized with a basic clock, by providing a D type flip-flop to which the basic clock is inputted between stages of a counter, in the asynchronous counter consisting of D type flip-flops. CONSTITUTION:A plurality of D type flip-flop are used, and a counter is constituted by taking an output Q1' of the prestage as an input phi of the clock of the next stage and an output Q1 of each stage as the D input of the stage. Between a D type flip-flop D-FFN of the Nth stage and a D type flip-flop D-FFN+1 at the N+1th stage, a D type flip-flop D-FFM taking the Nth output as D input and the basic clock CP as a clock input phi is inserted. The shift in output delay time caused by dispersion of characteristics of each D type flip-flop circuit element is corrected to obtain an output synchronized with the basic clock CP.
JP15193380A 1980-10-29 1980-10-29 Counter circuit Pending JPS5776927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15193380A JPS5776927A (en) 1980-10-29 1980-10-29 Counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15193380A JPS5776927A (en) 1980-10-29 1980-10-29 Counter circuit

Publications (1)

Publication Number Publication Date
JPS5776927A true JPS5776927A (en) 1982-05-14

Family

ID=15529366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15193380A Pending JPS5776927A (en) 1980-10-29 1980-10-29 Counter circuit

Country Status (1)

Country Link
JP (1) JPS5776927A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100361388C (en) * 2004-12-24 2008-01-09 科圆半导体（上海）有限公司 Programmable asynchronous triggering time delayer, and method of use

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100361388C (en) * 2004-12-24 2008-01-09 科圆半导体（上海）有限公司 Programmable asynchronous triggering time delayer, and method of use

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