JPS5597075A - Signal delay circuit - Google Patents

Signal delay circuit

Info

Publication number
JPS5597075A
JPS5597075A JP463479A JP463479A JPS5597075A JP S5597075 A JPS5597075 A JP S5597075A JP 463479 A JP463479 A JP 463479A JP 463479 A JP463479 A JP 463479A JP S5597075 A JPS5597075 A JP S5597075A
Authority
JP
Japan
Prior art keywords
delay
ram1
clock
counter
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP463479A
Other languages
Japanese (ja)
Inventor
Makoto Inagi
Sadanobu Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP463479A priority Critical patent/JPS5597075A/en
Publication of JPS5597075A publication Critical patent/JPS5597075A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

PURPOSE:To facilitate an easy alternation for the delay time by constituting the signal delay circuit mainly with the memory which is capable of designating the address. CONSTITUTION:The following component parts are provided: RAM1; counter 2 which designates address Ai of RAM1; latch circuit 3 for the input signal; and lathc circuit 4 for the output of RAM1 each. And clock 5 is supplied, and thus address Ai is altered with every cycle of clock f0. Thus both the reading and writing are carried out at one time and in synchronization with clock f0. And in case the N-1 notation counter is used for counter 2, the delay equivalent to N clocks can be obtained as a whole including the delay at latch 4.
JP463479A 1979-01-17 1979-01-17 Signal delay circuit Pending JPS5597075A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP463479A JPS5597075A (en) 1979-01-17 1979-01-17 Signal delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP463479A JPS5597075A (en) 1979-01-17 1979-01-17 Signal delay circuit

Publications (1)

Publication Number Publication Date
JPS5597075A true JPS5597075A (en) 1980-07-23

Family

ID=11589431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP463479A Pending JPS5597075A (en) 1979-01-17 1979-01-17 Signal delay circuit

Country Status (1)

Country Link
JP (1) JPS5597075A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07288454A (en) * 1994-04-15 1995-10-31 Nec Corp Digital delay circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07288454A (en) * 1994-04-15 1995-10-31 Nec Corp Digital delay circuit

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