JPS6449425A - Frequency dividing circuit - Google Patents

Frequency dividing circuit

Info

Publication number
JPS6449425A
JPS6449425A JP20518487A JP20518487A JPS6449425A JP S6449425 A JPS6449425 A JP S6449425A JP 20518487 A JP20518487 A JP 20518487A JP 20518487 A JP20518487 A JP 20518487A JP S6449425 A JPS6449425 A JP S6449425A
Authority
JP
Japan
Prior art keywords
signal
frequency division
output
flop
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20518487A
Other languages
Japanese (ja)
Other versions
JP2621205B2 (en
Inventor
Junichi Asada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20518487A priority Critical patent/JP2621205B2/en
Publication of JPS6449425A publication Critical patent/JPS6449425A/en
Application granted granted Critical
Publication of JP2621205B2 publication Critical patent/JP2621205B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To prevent a wicker in an output signal from being generated, by inputting the switching signal of a 1/2<n> frequency division signal and a 1/2<n-1> frequency division signal to the set input terminal of a flip-flop. CONSTITUTION:When the switching signal S2 to be inputted to the set input terminal S of a D flip-flop 1 with set input is an L, a clock signal S1 is frequency-divided, and a 1/8 frequency division signal is outputted to the output signal S3 of the clock signal. When the switching signal S2 goes to an H, the output (b) of the D flip-flop 1 goes to the H successively, and the function of a first frequency division circuit is interrupted, and the signal waveform (c) of the Q output of a D flip-flop 3 in a second frequency division circuit becomes a 1/2-frequency divided signal. The signal waveform (e) of the Q output of a D flip-flop 6 in a third frequency division circuit is outputted as a 1/4-frequency divided output signal S3.
JP20518487A 1987-08-20 1987-08-20 Divider circuit Expired - Lifetime JP2621205B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20518487A JP2621205B2 (en) 1987-08-20 1987-08-20 Divider circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20518487A JP2621205B2 (en) 1987-08-20 1987-08-20 Divider circuit

Publications (2)

Publication Number Publication Date
JPS6449425A true JPS6449425A (en) 1989-02-23
JP2621205B2 JP2621205B2 (en) 1997-06-18

Family

ID=16502800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20518487A Expired - Lifetime JP2621205B2 (en) 1987-08-20 1987-08-20 Divider circuit

Country Status (1)

Country Link
JP (1) JP2621205B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114337652A (en) * 2022-02-15 2022-04-12 山东兆通微电子有限公司 Frequency divider circuit and frequency synthesizer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114337652A (en) * 2022-02-15 2022-04-12 山东兆通微电子有限公司 Frequency divider circuit and frequency synthesizer
CN114337652B (en) * 2022-02-15 2022-06-17 山东兆通微电子有限公司 Frequency divider circuit and frequency synthesizer

Also Published As

Publication number Publication date
JP2621205B2 (en) 1997-06-18

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