JP2886281B2 - Boost circuit - Google Patents
Boost circuitInfo
- Publication number
- JP2886281B2 JP2886281B2 JP2177291A JP17729190A JP2886281B2 JP 2886281 B2 JP2886281 B2 JP 2886281B2 JP 2177291 A JP2177291 A JP 2177291A JP 17729190 A JP17729190 A JP 17729190A JP 2886281 B2 JP2886281 B2 JP 2886281B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- capacitor
- switches
- vcc
- charged
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0083—Converters characterised by their input or output configuration
- H02M1/009—Converters characterised by their input or output configuration having two or more independently controlled outputs
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、入力電圧の２倍の正の電圧と２倍の負の電
圧を得るための昇圧回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit for obtaining a positive voltage twice as high as an input voltage and a negative voltage twice as high as an input voltage.
［従来の技術］ 従来の昇圧回路として、第２図に示す回路がある。こ
の回路は、８個のスイッチS1〜S8と４個のコンデンサC1
〜C4から構成されるものである。まず、スイッチS1とS2
のみをオンして入力電源１の電圧VccでコンデンサC1を
図示の極性に充電する。次に、スイッチS3とS4のみをオ
ンして、コンデンサC2に図示の極性で充電を行う。この
ときは、入力電源１の電圧VccにコンデンサC1の電圧を
加算した電圧が充電される。次に、スイッチS1、S2、S
5、S6のみをオンする。このときは、上記したようにコ
ンデンサC1に入力電源１の電圧Vccで充電が行われと共
に、コンデンサC2の電荷がコンデンサC3に図示の極性で
放電される。次に、スイッチS3、S4、S7、S8のみをオン
する。このときは、コンデンサC2に上記したように電圧
が充電される外にコンデンサC4に接地端子４側を正とす
るように電荷が充電される。以後、以上の動作を繰り返
すことにより、コンデンサC2には入力電源１の電圧Vcc
の２倍の正の電圧＋2Vccが、またコンデンサC4には入力
電源１の電圧Vccの２倍の負の電圧−2Vccが発生し、各
々出力端子２、３が現れる。[Prior Art] As a conventional booster circuit, there is a circuit shown in FIG. This circuit consists of eight switches S1 to S8 and four capacitors C1
~ C4. First, switches S1 and S2
Only the capacitor is turned on, and the capacitor C1 is charged to the polarity shown in FIG. Next, only the switches S3 and S4 are turned on to charge the capacitor C2 with the illustrated polarity. At this time, a voltage obtained by adding the voltage of the capacitor C1 to the voltage Vcc of the input power supply 1 is charged. Next, switches S1, S2, S
5. Turn on only S6. At this time, as described above, the capacitor C1 is charged with the voltage Vcc of the input power supply 1, and the charge of the capacitor C2 is discharged to the capacitor C3 with the polarity shown in the figure. Next, only the switches S3, S4, S7 and S8 are turned on. At this time, in addition to charging the voltage to the capacitor C2 as described above, the capacitor C4 is charged with electric charge so that the ground terminal 4 side is positive. Thereafter, by repeating the above operation, the voltage of the input power supply 1
And a negative voltage of −2 Vcc, which is twice the voltage Vcc of the input power supply 1, is generated on the capacitor C4, and the output terminals 2 and 3 appear respectively.
［発明が解決しようとする課題］ ところが、この昇圧回路では、スイッチ素子が８個も
必要であり、これを半導体集積回路上で構成する場合に
は、スイッチ素子の抵抗分により負荷駆動能力が減殺さ
れるのでそのスイッチ素子の面積を大きくせざるを得
ず、このためチップサイズが大きくなるという欠点があ
った。[Problems to be Solved by the Invention] However, this booster circuit requires as many as eight switch elements, and when this is configured on a semiconductor integrated circuit, the load driving capability is reduced by the resistance of the switch elements. Therefore, there is no other choice but to increase the area of the switch element, which has the disadvantage of increasing the chip size.
本発明はこのような欠点をなくし、チップサイズを小
さくできるようにした昇圧回路を提供することである。An object of the present invention is to provide a booster circuit which eliminates such disadvantages and can reduce the chip size.
［課題を解決するための手段］ このために本発明の昇圧回路は、入力電圧を第１のコ
ンデンサに充電する第１、第２のスイッチ手段と、片端
に上記入力電圧が印加される第２のコンデンサに上記第
１のコンデンサの電圧を充電する第３、第４のスイッチ
手段と、第３のコンデンサに上記第３のスイッチ手段を
介して上記入力電圧を充電する第５のスイッチ手段と、
上記第１のコンデンサの電圧と上記第３のコンデンサの
電圧を加算した電圧を第４のコンデンサに充電する第
６、第７のスイッチ手段とを具備し、上記第２のコンデ
ンサの他端から上記入力電圧の２倍の正の出力電圧を、
上記第４のコンデンサから上記入力電圧の２倍の負の出
力電圧を得るように構成した。[Means for Solving the Problems] For this purpose, a booster circuit according to the present invention comprises a first and a second switch for charging an input voltage to a first capacitor, and a second switch for applying the input voltage to one end. Third and fourth switch means for charging the capacitor with the voltage of the first capacitor, and fifth switch means for charging the third capacitor with the input voltage via the third switch means;
Sixth and seventh switch means for charging a fourth capacitor with a voltage obtained by adding the voltage of the first capacitor and the voltage of the third capacitor, and providing the second capacitor from the other end of the second capacitor. A positive output voltage that is twice the input voltage
The fourth capacitor is configured to obtain a negative output voltage twice the input voltage.
［実施例］ 以下、本発明の実施例についてい説明する。第１図は
その一実施例の昇圧回路の回路図である。この回路で
は、７個のスイッチS11〜S17（第１〜第７のスイッチ手
段）と４個のコンデンサC11〜C14（第１の〜第４のコン
デンサ）により構成している。５は電圧がVccの入力電
源、６は正電圧出力端子、７は負電圧出力端子、８は入
力電源５の電圧Vccが印加する電圧端子である。この回
路をMOSFETで構成する場合には、スイッチS11、S13、S1
4をPMOSで、残りのスイッチS12、S15〜S17をNMOSで、各
々構成できる。[Example] Hereinafter, an example of the present invention will be described. FIG. 1 is a circuit diagram of a booster circuit according to one embodiment. This circuit comprises seven switches S11 to S17 (first to seventh switch means) and four capacitors C11 to C14 (first to fourth capacitors). 5 is an input power supply having a voltage of Vcc, 6 is a positive voltage output terminal, 7 is a negative voltage output terminal, and 8 is a voltage terminal to which the voltage Vcc of the input power supply 5 is applied. If this circuit is composed of MOSFETs, switches S11, S13, S1
4 can be constituted by PMOS, and the remaining switches S12 and S15 to S17 can be constituted by NMOS.
この回路では、以下の手順で昇圧動作を行う。 In this circuit, a boost operation is performed in the following procedure.
．スイッチS11とS12のみをオンさせる。このときは、
コンデンサC11が入力電源５の電圧Vccで充電される。. Only the switches S11 and S12 are turned on. At this time,
The capacitor C11 is charged with the voltage Vcc of the input power supply 5.
．スイッチS13、S14、S15のみをオンさせる。このと
きは、電圧VccでコンデンサC12が充電されて、出力端子
６からは＋2Vccの電圧が出力する。また同時に、入力電
源５の電圧VccでコンデンサC13に図示の極性に充電され
る。. Only the switches S13, S14 and S15 are turned on. At this time, the capacitor C12 is charged with the voltage Vcc, and a voltage of +2 Vcc is output from the output terminal 6. At the same time, the capacitor C13 is charged with the voltage Vcc of the input power supply 5 to the polarity shown.
．スイッチS11、S12のみをオンさせる。このときは、
のときと同様に、電圧VccでコンデンサC11に図示の極
性で充電される。. Only the switches S11 and S12 are turned on. At this time,
In the same manner as in the above case, the capacitor C11 is charged with the voltage Vcc with the polarity shown.
．スイッチS16、S17のみをオンさせる。このときは、
コンデンサC11の電圧とC13の電圧を加算した電圧でコン
デンサC14が図示の極性で充電される。. Only the switches S16 and S17 are turned on. At this time,
The capacitor C14 is charged with the polarity shown in the figure by adding the voltage of the capacitor C11 and the voltage of the capacitor C13.
．以上の〜のスイッチ切り替えを繰り返す。. The above-mentioned switches are repeated.
以上により、コンデンサC12には入力電源１の電圧Vcc
が充電されて＋2Vccの電圧が出力端子６に出力し、コン
デンサC14には同電圧Vccの２倍の負の電圧−2Vccが充電
されて出力端子７に出力する。Thus, the voltage Vcc of the input power supply 1 is
Is charged to output a voltage of +2 Vcc to the output terminal 6, and the capacitor C 14 is charged with a negative voltage −2 Vcc twice as high as the same voltage Vcc and outputs it to the output terminal 7.
［発明の効果］ 以上から本発明によれば、入力電圧の２倍の正の電圧
および負の電圧を得ることができ、しかもスイッチ素子
が７個で済むので、チップサイズを小さくすることがで
きるという利点かある。[Effects of the Invention] As described above, according to the present invention, a positive voltage and a negative voltage that are twice the input voltage can be obtained, and only seven switch elements are required, so that the chip size can be reduced. There is an advantage.
第１図は本発明の一実施例の昇圧回路の回路図、第２図
は従来の昇圧回路の回路図である。 ５……入力電源、６、７……出力端子。FIG. 1 is a circuit diagram of a booster circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional booster circuit. 5 ... input power supply, 6, 7 ... output terminal.
Claims (1)
１、第２のスイッチ手段と、片端に上記入力電圧が印加
される第２のコンデンサに上記第１のコンデンサの電圧
を充電する第３、第４のスイッチ手段と、第３のコンデ
ンサに上記第３のスイッチ手段を介して上記入力電圧を
充電する第５のスイッチ手段と、上記第１のコンデンサ
の電圧と上記第３のコンデンサの電圧を加算した電圧を
第４のコンデンサに充電する第６、第７のスイッチ手段
と具備し、上記第２のコンデンサの他端から上記入力電
圧の２倍の正の出力電圧を、上記第４のコンデンサから
上記入力電圧の２倍の負の出力電圧を得るようにしたこ
とを特徴とする昇圧回路。A first capacitor for charging an input voltage to a first capacitor; and a second switch for charging a voltage of the first capacitor to a second capacitor having one end to which the input voltage is applied. Third and fourth switch means, fifth switch means for charging the third capacitor with the input voltage via the third switch means, voltage of the first capacitor and voltage of the third capacitor A sixth and a seventh switch means for charging the fourth capacitor with the voltage obtained by adding the voltage, and outputting a positive output voltage twice the input voltage from the other end of the second capacitor to the fourth capacitor. Wherein a negative output voltage twice the input voltage is obtained from said capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2177291A JP2886281B2 (en) | 1990-07-06 | 1990-07-06 | Boost circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2177291A JP2886281B2 (en) | 1990-07-06 | 1990-07-06 | Boost circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0467769A JPH0467769A (en) | 1992-03-03 |
| JP2886281B2 true JP2886281B2 (en) | 1999-04-26 |
Family
ID=16028455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2177291A Expired - Fee Related JP2886281B2 (en) | 1990-07-06 | 1990-07-06 | Boost circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2886281B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008131838A (en) * | 2006-11-24 | 2008-06-05 | Stanley Electric Co Ltd | Power supply |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5262934A (en) * | 1992-06-23 | 1993-11-16 | Analogic Corporation | Bipolar voltage doubler circuit |
| JPH0828965B2 (en) * | 1992-09-02 | 1996-03-21 | 日本電気株式会社 | Voltage conversion circuit |
| US20050077950A1 (en) * | 2003-10-14 | 2005-04-14 | Robinson Curtis B. | Negative charge pump |
| CN103248220B (en) * | 2013-05-09 | 2016-01-20 | 广东宽普科技股份有限公司 | A kind ofly realize the charge pump being converted to twice negative voltage by positive voltage |
-
1990
- 1990-07-06 JP JP2177291A patent/JP2886281B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008131838A (en) * | 2006-11-24 | 2008-06-05 | Stanley Electric Co Ltd | Power supply |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0467769A (en) | 1992-03-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |