JPH05199116A - A/d converter - Google Patents

Abstract

PURPOSE:To attain the smaller size of the A/D converter and the A/D conversion at a higher speed. CONSTITUTION:A source of a P-channel MOS transistor(TR) TP is connected to a power supply VDD and its drain connects to a drain of an N-channel MOS TR TN and a comparator output Cout. A source of the N-channel MOS TR TN is connected to ground GND. Gates of the P-channel MOS TR TP and the N-channel MOS TR TN are connected to a comparator input Cin. Its prescribed logic threshold level is adjusted depending on the circuit parameter relating to the P-channel MOS TR and the N-channel MOS TR TN such as a gate length L, a gate width W or a voltage of the power supply VDD. The result of comparison between an analog input Ain inputted to the comparator input Cin and the logic threshold level is outputted to the comparator output Cout.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter for converting an analog input value into a digital value, and in particular, it is possible to achieve further miniaturization and high speed A / D conversion. The present invention relates to an A / D converter. Alternatively, the present invention relates to an A / D converter that includes a plurality of comparators and converts an analog input value into a digital value. Particularly, it suppresses the peak value of fluctuations in consumption current and also reduces power supply noise accompanying fluctuations in the consumption current. The present invention relates to an A / D converter that can be reduced.

[0002]

2. Description of the Related Art A / D converters have long been used in industrial fields such as measuring devices such as digital voltmeters and programmable power supplies. In recent years, A / D
The converter is also used in consumer products such as compact disc players and in special fields such as codecs for connecting a telephone to a digital line.

A home VTR (video tape recorder)
) For special playback and noise reduction on the device,
A capable of high-speed operation of 6 to 8 bits and 10 to 20 MHz
/ D converter is used. Relatively large capacity DR
With the recent development of digital technology such as the use of AM (dynamic random access memory) at relatively low cost, A / D converters are widely used in image processing devices and digital signal processors.
A / D converters used in such image processing devices and digital signal processors are required to operate at higher speed.

A flash type A / D converter is known as an A / D converter capable of high-speed operation. This flash type A / D converter is, for example, when this is an n-bit flash type A / D converter,
A total of (2 ⁿ -1) comparators are operated simultaneously and A
/ D conversion. These total (2 ⁿ −
1) To each of the comparators, reference reference voltages which are obtained by dividing the reference voltage by using ladder resistors in which a total of 2 ⁿ resistance elements having the same resistance value are connected are input respectively. .. Therefore, the individual comparators are
The comparison reference voltage input to each is compared with the analog signal voltage. Also, an encoded n-bit digital signal is output based on the comparison result by such a total of (2 ⁿ -1) comparators. According to such a flash type A / D converter, a digital signal corresponding to an input analog signal voltage can be obtained at a much higher speed than that of an integration type A / D converter or a successive approximation type A / D converter. it can.

Regarding the A / D converter capable of high-speed operation, Japanese Patent Publication No. 2-39136 discloses a technique related to what is called a two-step flash type A / D converter in recent years. The 2-step flash type A / D converter disclosed in Japanese Patent Publication No. 2-39136 is
For example, if this is a (m + n) -bit A / D converter, first a total of (2 ^m −1) comparators are used to perform A / D conversion corresponding to the upper m bits, and then the upper m bits are equivalent. Based on the result of the A / D conversion, a total of (2 ⁿ -1) other comparators are used to perform the A / D conversion corresponding to the lower n bits. Therefore, the total number of comparators used in the 2-step flash A / D converter is (2 ^{(m + n)} -2).
The number of individual flash-type A / D converters is significantly smaller than that of the general flash A / D converter described above.

Also, such a two-step flash type A
In recent years, a chopper type comparator has been used as a comparator of a / D converter. This chopper type comparator is a CMOS (complementary metal oxide se
miconductor) First, input the analog signal voltage to the capacitor connected in series to the input of the inverter. At this time,
By shorting its input and output of the CMOS inverter, a charge Q corresponding to the analog signal voltage is stored in the capacitor. After that, the input and output of the CMOS inverter are opened, and the capacitor to which the analog signal voltage is input is connected to the comparison reference voltage. At this time, the output of the CMOS inverter becomes an output according to the positive or negative value of the difference between the analog signal voltage and the comparison reference voltage.

Further, in Japanese Patent Laid-Open No. 1-259628, A / D
A technique of providing a correction input terminal in a comparator used in a converter, particularly in a comparator using a differential amplifier is disclosed. The comparator using the differential amplifier is a comparator widely used in the A / D converter together with the chopper type comparator described above. According to the technique disclosed in Japanese Patent Laid-Open No. 1-259628, there is no influence of variations in offset voltage,
It is possible to provide a highly accurate and high speed A / D converter.
For example, a MOS of a comparator using the differential amplifier
When a (metal oxide semiconductor) transistor is used, it is possible to reduce the problem of variation in offset voltage due to non-uniformity of threshold voltage of transistors used in a pair.

[0008]

However, the flash type A / D converter described above has an advantage that it can be converted at a much higher speed than the integration type A / D converter and the successive approximation type A / D converter. However, there is a problem that the number of comparators used is very large.

Further, the above-mentioned two-step flash type A / D
Even in the converter, the normal flash type A / D
Although the number of comparators used is smaller than that of converters, the number of comparators used is still large. For example, an 8-bit 2-step flash A / D converter requires a total of (2 ⁴ +2 ⁴ −2 = 30) comparators. Therefore, the two-step flash type A / D
The flash type A / D converter including the converter has a problem that the circuit size becomes large and the chip size becomes large when integrated into an integrated circuit.

The chopper type comparator used in the A / D converter has two voltages to be compared,
That is, the analog input value and the comparison reference voltage must be input alternately. Therefore, the conversion operation time is long. Also, the A / D conversion operation of the chopper type comparator performs operations such as charge charging according to the analog input value to the capacitor, charge charging according to the comparison reference voltage, and initialization by short-circuiting the charge. However, it also has a problem such as generation of noise. Further, since the chopper type comparator performs such a dynamic operation during A / D conversion, there is a problem that power consumption is relatively large.

On the other hand, a comparator using the differential amplifier used in the A / D converter has an operating speed of 2
It is about 0 to 30 MHz. Therefore, it cannot be used for the A / D converter that performs conversion operation at a higher speed.

The first invention of the present application was made in order to solve the above-mentioned conventional problems, and it is possible to further reduce the size and to perform high-speed A / D conversion. Is provided (hereinafter, referred to as a first purpose).

On the other hand, the second invention of the present application was made in order to solve the above-mentioned conventional problems, and suppresses the peak value of the fluctuation of the consumption current, and also reduces the power supply noise accompanying the fluctuation of the consumption current. It is an object to provide an A / D converter that can be reduced (hereinafter referred to as a second object).

[0014]

The first invention is an A / D converter for converting an analog input value into a digital value, and outputs a comparator output by a switching active element according to a comparator input and a predetermined logic threshold value. And at least one switching comparator whose logical threshold value is set within a possible range of the analog input value by adjusting a circuit parameter relating to the switching active element, and the analog input value is supplied to the comparator input. So that
Further, the first object is achieved by determining the digital value based on the output of the comparator (corresponding to claim 1).

In the A / D converter of the first aspect of the invention, the switching comparator has a CMO configuration.
With the configuration of the S inverter, the first object is achieved and the power consumption is further reduced (corresponding to claim 2).

In the A / D converter of the first invention, the switching comparator sets the logical threshold value by adjusting the power supply to the switching comparator.
The first object is achieved and various logical threshold values can be set more easily (corresponding to claim 3).

Further, in the A / D converter of the first aspect of the present invention, further, there is provided a plurality of threshold value variable switch groups for changing the logic threshold value of the switching comparator, and a plurality of threshold value variable switch groups. Each of the threshold variable switch elements of the variable threshold switch group is turned on / off to change the number of the switching active elements connected in parallel with each other, thereby changing the logical threshold value. By providing a switching active element group for changing the above, the first object is achieved and the logic threshold value is made variable (corresponding to claim 4).

On the other hand, in the second aspect of the invention, an A is provided which has a plurality of comparators and which converts an analog input value into a digital value.
In the / D converter, at least one of the plurality of comparators is provided with a comparison operation stop switch, and the operation time of at least a part of the plurality of comparators is controlled by controlling the on / off time of the comparison operation stop switch. The second object is achieved by shifting the above (corresponding to claim 5).

In the A / D converter of the second aspect of the invention, the on / off operation of the comparison operation stop switch operates according to the output of another comparator that determines the digital value of the higher-order bit than the comparator provided with the comparison operation stop switch. As a result, the second object is achieved, the conversion operation speed is further improved, and the power consumption is further reduced (corresponding to claim 6).

[0020]

First, the operation of the A / D converter of the first invention will be described.

As described above, the chopper type comparator generally used in the A / D converter and the comparator using the differential amplifier have problems to be improved. In order to solve such a problem, the first invention has been made by finding a comparator different from the conventional one.

In particular, the active element such as a transistor used is one in which the degree of driving is continuously operated when the output is driven (hereinafter referred to as an analog active element). In comparison, an active element used as a transistor, such as a logic gate of an inverter, is discontinuously turned on or off when its output is driven,
Alternatively, it is made by paying attention to the fact that the one using a switch which is switched substantially discontinuously (hereinafter referred to as a switching active element) is capable of a much higher speed operation.

For example, DTL (diode-transistor logi)
c) Logic gate, TTL (transistor-transistor logic)
) A logic gate, an ECL (emitter-coupled logic) logic gate, a CMOS logic gate or the like outputs a predetermined logic output by the switching active element such as a transistor according to its logic input and a predetermined logic threshold value. The first invention is based on a completely new viewpoint of using such a logic gate as a comparator. Such a logic gate using the switching active element, compared to a comparator using the differential amplifier composed of the analog active element,
Much faster operation is possible.

That is, in the first invention, as described above,
According to a logic input and a predetermined logic threshold value, a logic output is output by the switching active element such as a transistor, for example, for a logic gate, the logic input is a comparator input and the logic output is a comparator output. It is a switching comparator that compares a comparator input with the predetermined logic threshold value.

Further, the switching comparator is adapted to set the logic threshold value to a desired value by adjusting a circuit parameter relating to the switching active element. The value of the logical threshold value set by the switching comparator is set within the range of the analog input value that is input to the comparator input and is converted into a digital value. Adjustment of the circuit parameter relating to the switching active element in the switching comparator, which is performed to set the logical threshold value of the switching comparator, is, for example, an amplification factor β of the switching active element, an on-resistance of the switching active element, It can be adjusted by an off resistance of the switching active element, a threshold voltage of the switching active element, a voltage applied to the switching active element, and the like.

For example, when the switching active element is, for example, a MOS transistor, the amplification factor, the on resistance, and the off resistance of the switching active element can be adjusted by the gate width W and the gate length L thereof. is there.
Further, the voltage applied to the switching active element can be adjusted by the resistance value of the resistance element, or
It can also be adjusted by the voltage of the power supply supplied to the entire switching comparator including the switching active element. The first invention does not specifically limit such adjustment of the circuit parameter for setting the logical threshold value.

The switching comparator used in the first invention is not specifically limited to the first invention, and as described above, a predetermined switching active element is formed according to the input of the comparator and a predetermined logic threshold value. Anything that can output its comparator output by adjusting the circuit parameters
It is sufficient that the logical threshold can be set to a desired value within the range that the analog input value can take. For example, the configuration of the switching comparator may be that of a CMOS inverter. With such a CMOS inverter configuration, it is possible to reduce the power consumption of the switching comparator. The power consumption of the CMOS inverter is extremely low in the steady state where the output does not change. Further, regardless of whether the switching comparator is a CMOS inverter or not, a plurality of comparison reference voltages having different voltages, which require a general A / D converter such as the Japanese Patent Publication No. 2-39136, are required. The ladder resistance generated by dividing the reference voltage may be unnecessary in the first aspect of the invention, and in this case, the power consumption related to the ladder resistance is unnecessary. In comparison, in a comparator using the differential amplifier, the differential amplifier is generally provided with a constant current source, and steady power consumption occurs.

Further, as described above, there are various adjustments of the circuit parameter relating to the switching active element for setting the logic threshold value in the first embodiment, and the present invention limits this. is not. However, according to the setting of the logical threshold, by adjusting the power supply voltage supplied to the switching comparator according to the first aspect of the present invention, for example, fluctuation of the logical threshold due to variation in manufacturing process of the switching comparator is reduced. It is possible. Further, when such a switching comparator is formed into a semiconductor integrated circuit, the logic threshold value is adjusted by the voltage of the power supply, so that the plurality of switching comparators having different logic threshold values have different integrated circuit patterns. It is possible to create them as the same one. For example, the size and shape of transistors to be built can be made the same between the switching comparators, and it is possible to reduce the amount of work for designing an integrated circuit layout pattern.

Further, the switching comparator according to the first aspect of the present invention may be one in which the logic threshold value is variable. For example, a threshold variable switch group composed of a plurality of threshold variable switch elements may switch the circuit parameter for determining the logical threshold of the switching comparator to make the logical threshold variable. For example, by turning on / off each of the threshold variable switch elements of the threshold variable switch group, the number of the switching active elements connected in parallel to each other in the switching active element group constituted by the plurality of switching active elements is determined. The logical threshold value may be changed according to the change. According to the switching comparator of the first aspect of the invention, in which the logical threshold value is variable, it is possible to compare the analog input value to be converted into a digital value with a plurality of logical threshold values.
The number of comparators used in the A / D converter can be reduced.

The operation of the second invention will be described below.

In recent years, Bi CMOS (bipolar complement)
ary metal oxide semiconductor) Due to progress in process technology and the like, analog / digital mixed LSI (large scale integrated circuit) in which an analog circuit portion and a digital circuit portion are mixedly mounted on a single semiconductor chip has been widely used. .. In particular, the A / D converter is often integrated into one chip together with the digital circuit part because of the nature that the output is connected to the digital circuit. In recent years, the degree of integration of LSIs, including such analog / digital mixed LSIs, has been dramatically improved, and as a result, an increase in power consumption per chip has become a problem.

The second invention of the present application is particularly directed to the A / D
In order to reduce the power consumption of the converter,
In an A / D converter that includes a plurality of comparators and converts the analog input value into a digital value in order to reduce noise generated from the A / D converter, at least one of the comparators has a comparison operation stop switch. I am preparing. By thus providing the comparison operation stop switch, it is possible to shift the operation timing of the comparison operation of the comparator including the comparison operation stop switch compared to the comparison operation of the other comparators.

Therefore, A / with a plurality of comparators
In the D converter, the operation time of the specific comparator can be intentionally shifted to reduce the number of the comparators operating at the same time, and the peak of the power consumption of the A / D converter as a whole due to the power consumption of the comparators operating simultaneously. It is possible to reduce the value. Further, by reducing the number of the comparators that operate simultaneously in this way, it is possible to reduce the peak of noise that is generated due to the comparison operation of the comparators.

The A / D converter to be adapted according to the second aspect of the invention may be any one provided with a plurality of comparators, and is not particularly limited thereto. However, the effects of the second invention can be obtained, for example, with respect to the chopper type comparator, the switching comparator of the first aspect of the invention, or the like in which the current consumption is concentrated or the variation of the current consumption is concentrated during the comparison operation. It is more prominent.

In the second invention, the specific on / off timing of the comparison operation stop switch is not specifically limited in the second invention, but at least a part of the comparison operations of the plurality of comparators. It suffices that the comparison operation timings of the items are shifted. However, the comparison operation of the comparator provided with the comparison operation switch is
For example, in the case of starting according to the output of another comparator that determines the digital value of the higher order bit than the comparator, a digital value obtained by A / D converting the analog input value as in the third embodiment described later. It is possible to reduce the number of the plurality of comparators that actually perform the comparison operation until the above is determined, and it is possible to reduce the power consumption until the A / D conversion is completed. That is, it is possible to prevent the comparison operation of a certain comparator from being performed at all by the output of the comparator that determines the digital value of the higher-order bit. It is possible to reduce the overall power consumption.

[0036]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a first embodiment and a fourth embodiment to which the first invention is applied, and a second embodiment and a third embodiment to which the first invention and the second invention are applied. It is a circuit diagram of a switching comparator used.

In FIG. 1, the switching comparator to which the first invention is applied is shown.
The configuration of the switching comparator is that of a CMOS inverter, and the power consumption thereof is further reduced. The current consumption of the CMOS inverter mainly flows when the comparator output Cout changes.

In FIG. 1, the switching comparator includes a P-channel MOS transistor TP,
It is composed of an N-channel MOS transistor TN.

The source of the P-channel MOS transistor TP is connected to the power supply V _DD (or VRn), and the drain of the P-channel MOS transistor TP is connected to the comparator output Cout and the drain of the N-channel MOS transistor TN. .. That is, the drain of the N-channel MOS transistor TN is connected to the drain of the P-channel MOS transistor TP and also to the comparator output Cout. The source of the N-channel MOS transistor TN is
It is connected to ground GND. The P channel MO
Gate of S-transistor TP and N-channel MOS
The gates of the transistors TN are all connected to the comparator input Cin.

In the CMOS inverter shown in FIG.
The logical threshold V of the switching comparator of the configuration
_THIs the power supply voltage V_DDAnd the P-channel MOS transistor
The threshold of the transistor TP to V_TNAnd the N-channel MOS
Set the threshold of the transistor TN to V _TPThen, as in the following equation,
Can be represented.

V _TH = {V _DD + V _TN · β _R ^1/2 − | V _TP |} / {1 + β _R ^1/2 } (1)

[0043] In the above equation (1), beta _R is the ratio of the amplification factor beta _N and amplification factor beta _P of the P-channel MOS transistor TP of the N-channel MOS transistor TN, are as follows is there.

Β _R = β _N / β _P (2)

Further, the N-channel MOS transistor T
Both the amplification factor β _{N of N} and the amplification factor β _P of the P-channel MOS transistor TP can be calculated by the following formula for obtaining the amplification factor β.

Β = μ · C _ox · W / L (3)

In the equation (3), μ is carrier mobility, C _ox is the gate capacitance of the MOS transistor, W is its gate width, and L is its gate length.

As shown in these equations (1) to (3), the logical thresholds of the switching comparator by the CMOS inverter shown in FIG. 1 are listed next to those of the circuit shown in FIG. It can be set by adjusting such circuit parameters.

(1) Adjustment of the power supply voltage V _DD (see formula (1)) (2) Adjustment of the threshold V _TN of the N-channel MOS transistor TN or adjustment of the threshold V _TP of the P-channel MOS transistor TP (See the formula (1)) (3) By adjusting at least one of the adjustment of the gate capacitance C _ox , the adjustment of the gate width W, and the adjustment of the gate length L of the N-channel MOS transistor TN. (See Formulas (1) to (3) above) (4) At least one of adjustment of the gate capacitance _Cox , adjustment of the gate width W, and adjustment of the gate length L of the P-channel MOS transistor TP. By one adjustment (see the above formulas (1) to (3))

As described above, according to the switching comparator using the CMOS inverter as shown in FIG. 1, according to the comparator input Cin and the predetermined logic threshold V _TH , the switching logic element,
That is, the P-channel MOS transistor TP and the N-channel
The comparator output Cout can be output by the channel MOS transistor TN. Further, as described using the equations (1) to (3), the logic threshold value V _TH can be set within a range that the analog input value Ain input from the comparator input Cin can take. FIG. 1
The CMOS inverter as shown in FIG. 1 can operate at a speed of about 1 GHz at present. Therefore,
According to the first switching comparator embodiment, it is possible to provide a comparator that can be used in an A / D converter that can perform high-speed A / D conversion. In addition, the CMOS type inverter as shown in FIG.
Especially, the power consumption is small, and especially the comparator input Cin
When the signal input to is in a steady state, its power consumption is almost zero.

The switching comparator according to the present invention is the CMOS as shown in FIG.
The present invention is not limited to the inverter, and may be a CMOS logic gate having another circuit configuration, the TTL logic gate, the DTL logic gate, or the ECL.
It may be a logic gate or the like. Alternatively, the M of the ED (enhancement-depletion) configuration as shown in FIG.
It may be an OS logic gate (inverter).

The MOS inverter shown in FIG.
The N-channel MOS transistor TND is used as an enhancement transistor, and the N-channel MOS transistor TNL is
It is used as a load device which is a depletion transistor with its gate and source short-circuited. As shown in this FIG.
The logical threshold value V _TH of the OS inverter is the threshold value of the N-channel MOS transistor TND set to V _TND ,
If the threshold value of the channel MOS transistor TNL is V _TNL , it can be expressed by the following equation.

V _TH = {V _TND · β _R ^1/2 − | V _TNL │} / {1 + β _R ^1/2 } (4)

In the equation (4), β _R is the amplification factor β _ND of the N-channel MOS transistor TND,
Amplification factor β _NL of the N-channel MOS transistor TNL
And the ratio is as follows.

Β _R = β _ND / β _NL (5)

The amplification factor β _ND of the N-channel MOS transistor TND and the amplification factor β _NL of the N-channel MOS transistor TNL shown in the above equation (5).
Can be calculated by the equation (3) for obtaining the amplification factor β.

3 and 4 are used in FIGS. 7 to 10, which will be described later, showing the entire switching comparator shown in FIG. 1 or the entire switching comparator shown in FIG. It is a diagram showing a symbol.

In FIG. 3, the switching comparator designated by reference numeral Cn is shown. Also, the comparator input Cin, the comparator output Cout, the power supply V _DD (or VRn
) And its ground GND are shown. On the other hand, in FIG. 4, the power source V _DD and the ground GND are not shown, and the comparator input Cin and the comparator output Cout of the comparator Cn are shown.

FIG. 5 is a circuit diagram of a power supply circuit for generating a plurality of power supplies having different voltages to be supplied to the plurality of comparators of the first to third embodiments.

In FIG. 5, the power supply circuit is composed of a total of 256 resistance elements R0 to R255 and a total of 255 power supply buffers B1 to B255.

A total of 256 resistance elements R0 to R25
5 are sequentially connected in series. Terminal VR at the extreme ends
A predetermined reference voltage Vs is applied between T and the terminal VRB. The plus of the reference voltage Vs is connected to the terminal VRT, and the reference voltage Vs is connected to the terminal VRB.
The minus of is connected. Further, a total of 255 comparative reference voltages V1 to V255 are taken out from a total of 255 series connection points of the total of 256 resistance elements R0 to R255 whose resistance values are equal to each other.

A total of 255 power supply buffers B1 to B
The reference voltages V1 to V255
Has been entered. These power supply power supply buffers B1 and B2
Each of 55 is a power supply VR1 of a voltage corresponding to the comparison reference voltages V1 to V255 input thereto.
VR255 is output. These power supplies VR1 and VR2
55 is supplied as a power source to each of a total of 255 switching comparators C1 to C255, which will be described later, used in each of the first to third embodiments. These power supply buffers B1 to B255 are constant voltage power supplies that output the power supplies VR1 to VR255, respectively, according to the comparison reference voltages V1 to V255 input to them.

FIG. 6 is a circuit diagram of a first example of the power supply buffer used in the power supply circuit.

In FIG. 6, one power supply buffer Bn having the total of 255 power supply buffers B1 to B255 shown in FIG. 5 is shown. The power supply buffer Bn has a buffer 30n which is a differential amplifier having a plus input and a minus input, and outputs a power supply of a voltage according to the voltage difference between the plus input and the minus input. In the buffer 30n, the comparison reference voltage Vn is input to the plus input, and the output is the power supply VRn. In the buffer 30n, the output voltage of the power supply VRn is negatively fed back to its negative terminal. Therefore, the power supply buffer Bn shown in FIG. 6 has the comparison reference voltage Vn.
The power supply VRn having a voltage equal to n is supplied.

FIG. 7 is a circuit diagram of a second example of the power supply buffer used in the power supply circuit.

In FIG. 7, the power source power source buffer Bn
Is composed of a buffer 30n and an inverter 32n.

The buffer 30n is the same as the buffer 30n described with reference to FIG. The buffer 3
The inverter 32n is inserted in the negative feedback loop of 0n. The input and output of the inverter 32n are short-circuited, which is connected to the negative input of the buffer 30n. The power supply VRn output from the buffer 30n is supplied to the power supply of the inverter 32n. Since the input and output of the inverter 32n are connected, the voltage of the output of the inverter 32n becomes the logic threshold voltage V _{TH of the} inverter 32n. Therefore,
The negative input of the buffer 30n is supplied with the logical threshold voltage V _{TH of the} inverter 32n when the voltage of the power supply VRn is supplied to the inverter 32n.

Therefore, in the power supply buffer Bn shown in FIG. 7, the relation between the comparison reference voltage Vn and the logical threshold voltage V _TH of the inverter 32n is as follows.

Vn = _VTH (6)

In the switching comparator shown in FIG. 1 and the switching comparator shown in FIG. 2, the logic threshold V _TH is _equal to the power supply V
By supplying Rn, it is set to be equal to Vn, and it is possible to prevent variations in the logical threshold of the inverter due to variations in circuit parameters.

FIG. 8 is an overall circuit diagram of the A / D converter of the first embodiment to which the first invention is applied.

In FIG. 8, a total of 255 switching comparators C1 to C255 used in the A / D converter 1 are those to which the first invention described above with reference to FIG. 1 is applied. There is. Also, the A
The overall configuration of the / D converter 1 is a flash type A / D converter that performs A / D conversion of the analog input value Ain into 8-bit digital values D1 to D8.

The A / D converter 1 mainly comprises a total of 255 switching comparators C1 to C25.
5 and an encoder 2.

The supply power sources VR1 to VR255 output from the power supply circuit described above with reference to FIG. 5 and having different voltages are supplied to the total of 255 switching comparators C1 to C255 as power supplies. .. These switching comparators C1 to C25
5, the circuits are the same as each other, and the voltages of the supplied power supplies VR1 to VR255 are different from each other. Further, since the respective power supplies VR1 to VR255 supplied in this way are different from each other, these switching comparators C1 to C255 are
The respective thresholds V _{TH1 to} V _TH255 are different from each other.

The total of 255 switching comparators C1 to C255 have their respective thresholds V _TH1 to V _TH1 .
_They are arranged in parallel in ascending order of V _TH255 value. or,
These threshold values V _{TH1 to} V _TH255 are the range that the analog input value Ain can take, that is, the range between the lower limit value Amin and the upper limit value Amax of the analog input value Ain (hereinafter referred to as full scale). 8-bit resolution of digital values D1 to D8 output from the A / D converter 1 (2 ⁸ =
256). For example,
Threshold value V _{THn of} the nth switching comparator Cn
Is as shown in the following equation (n is “1” to “25
5 "integer).

V _THn = Amin + n × (Amax-Amin) / 256 (7)

In the first embodiment, the threshold V _TH1 of each of the switching comparators C1 to C255 is set.
To V _TH255 are mainly power supplies VR1 to VR supplied to these switching comparators C1 to C255.
It is set by the voltage of 255. However, the thresholds V _{TH1 to} V _TH255 of the switching comparators C1 to C255 may be set by other means, for example, the P channel MOS transistor TP and the P channel MOS transistor TP shown in FIG. N
It may be set by the gate width W or the gate length L of the channel MOS transistor TN ((1) above).
Formula- (3) Formula reference).

In this way, the threshold values V _{TH1 to} V _TH255
The analog input value Ain held by an input buffer, a sample-and-hold circuit or the like (not shown) is input to the comparator inputs Cin of all the switching comparators C1 to C255 which are set respectively. Moreover, these switching comparators C1 to
The comparator output Cout of each of C255 is
It is independently input to the encoder 2.

Further, these switching comparators C1
To C255, the analog input value Ain input to the comparator input Cin is the threshold value V
When it is smaller than _{TH1 to} V _TH255 , each comparator output Cout outputs a logical value "1". On the other hand, each of the switching comparators C1 to C255, when the inputted analog input value Ain is larger than the respective threshold value V _{TH1 to} V _TH255 ,
A logical value "0" is output from each of the comparator outputs Cout.

The encoder 2 is independently input to the switching comparators C1 to C255.
Is binary-coded into an 8-bit binary number, and digital values D1 to D8 are output.

For example, when the analog input value Ain is the lower limit value Amin, the switching comparator C1
~ All the comparator outputs Cout of C255 are "1"
Then, the encoder 2 converts this into a binary code, and the digital values D1 to D8 are all "0".
Further, when the analog input Ain is the value of the upper limit value Amax, all the comparator outputs Cout of the switching comparators C1 to C255 become "0", and the encoder 2 converts this into a binary code, and the digital values D1 to D8. Are all "1". Further, the magnitude of the analog input value Ain is the lower limit value Amin and the upper limit value Ama.
Within the range of x, as the value of the analog input value Ain increases, the switching comparators C1 to C2
The output of each of the comparator outputs Cout of 55 sequentially becomes “0” from the switching comparator C1 side to the switching comparator C255 side, and the other comparator output Cout is output.
Outputs "1".

For example, in the case of a certain value of the analog input value Ain, a total of 23 switching comparators C1 to C23 corresponding to the value output a logical value "0", and the other switching comparators C24 to C24. C25
5 outputs a logical value "1". Further, at this time, the encoder 2 has the switching comparators C1 to C2.
The output of such a logical value of 55 is coded to output the digital values D1 to D8 as shown in the following equation.

D8 = D7 = D6 = D4 = 0 (8a) D5 = D3 = D2 = D1 = 1 (8b)

That is, the digital values D1 to D8 represented by the equations (8a) and (8b) are "00" in binary.
010111 ", which is" 23 "in decimal.

[0085] As described above, according to the first embodiment, the respective threshold V _{TH 1} ~V _TH255 of the switching comparator C1~C255 total 255 of the first invention is applied, the value of each other Different values can be set as shown in the above formula (7), and a flash type A / D converter can be configured. These switching comparators C1 to C255 can perform higher-speed comparison operation in addition to the comparator using the differential amplifier and the chopper type comparator. Therefore, according to the first embodiment, it is possible to further improve the conversion speed of the flash type A / D converter that is originally capable of high-speed A / D conversion. Further, the switching comparators C1 to C255 can be downsized as compared with the comparator using the differential amplifier or the chopper type comparator. Therefore, according to the first embodiment, the entire A / D converter 1 is provided. It is possible to reduce the occupying area, and it is possible to improve the degree of integration.

According to the estimation by the inventors, the occupied area of the A / D converter of the first embodiment is 1/100, as compared with the A / D converter of the same number of bits using the conventional chopper type comparator. It can be reduced to about 2 and its A / D conversion speed can be expected to be improved to about 5 to 10 times.

FIG. 9 is an overall circuit diagram of the A / D converter of the second embodiment to which the first invention and the second invention are applied.

In the second embodiment shown in FIG. 9, a total of 255 switching comparators Cn shown in FIG. 1 to which the first invention is applied are used. Further, the second invention is applied to the A / D converter 1 as an entire configuration, and improvements such as reduction of fluctuations in power consumption and noise of the conventional flash type A / D converter have been achieved. It is a thing.

The A / D converter 1 of the second embodiment
Is mainly a total of 255 of the switching comparators C1 to C255 and a total of 254 N-channel MOs corresponding to the threshold variable switch element of the second invention.
It is composed of S transistors T1 to T254 and an encoder 2. The switching comparators C1 to C255 and the encoder 2 used in the second embodiment are the same as those of the first embodiment described above with reference to FIG. And operates similarly.

The feature of the second embodiment is that the comparator input C of each of the 254 switching comparators C1 to C254 in total is different from that of the first embodiment.
between the N-channel MOS transistors T1 to T254 and the analog input value Ain terminal, respectively.
Are connected in series for each source and drain. Further, the gates of the N-channel MOS transistors T1 to T254 are connected to the comparator output Cout of the switching comparators C2 to C255 which are shown one above in FIG. For example, the nth N
Regarding the channel MOS transistor Tn, the (n +
1) th switching comparator C (n + 1)
Of the comparator output Cout.

Therefore, in the second embodiment, the n-th switching comparator Cn operates when the output of the (n + 1) -th switching comparator C (n + 1) has the logical value "1", that is, Only when the magnitude of the analog input value Ain is smaller than the threshold value V _{TH (n + 1) of the (n + 1) th} switching comparator C _{(n + 1)} , the nth N-channel MOS When the transistor Tn is turned on, it becomes a driving state. Therefore, in the second embodiment, the comparison operation of the nth switching comparator Cn is at least the (n + 1) th.
The second switching comparator C (n + 1) is operated after completion of the comparison operation, and even when a total of 255 switching comparators C1 to C255 are operated, the operation timing of these is the threshold value V
_The order is from _{TH1 to} V _TH255 . At least the minute time operation timing is shifted, and the comparison operations are sequentially performed.

Therefore, the through currents of these switching comparators C1 to C255 of the CMOS inverter are not concentrated at one time, the peak current value of the power supply current due to the through current is suppressed, the fluctuation of the power supply voltage is reduced, and the power supply voltage is reduced. It is possible to reduce noise. Further, depending on the value of the analog input value Ain, only the required number of the switching comparators C1 to C255 are compared, and the average power consumption of the A / D converter 1 can be reduced. It is possible.

In the second embodiment, even if the comparison operations of the switching comparators C1 to C255 are sequentially operated as described above, the individual comparison operations of the switching comparators C1 to C255 should be performed at high speed. Therefore, the A of the A / D converter 1 can be
There is no significant delay in the overall processing speed of the / D conversion.

In the second embodiment, when the nth switching comparator Cn determines that the analog input value Ain is larger than the threshold value V _THn , other switching thereafter. The comparison operation of the comparators C1 to C (n-1) is not performed, and the comparator output Cout of these switching comparators C1 to C (n-1) becomes indefinite. Therefore, the encoder 2 takes such points into consideration. That is, in the encoder 2, the output of the (n + 1) th switching comparator C (n + 1) is a logical value "1".
The output of the nth switching comparator Cn next to this is a logical value "0", and the logical value "1" and the logical value "0" are arranged at the most of the above. The one on the switching comparator C255 side (the side opposite to the switching comparator C1) is determined, and based on this, the 8-bit digital values D1 to D8 are encoded.

FIG. 10 is an overall circuit diagram of the A / D converter of the third embodiment to which the first invention and the second invention are applied.

A of the third embodiment shown in FIG.
The / D converter 1 includes the switching comparator C to which the first invention is applied, which is described above with reference to FIG.
It has a total of 7 n. Further, the third embodiment is a 3-bit flash type A / D converter to which the second invention is applied as a whole configuration. The A / D converter converts the analog input Ain into the 3-bit digital values D1 to D3.

The A / D converter 1 of the third embodiment is
Mainly, a total of 7 switching comparators C
1 to C7, encoder 2, and a total of 7 N channels M
It is composed of OS transistors T1 to T7 and a total of three inverters 3 to 5.

The switching comparators C1 to C7
The power supplies VR1 to VR7 generated by the power supply circuit shown in FIG. 11 are supplied to each of them. The power supply circuit used in the third embodiment shown in FIG. 11 is composed of a total of eight resistance elements R0 to R7 having the same resistance value and a total of seven power supply buffers B1 to B7. The power supply buffers B1 to B7 are the same as those shown in FIG. 5, and either the one shown in FIG. 6 or the one shown in FIG. 7 is used.

In FIG. 10, a total of seven switching comparators C1 to C7 have the same internal circuit as shown in FIG.
The integrated circuit layout patterns are also the same. On the other hand, these switching comparators C
1 to C7, respectively, in order from the power supply VR1 to be supplied from the power supply circuit described above with reference to FIG.
The power supplies of VR7 having different voltages are supplied. Therefore, the thresholds V _{TH1 to} V _{TH of the} seven switching comparators C1 to C7 in total, respectively.
_TH7 has different values. The threshold value V _THn of the nth switching comparator Cn can be expressed by the following equation (n is an integer of “1” to “7”).

V _THn = Amin + n × (Amax-Amin) / 8 (9)

In FIG. 10, the analog input value Ain is input to the comparator input Cin of the switching comparator C4. Further, between the comparator input Cin of each of the six switching comparators C1 to C3 and C5 to C7 and the terminal of the analog input value Ain, the N channel MOS transistors T1 to T3 and T5 are sequentially arranged. ~ T7 are connected in series for each source and drain.

Regarding the switching comparator C4 whose threshold value V _TH4 is half the full scale of the lower limit value Amin and the upper limit value Amax, the output of the switching comparator C4 is the gate of the N-channel MOS transistor T2. And the input of the inverter 3 are connected. The output of the inverter 3 is connected to the gate of the N-channel MOS transistor T6. Therefore, when the value of the analog input value Ain is smaller than the threshold value V _TH4 , the switching comparator C2 performs the comparison operation. On the other hand, when the value of the analog input value Ain is larger than the threshold value V _TH4 , the switching comparator C6 performs the comparison operation.

Further, the switching comparator C2
The output of is connected to the gate of the N-channel MOS transistor T1 and the input of the inverter 4.
The output of the inverter 4 is connected to the gate of the N-channel MOS transistor T3. Therefore, when the value of the analog input value Ain is smaller than the threshold value V _TH2 , the switching comparator C1 performs the comparison operation. On the other hand, if the analog input value Ain is the threshold value V
When it is larger than _TH2 , the switching comparator C3 performs a comparison operation.

On the other hand, the switching comparator C6
For, the output is connected to the gate of the N-channel MOS transistor T5 and the input of the inverter 5. The output of the inverter 5 is connected to the gate of the N-channel MOS transistor T7.
Therefore, the value of the analog input value Ain is the threshold value V _{TH 6}
If it is smaller than the above, the switching comparator C5 performs a comparison operation. On the other hand, the analog input value Ain
Is larger than the threshold value V _TH6 , the switching comparator C7 performs a comparison operation.

The encoder 2 converts the inverted value of the output of the switching comparator C4 into MSB (most signi
The digital value of ficant bit is D3. That is, when the logical value of the output of the switching comparator C4 is "1", the logical value of the digital value D3 is "0", and when the logical value of the output of the switching inverter C4 is "0", the digital value is The logical value of D3 is "1".

Further, when the logical value of the output of the switching comparator C4 is "1", the encoder 2 outputs the inverted value of the output of the switching comparator C2 as the logical value of the digital value D2. On the other hand, when the logical value of the output of the switching comparator C4 is "0", the inverted value of the output of the switching comparator C6 is set as the logical value of the digital value D2.

Further, when the logical value of the output of the switching comparator C4 is "1" and the logical value of the output of the switching comparator C2 is also "1", the encoder 2 outputs the value of the switching comparator C1. The inverted value of the output is the LSB (least significant bi
Let t be the digital value D1. Further, the logical value of the output of the switching comparator C4 is "1",
When the logical value of the output of the switching comparator C2 is "0", the inverted value of the output of the switching comparator C3 is set to the digital value D1 of LSB.
Is a logical value of.

On the other hand, when the logical value of the output of the switching comparator C4 is "0" and the logical value of the output of the switching comparator C6 is "1", the encoder 2 outputs the value of the switching comparator C5. The inverted value of the output is the logical value of the digital value D1 of LSB. Further, when the logical value of the output of the switching comparator C4 is "0" and the logical value of the output of the switching comparator C6 is also "0", the inverted value of the output of the switching comparator C7 is set to the LSB. And the logical value of the digital value D1.

In the A / D converter of the third embodiment as described above, the switching comparators C1 to C are used.
3 and C5 to C7 are respectively provided with the N-channel MOS transistors T1 to T3 and T5 to T7 corresponding to the comparison operation stop switch of the second invention. or,
In the third embodiment, these N-channel MOS transistors T1 to T3, T corresponding to the comparison operation stop switch are
5 to T7 are digital values D determined by the corresponding comparators C1 to C3 and C5 to C7, respectively.
Other switching comparators C2, C4, C6 that determine the digital values D2 to D3 of the upper bits than 1, D2
It operates according to the output of. Therefore, after the analog input value Ain is supplied, finally the digital values D1 to
In the period until each value of D3 is determined,
Of the seven switching comparators C1 to C7 in total, the one performing the comparison operation is the analog input value Ain.
There are only a predetermined total of three items determined in accordance with.

That is, immediately after the analog input value Ain is input, first, the switching comparator C4
Only the comparison operation is performed. In the next second step, only one of the switching comparators C2 and C6 performs the comparison operation. In the subsequent third stage, only one of the switching comparators C1, C3, C5 and C7 performs the comparison operation. By the operation of only three of the switching comparators C1 to C7 from the first stage to the third stage,
Values of the digital values D1 to D3 are determined.

As described above, according to the third embodiment, when the analog input value Ain is A / D-converted, only a total of three switching comparators C1 to C7 perform a comparison operation. Power consumption can be reduced. Further, the switching comparator C
Of the 1 to C7, the three that perform the comparison operation do not perform the comparison operation at the same time, and their operation timings are shifted by a minute time. Therefore, the peak value of the consumption current in the third embodiment is suppressed, the fluctuation amount of the consumption current is also reduced, and the power supply noise is also reduced accordingly. Further, even if the operation timing of the comparison operation is shifted in this way, the comparison operation of these switching comparators C1 to C7 is performed at a relatively high speed, so that it is necessary for the A / D conversion of the entire A / D converter 1. The processing time is not unnecessarily extended.

FIG. 12 is a circuit diagram of the A / D converter of the fourth embodiment to which the first invention is applied.

A of the fourth embodiment shown in FIG.
The / D converter 1 includes a switching comparator 10 including a total of m P-channel MOS transistors P1 to Pm and a total of one N-channel MOS transistor N1. The switching comparator 10
Is a configuration of a CMOS inverter, to which the first invention is applied.

Further, the A / D converter 1 includes the switching comparator 10, the threshold variable switch group ST composed of a total of m N-channel MOS transistors ST1 to STm, the controller 11 and the inverter 12. It is configured.

The switching comparator of the fourth embodiment.
In the emulator 10, a total of m P-channel MOS
The sources of all the transistors P1 to Pm are electrically charged.
Source V _DDConnected to each drain
It is connected to the output Cout and each drain is
Note Connect to the drain of N-channel MOS transistor N1.
Has been continued. Also, these P-channel MOS transistors
The gates of each of the switches P1 to Pn are provided with the variable threshold switch.
The N-channel MOS corresponding to each of the group ST
Via the source-drain of the transistors ST1 to STm
And is connected to the comparator input Cin.

Therefore, for example, when the N-channel MOS transistor ST1 is turned on, the P-channel MOS transistor is turned on.
The gate of the transistor P1 has the comparator input Cin
It becomes conductive. Further, for example, when the N-channel MOS transistor ST2 is turned on, the P-channel MO transistor is turned on.
The gate of the S transistor P2 is the comparator input C.
It becomes conductive in.

On the other hand, in the switching comparator 10, the drain of the N-channel MOS transistor N1 is connected to all the sources of the P-channel MOS transistors P1 to Pm, and is also connected to the comparator output Cout. There is. The source of the N-channel MOS transistor N1 is connected to the ground GND, and the gate thereof is connected to the comparator input Cin.

The switching comparator 10 of the fourth embodiment as described above includes the individual N-channel MOS transistors ST1 to ST of the threshold variable switch group ST.
By turning on / off m, a total of m P channel MOs
One of the gates of the S transistors P1 to Pm can be selectively turned on to the comparator input Cin. This makes it possible to change the number of P-channel MOS transistors P1 to Pm connected to the comparator input Cin of each gate.

Therefore, in such a switching comparator 10, the threshold variable switch group ST
The individual N-channel MOS transistors ST1 to ST1
The logic threshold value V _TH of the switching comparator 10 can be changed by turning on and off STm. This is a total of n P-channel MOS transistors P1 to P1 connected in parallel with respect to source and drain.
If Pn is hypothesized as one composite P-channel MOS transistor P, the device parameter of the P-channel MOS transistor P is changed by turning on / off each of the N-channel MOS transistors ST1 to STn of the threshold variable switch group ST. Can be thought of as being done. For example, in the P-channel MOS transistor P, it can be considered that the virtual gate width W is changed.

According to the switching comparator 10, the controller 11 sets the desired logical threshold value V _TH by turning on / off the individual N-channel MOS transistors ST1 to STm in the threshold variable switch group ST. can do. Further, the switching comparator 10 can compare the logic threshold value V _TH with the analog input value Ain.

Further, in the A / D converter 1 of the fourth embodiment, one switching comparator 10 in total is provided.
Is input to the controller 11 through the inverter 12 for waveform shaping. Also, the controller 1
1 turns on / off the individual N-channel MOS transistors ST1 to STn of the threshold variable switch group ST in accordance with the input from the inverter 12.
During this time, MSB to LSB from digital output Dout
In that order, the digital values D1 to D3 are output. For example, the operation of the controller 11 can be the operation of a conventional successive approximation A / D converter or the operation of a conventional follow-up comparison A / D converter.

For example, in the case where the operation of the A / D converter 1 is the operation of the successive approximation A / D converter by the controller 11, first, as the first step,
The N of the threshold variable switch group ST is set so that the switching comparator 10 can compare the analog input value Ain with the analog input value Ain at the logical threshold value V _{TH that} is 1/2 of the full scale. Channel MO
The S transistors ST1 to STn are individually turned on and off. Based on the comparison result of the switching comparator 10 at this time, that is, the digital output Dout, the controller 11 controls the M of the digital values D1 to Dn.
SB can be obtained.

Next, in the second step, based on the comparison result of the first step, the controller 11 sets the threshold value V _TH of the switching comparator 10 to a value of ¼ of the full scale, or 3/4 of the full scale
_Is set, and the threshold value V _TH of the switching comparator 10 is set by _turning on and off the threshold value variable switch group ST based on the determination. The comparison result of the switching comparator 10 based on the threshold value V _TH set in this way is the digital value D1.
.. Dn is output from the digital output Dout as the second bit logical value from the MSB.

The same processing is performed for the three stages and thereafter. During such a series of processing, MS is sequentially output from the digital output value Dout by a total of three logical values.
From B to LSB, the digital values D1 to D3 of the A / D conversion result of the analog input value Ain can be obtained.

As described above, according to the fourth embodiment, the A / D conversion of the analog input value Ain can be performed by only one of the switching comparators 10,
It is possible to reduce the number of required elements and improve the degree of integration. In addition, the switching comparator 1
0 can operate at higher speed than the conventional comparator. Therefore, the A / D converter 1 of the fourth embodiment is
Is faster than the conventional successive approximation A / D converter and the conventional follow-up comparison A / D converter.

In the fourth embodiment, the switching comparator 10 having a CMOS inverter structure is used.
The P-channel MOS transistor P connected to the power supply V _DD side is operated by the threshold variable switch group ST to change the logic threshold V _TH . However, the N-channel MOS transistor N1 is
It is also possible to form a composite using a large number of N-channel MOS transistors, and switch this by the same one as the threshold variable switch group ST, thereby changing the logical threshold V _TH . Alternatively, the P-channel M of the switching comparator 10 configured as a CMOS inverter is used.
Both the OS transistor and the N-channel MOS transistor may be combined.

The first to third embodiments described above are used.
In the embodiment, the switching comparators C1 to C1
When each output of C255 is input to the encoder 2, one or more inverters for waveform shaping may be provided in this path. As a result, the encoder 2
It is possible to more stably perform the coding operation in.

Further, in the second and third embodiments, the switching comparator to which the first invention is applied is used. However, in the second and third embodiments, other comparators such as the chopper type comparator and the comparator using the differential amplifier may be used.

In the first to fourth embodiments, the switching comparator having the CMOS inverter configuration described with reference to FIG. 1 is used, but the switching comparator having another configuration, for example, the configuration shown in FIG. Alternatively, an ED type MOS inverter as shown in 2 may be used.

[0130]

As described above, according to the first aspect of the present invention, it is possible to further reduce the size and to increase the high speed A /
An excellent effect that an A / D converter capable of D conversion can be provided can be obtained. Also, the second
According to the invention, the peak value of fluctuations in current consumption is suppressed, and
It is possible to obtain an excellent effect that it is possible to provide an A / D converter capable of reducing the power supply noise accompanying the fluctuation of the consumed current.

[Brief description of drawings]

FIG. 1 is a first embodiment to which the first invention of the present application is applied, a second embodiment and a third embodiment to which the first and second inventions of the present application are applied, and a first to which the first invention is applied. A of 4 Examples
Circuit diagram of switching comparator used in D converter

FIG. 2 is a circuit diagram of a modification of the switching comparator.

FIG. 3 is a first symbol diagram showing the switching comparator.

FIG. 4 is a second symbol diagram showing the switching comparator.

FIG. 5 is a circuit diagram of a power supply circuit used in the first embodiment and the second embodiment.

FIG. 6 is a first power supply buffer used in the power supply circuit.
Circuit diagram showing an example

FIG. 7 is a second power supply buffer used in the power supply circuit.
Circuit diagram showing an example

FIG. 8 is an overall circuit diagram of the A / D converter of the first embodiment.

FIG. 9 is an overall circuit diagram of the A / D converter of the second embodiment.

FIG. 10 is an overall circuit diagram of the A / D converter of the third embodiment.

FIG. 11 is a circuit diagram of a power supply circuit used in the third embodiment.

FIG. 12 is an A / A diagram of a fourth embodiment to which the first invention is applied.
Overall circuit diagram of D converter

[Explanation of symbols]

1 ... A / D converter 2 ... Encoder 10, Cn, C1-C255 ... Switching comparator 12 ... Inverter 30n ... Buffer (differential amplifier) 32n ... Analog inverter Ain ... Analog input value Bn ... Power supply buffer Cin ... Comparator input Cout ... Comparator Outputs D1 to D8 ... Digital values R0 to R255 ... Resistor elements SR1 to SRn ... N channel MOS transistors (threshold variable switch elements) TN, TND ... N channel MOS transistors (switching active elements) TNL ... N channel MOS transistors (load devices) TP, P1 to Pm ... P channel MOS transistor (switching active element) T1 to T254 ... N channel MOS transistor (comparison operation stop switch) V1 to V255 ... Comparison reference voltage VR1 to VR255 ... Power supply of the switch ring comparator

Claims (6)

[Claims] 1. A for converting an analog input value into a digital value
In the / D converter, according to the comparator input and the predetermined logic threshold value, the switching active element outputs the comparator output, and
Further, by adjusting a circuit parameter relating to the switching active element, at least one switching comparator having the logical threshold value set within a range that the analog input value can take is provided, and the analog input value is supplied to the comparator input. An A / D converter characterized by being introduced and determining the digital value based on the output of the comparator. 2. The A / D converter according to claim 1, wherein the configuration of the switching comparator is a configuration of a CMOS inverter. 3. The A / D converter according to claim 1, wherein the switching comparator has the logic threshold value set by adjusting a power supply to the switching comparator. 4. The method according to claim 1 or 2,
Further, the threshold variable switch group for changing the logic threshold value of the switching comparator is composed of a plurality of threshold variable switch elements, and a plurality of the switching active elements. When the threshold variable switch element is turned on and off, the number of the switching active elements connected in parallel to each other is changed, and thereby the switching threshold value is changed to thereby change the logical threshold value. Is an A / D converter. 5. An A / D converter including a plurality of comparators for converting an analog input value into a digital value, comprising a comparison operation stop switch provided in at least one of the comparators, An A / D converter characterized in that the operation timing of at least a part of the plurality of comparators is shifted by controlling the on / off timing. 6. The on / off operation of the comparison operation stop switch according to claim 5, wherein the on / off operation of the comparison operation stop switch operates according to an output of another comparator that determines a digital value of a higher-order bit than a comparator provided with the comparison operation stop switch. / D converter.