JP2004201197A - Drive circuit and communication equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive circuit capable of keeping the output amplitude constant by suppressing fluctuation and capable of reducing the current consumption, and a communication equipment using the same. <P>SOLUTION: The drive circuit has first and second transistors MN11, MN12 wherein a differential voltage is supplied to their gates, a current source US11 connected to sources of the first and second transistors MN11, MN12, load resistors R11, R12 and capacitors C11, C12 connected to the drain sides of the first and second transistors MN11, MN12, and a current value I11 of the current source IS11 is set to a value approximately proportional to an inverse of an absolute value of a total load impedance composed of the load resistors R11, R12 and the capacitors C11, C12. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a driving circuit for a high-frequency signal, and more particularly to a driving circuit and a communication device for driving a mixer for a local oscillation signal in a transceiver for wireless communication, for example.
[0002]
[Prior art]
Conventionally, in a driving circuit for a high-frequency signal, a current I (∝1 / R) proportional to the reciprocal of a resistance value R of a load resistor is applied in order to keep an output voltage amplitude constant regardless of manufacturing variations and temperature. Was taking.
[0003]
FIG. 7 is a circuit diagram showing a configuration example of this type of drive circuit.
In the drive circuit of FIG. 7, MOS transistors (hereinafter simply referred to as transistors) MN1 and MN2 switched by differential voltages VIP and VIN supplied to input terminals TVIP and TVIN, a current source IS1 and a resistance value are R, respectively. It has load resistances R1 and R2.
In the drive circuit, the transistors MN1 and MN2 are switched by the input differential voltages VIP and VIN, and one of the transistors is turned on, and almost all of the current I1 by the current source IS1 flows to the turned on transistor. This current flows through the load resistors R1 and R2, and the output voltages VOP and VON are output to the output terminals TVOP and TVON due to the voltage drop generated by the load resistors.
Here, the potential of both terminals is expressed by V _DD Then, the on side is (V _DD −R * I1), the off side is V _DD It becomes.
That is, the output voltage amplitude is determined by (R * I1).
[0004]
With this configuration, it is possible to make the output voltage amplitude independent of the manufacturing variation of the load resistors R1 and R2 and the resistance value fluctuation due to temperature.
In general, in a resistor on a semiconductor, the relative value variation is small, so that R1 = R2 = R always holds, and the manufacturing variation here indicates the absolute value variation.
[0005]
[Problems to be solved by the invention]
However, in a circuit for driving a high-frequency signal whose absolute value of the reactance Xc (= -1 / ωC) of the capacitance attached to the output node is not negligible compared to the resistance value R of the load resistance, the load impedance ZRC composed of the resistance and the capacitance is used. = Absolute value of R の jXc | ZRC | = R / ｛(1+ (R / Xc) ^Two )｝ ^1/2 The effect of the change in the resistance value is smaller than that of the resistance alone.
For this reason, when the current is assumed to be proportional to the reciprocal 1 / R of the resistance value, there is a disadvantage that the output amplitude fluctuates due to Xc and cannot be kept constant.
[0006]
Also, in order to ensure a certain minimum output amplitude, it is necessary to take into account manufacturing variations in resistance values, temperature fluctuations, etc. There was a disadvantage of becoming.
[0007]
Further, as a conventional example, there is a method using AGC (Auto Gain Control) for adjusting the current by monitoring the output amplitude. However, there is a disadvantage that current consumption is generally increased.
[0008]
The present invention has been made in view of the above circumstances, and an object of the present invention is to use a drive circuit capable of suppressing fluctuations in output amplitude and keeping the output amplitude constant and reducing current consumption, and using the same. A communication device is provided.
[0009]
[Means for Solving the Problems]
To achieve the above object, a driving circuit according to a first aspect of the present invention includes a switching element that adjusts an amount of current flowing between a first terminal and a second terminal according to a signal level supplied to a control terminal. A current source connected to a first terminal of the switching element, a load resistor connected between a second terminal of the switching element and a power supply voltage source, and a capacitance added to a second terminal of the switching element. And a current value of the current source is set to a value substantially proportional to the reciprocal of the absolute value of the total load impedance of the load resistance and the capacitance element.
[0010]
A drive circuit according to a second aspect of the present invention includes a first switching element that adjusts an amount of current flowing between a first terminal and a second terminal according to a signal level supplied to the control terminal; A second switching element for adjusting an amount of current flowing between the first terminal and the second terminal in accordance with a supplied signal level; and a current source connected to the first terminal of the first and second switching elements. A first load resistor connected between a second terminal of the first switching element and a power supply voltage source; and a first load resistor connected between a second terminal of the second switching element and a power supply voltage source. A second load resistor, and a capacitive element added to at least one of the second terminals of the first and second switching elements. The control terminal of the first switching element and the second terminal Control terminal of switching element 2 Is supplied with a differential signal, the current value of the current source is set to a value that schematically proportional to the reciprocal of the absolute value of the total load impedance due to the first and second load resistors and the capacitive element.
[0011]
A third aspect of the present invention is a communication device that includes a local oscillator and a mixer, and drives the mixer with a drive signal from the local oscillator, wherein the local oscillator includes a drive circuit that generates the drive signal, The driving circuit includes: a switching element that adjusts an amount of current flowing between a first terminal and a second terminal according to a signal level supplied to a control terminal; and a current source connected to the first terminal of the switching element. A load resistor connected between the second terminal of the switching element and a power supply voltage source, and a capacitive element added to the second terminal of the switching element, wherein the current value of the current source is: It is set to a value that is approximately proportional to the reciprocal of the absolute value of the total load impedance due to the load resistance and the capacitive element.
[0012]
A fourth aspect of the present invention is a communication device that includes a local oscillator and a mixer, and drives the mixer with a drive signal from the local oscillator, wherein the local oscillator includes a drive circuit that generates the drive signal, The drive circuit includes: a first switching element that adjusts an amount of current flowing between a first terminal and a second terminal according to a signal level supplied to a control terminal; A second switching element for adjusting an amount of current flowing between the first terminal and the second terminal, a current source connected to a first terminal of the first and second switching elements, and a first switching element. A first load resistance connected between the second terminal of the second switching element and the power supply voltage source; a second load resistance connected between the second terminal of the second switching element and the power supply voltage source; The above first and second And a capacitive element added to at least one of the second terminals of the switching element. A differential signal is applied to the control terminal of the first switching element and the control terminal of the second switching element. The supplied current value of the current source is set to a value substantially proportional to the reciprocal of the absolute value of the total load impedance of the first and second load resistors and the capacitive element.
[0013]
Preferably, when the resistance value of the load resistor is R and the reactance of the capacitive element is Xc, the current source sets the current to a first current substantially proportional to 1 / R and a first current proportional to 1 / Xc. And an appropriate second ratio.
[0014]
Also, preferably, when the resistance value of the load resistor is R, the current source appropriately converts the first current that is approximately proportional to 1 / R and the second current that is approximately fixed to an appropriate value. Generated by adding together with a ratio.
[0015]
The ratio between the first current and the second current is set to approximately 1 / R: 1 / Xc.
[0016]
Preferably, the current source includes at least a reference voltage source and a resistor, and generates the first current as a current obtained by dividing a reference voltage by a resistance value of the resistor.
Further, the current source includes a switched capacitor unit that switches a reference voltage with a signal having a predetermined frequency, and generates the second current by buffering a current proportional to a capacitance in the switched capacitor unit.
[0017]
Preferably, the current source includes at least a reference voltage source and a resistor having a small resistance value variation, and generates the second current as a current obtained by dividing a reference voltage by a resistance value of the resistor.
[0018]
According to the present invention, for example, the first and second switching elements are switched by a differential voltage, one of the switching elements is turned on, and almost all of the current from the current source flows to the turned on switching element. This current I flows through the first and second load resistors, and an output drive voltage is obtained by a voltage drop generated at the load resistors.
Here, assuming that the first and second switching elements are completely switched at the angular frequency ω by the input differential voltage, the fundamental component of the switching current is (I * 4 / π).
Since the load impedance ZRC of the drive circuit is R‖jXc, the output voltage is (VOP−VON∝I * | ZRC |).
At this time, the current I is a reciprocal | R‖jXc | of the absolute value (| ZRC | = | R‖jXc |) of the total load impedance ZRC. ^-1 , The output voltage amplitude is substantially constant.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
[0020]
FIG. 1 is a circuit diagram showing one embodiment of a drive circuit according to the present invention.
[0021]
As shown in FIG. 1, the drive circuit 10 includes a first MOS transistor (hereinafter simply referred to as a transistor) MN11 as first switching means, a second transistor MN12 as second switching means, and a current source IS11, first load resistor R11, second load resistor R12, first capacitive element C11, second capacitive element C12, first input terminal TVIP, second input terminal TVIN, first output terminal TVOP , And a second output terminal TVON.
In the present embodiment, the resistance values of the first load resistor R11 and the second load resistor R12 are each set to R, and the capacitance values of the first and second capacitors C11 and C12 are set to C. ing.
[0022]
The gate (control terminal) of the first transistor MN11 is connected to the first input terminal TVIP, the source (first terminal) is connected to the current supply end of the current source IS11, and the other end of the current source IS11 is connected to the ground GND. It is connected. The drain (second terminal) of the first transistor MN11 is connected to one end of the first load resistor R11, the first electrode of the first capacitive element C11, and the second output terminal TVON.
The other end of the first resistance element R11 and the second electrode of the first capacitance element C11 are connected to the power supply voltage V. _DD Connected to the supply line.
[0023]
The gate (control terminal) of the second transistor MN12 is connected to the second input terminal TVIN, and the source (first terminal) is connected to the current supply terminal of the current source IS11. The drain (second terminal) of the second transistor MN12 is connected to one end of the second load resistor R12, the first electrode of the second capacitive element C12, and the first output terminal TVIP.
The other end of the second resistance element R12 and the second electrode of the second capacitance element C12 are connected to the power supply voltage V. _DD Connected to the supply line.
[0024]
The first and second capacitance elements C11 and C12 are each composed of, for example, a capacitance element, a wiring capacitance for connecting the elements, or a parasitic capacitance inherent in a transistor or a resistor. Is added to the drain of the transistor MN12. In FIG. 1, the output terminal and the power supply voltage V are shown for easy understanding. _DD Are shown as capacitive elements connected between the supply lines.
[0025]
In the above configuration, the differential signals VIP and VIN are supplied to the gate of the first transistor MN11 and the gate of the second transistor MN12.
The first load resistor R11 and the first capacitive element C11 are connected in parallel to the second output terminal TVON, and the second load resistor R12 and the second load resistor R12 are connected to the first output terminal TVOP. Are connected in parallel.
[0026]
Further, in the drive circuit 10 according to the present embodiment, the current value I11 of the current source IS11 is determined by the total load of the first and second load resistors R11 and R12 and the first and second capacitance elements C11 and C12. The impedance ZRC is the absolute value of R‖jXc | the reciprocal of R‖jXc | ^-1 Is set to a current value that is approximately proportional to.
Here, Xc (= -1 / ωC) indicates the reactance of the capacitance.
[0027]
Next, the operation will be described.
[0028]
The first and second transistors MN11 and MN12 are switched by the input differential voltages VIP and VIN, and one of the transistors is turned on, and almost all of the current I11 from the current source IS11 flows to the turned on transistor. This current flows through the first and second load resistors R11 and R12, and output voltages VOP and VON are output to the first and second output terminals TVOP and TVON due to a voltage drop generated by the load resistors.
[0029]
Here, assuming that the first and second transistors MN11 and MN12 are switching at the angular frequency ω by the input differential voltages VIP and VIN, the fundamental wave component of the switching current (IMN11−IMN12) is (I11 * 4 / π).
Since the impedance ZRC of the load of the drive circuit 10 is R‖jXc, the output voltage is (VOP−VON∝I11 * | ZRC |).
At this time, the current I11 is a reciprocal | R 絶 対 jXc | of the absolute value (| ZRC | = | R‖jXc |) of the total load impedance ZRC. ^-1 , The output voltage amplitude is substantially constant.
[0030]
Hereinafter, a method for generating the current I11 will be described.
[0031]
Here, assuming that G = 1 / R and Bc = 1 / Xc, for example, if there is a first current IR proportional to G and a second current IC1 proportional to the absolute value of BC, IR and IC1 are appropriately set. The sum of the absolute values of the total load impedance ZRC (| ZRC | = | RｃjXc |) | R‖jXc | ^-1 Can be generated.
[0032]
| R‖jXc | ^-1 = (G ^Two + BC ^Two ) ^1/2 Therefore, I∝ (G ^Two + BC ^Two ) ^1/2 Should be fine.
Assuming that I = a * IR + b * IC1, it is understood that a / b = G / BC in the first-order approximation.
That is, a current obtained by adding IR (first current) and IC1 (second current) at a ratio of (1 / R: 1 / Xc) may be used.
The addition of the currents IR and IC1 can be realized, for example, by changing the mirror ratio of the current mirror and adding the currents.
[0033]
FIG. 2 is a circuit diagram illustrating a configuration example of the current source according to the present embodiment.
[0034]
This current source IS11 has MOS transistors MN21 to MN26 and current sources IS21 and IS22.
[0035]
The drain of the transistor MN21 is connected to the current source IS21 of the first current IR, its own gate and the gate of the transistor MN21, and the sources of the transistors MN21 and MN22 are connected to the power supply voltage V _DD Connected to the supply line. Further, the drain of the transistor MN22 is connected to the drain of the transistor MN25.
The drain of the transistor MN23 is connected to the current source IS22 of the second current IC, its own gate and the gate of the transistor MN24, and the sources of the transistors MN23 and MN24 are connected to the power supply voltage V _DD Connected to the supply line. Then, the drain of the transistor MN24 is connected to the drain of the transistor MN25.
The source of the transistor MN25 is grounded, and the connection point between its own drain and the drains of the transistors MN22 and MN24 is connected to its own gate and the gate of the transistor MN26. The source of the transistor MN26 is grounded, and the drain constitutes a current supply end of the current source IS11, which is connected to the sources of the first and second transistors MN11 and MN12 in FIG.
[0036]
In the current source IS11 having such a configuration, the first current mirror circuit MIR21 is formed by the transistors MN21 and MN22, the second current mirror circuit MIR22 is formed by the transistors MN23 and MN24, and the first current mirror circuit MIR22 is formed by the transistors MN25 and MN26. Three current mirror circuits MIR23 are configured.
In the first current mirror circuit MIR21, the transistor size of the transistors MN21 and MN22 is set to 1: a. In the second current mirror circuit MIR22, the transistor size of the transistors MN23 and MN24 is set to 1: b.
Therefore, in the first current mirror circuit MIR21, the first current IR of the current source IS21 is multiplied by a, and a current (a * IR) is generated. Similarly, in the second current mirror circuit MIR22, the second current IC of the current source IS22 is multiplied by b to generate a current (b * IC).
Then, the current (a * IR) from the first current mirror circuit MIR21 and the current (b * IC) from the second current mirror circuit MIR22 are added, and the current I11 passes through the drain of the transistor MN26 of the third current mirror circuit MIR23. = A * IR + b * IC.
[0037]
FIG. 3 is a circuit diagram showing a configuration example of the current source IS21 of the first current IR of FIG.
[0038]
As shown in FIG. 3, the current source IS21 includes a reference voltage source V31, an operational amplifier OP31, MOS transistors MN31 to MN34, and a resistor R31.
[0039]
The positive electrode of a reference voltage source V31 that supplies the reference voltage VREF is connected to the inverting input (-) of the operational amplifier OP31, and the negative electrode is grounded.
The output of the operational amplifier OP31 is connected to the gates of the transistors MN31 and MN32, and the sources of the transistors MN31 and MN32 are connected to the power supply voltage V _DD Connected to the supply line.
The drain of the transistor MN31 is connected to the non-inverting input (+) of the operational amplifier OP31 and one end of the resistor R31, and the other end of the resistor R31 is grounded.
The drain of the transistor MN32 is connected to the drain and gate of the transistor MN33 and the gate of the transistor MN34.
The drains of the transistors MN33 and MN34 are grounded, the drain of the transistor MN34 forms a supply end for the current IR, and is connected to the drain of the transistor MN21 in FIG.
A current mirror circuit MIR31 is configured by the transistors MN33 and MN34.
[0040]
In the current source IS21, a current obtained by dividing the reference voltage VREF by the reference voltage source V31 by the resistance R0 (∝R) of the resistor R31 flows to the transistor MN32, and this current is turned back by the current mirror MIR31 to be proportional to 1 / R0. To generate a first current IR.
By using this current, a current in which the resistance value of the load resistor is inversely proportional to the fluctuation can be supplied, and the output voltage amplitude of the drive circuit 10 can be kept constant.
[0041]
FIG. 4 is a circuit diagram showing a configuration example of the current source IS22 of the second current IC1 in FIG.
[0042]
As shown in FIG. 4, the current source IS22 includes a reference voltage source V41, switch transistors SW41 and SW42, capacitors C41 and C42, an inverter INV41, operational amplifiers OP41 and OP42, MOS transistors MN43 to MN46, a resistor R41 having a resistance value R1, And a resistor R42 having a resistance value R0.
[0043]
The positive electrode of a reference voltage source V41 for supplying the reference voltage VREF is grounded, the negative electrode is connected to one source / drain terminal of the switch transistor SW41, and the other source / drain terminal of the switch transistor SW41 is connected to the first electrode of the capacitor C41. The switching transistor SW42 is connected to one source / drain terminal. The other source / drain terminal of the switch transistor SW42 is connected to the inverting input (−) of the operational amplifier OP41, one end of the resistor R41, and the first electrode of the capacitor C42. The second electrode of the capacitor C41 is grounded, and the second electrode of the capacitor C42 and the other end of the resistor R41 are connected to the output of the operational amplifier OP41. The non-inverting input (+) of the operational amplifier OP41 is grounded.
The gate of the switch transistor SW41 and the input of the inverter INV41 are connected to the input terminal Tf of the signal Sf of the frequency f, and the output of the inverter INV41 is connected to the gate of the switch transistor SW42.
[0044]
The inverting input (-) of the operational amplifier OP42 is connected to the output of the operational amplifier OP41.
The output of the operational amplifier OP42 is connected to the gates of the transistors MN43 and MN44, and the sources of the transistors MN43 and MN44 are connected to the power supply voltage VN. _DD Connected to the supply line.
The drain of the transistor MN43 is connected to the non-inverting input (+) of the operational amplifier OP42 and one end of the resistor R42, and the other end of the resistor R42 is grounded.
The drain of the transistor MN44 is connected to the drain and gate of the transistor MN45 and the gate of the transistor MN46.
The drains of the transistors MN45 and MN46 are grounded, the drain of the transistor MN46 forms a supply end of the current IR, and is connected to the drain of the transistor MN23 in FIG.
[0045]
The first stage including the switch transistors SW41 and SW42, the inverter INV41, and the capacitor C41 forms a switched capacitor unit SWCP41, and the second stage of the operational amplifier OP41, the resistor R41, and the capacitor C42 forms a low-pass filter unit LPF41, and the transistor MN45. And MN46 constitute a current mirror circuit MIR41.
[0046]
The current source IS22 having such a configuration can generate the second current IC1 by buffering a current proportional to the capacitance in the switched capacitor unit.
[0047]
In general, the capacitance C is a gate capacitance of a transistor serving as a load of the next stage or a parasitic capacitance of a wiring, and thus the capacitance C can be applied to a switched capacitor unit. The signal Sf is input from the input terminal Tf to turn on / off the switch transistors SW41 and SW42. Thus, by switching the reference voltage VREF at the frequency f, the average current of the switched capacitor unit SWCP41 becomes fCVREF.
This is buffered while being averaged by a low-pass filter unit LPF41 in the next stage, and a current I = fCVREF R1 / R0 is generated based on this.
Here, by setting R1 = R0, an average current of the switched capacitor unit can be obtained.
Here, the frequency f is a reference frequency of, for example, a crystal oscillator or the like, and a current I∝C∝1 / Xc is obtained by keeping the voltage VREF constant.
The current at this time is turned back by the current mirror circuit MIR41 to obtain the second current IC1.
[0048]
Also, in comparison with the absolute value of R, the absolute value of C generally has less variation in manufacturing variation. Therefore, even if it is considered that C is fixed and the second current IC2 is constant, the output voltage amplitude is kept almost constant.
This corresponds to a configuration in which IC2 = constant instead of IC1∝1 / Xc described with reference to FIG.
[0049]
FIG. 5 is a circuit diagram showing a configuration example of the current source IS22 of FIG. 2 where the second current IC2 is constant.
[0050]
As shown in FIG. 5, the current source IS22a includes a reference voltage source V51, an operational amplifier OP51, MOS transistors MN51 to MN54, and a resistor R51.
In this case, as the resistor R51, a resistor having a small variation in the resistance value RX, for example, an external chip resistor is used.
[0051]
The positive electrode of the reference voltage source V51 for supplying the reference voltage VREF is connected to the inverting input (-) of the operational amplifier OP51, and the negative electrode is grounded.
The output of the operational amplifier OP51 is connected to the gates of the transistors MN51 and MN52, and the sources of the transistors MN51 and MN52 are connected to the power supply voltage V _DD Connected to the supply line.
The drain of the transistor MN51 is connected to the non-inverting input (+) of the operational amplifier OP51 and one end of the resistor R51, and the other end of the resistor R51 is grounded.
The drain of the transistor MN52 is connected to the drain and gate of the transistor MN53 and the gate of the transistor MN54.
The drains of the transistors MN53 and MN54 are grounded, the drain of the transistor MN34 forms a supply end of the current IC2, and is connected to the drain of the transistor MN23 in FIG.
A current mirror circuit MIR51 is configured by the transistors MN53 and MN54.
[0052]
In the current source IS22a, a current obtained by dividing the reference voltage VREF by the reference voltage source V51 by the resistance value RX of the resistor R51 flows to the transistor MN52, and this current is turned back by the current mirror MIR51, so that IC2∝1 / Xc = constant. Generates current.
By using this current, a constant current can be supplied irrespective of the variation in the resistance value of the load resistance due to manufacturing variations and temperature, and the output voltage amplitude of the drive circuit 10 can be kept constant.
[0053]
As described above, according to this embodiment, the first and second transistors MN11 and MN12 whose gates are supplied with the differential voltage and the sources of the first and second transistors MN11 and MN12 are connected. It has a current source IS11, load resistors R11 and R12 connected to the drain sides of the first and second transistors MN11 and MN12, and capacitive elements C11 and C12. The current value I11 of the current source IS11 is , R12 and the capacitances C11, C12 are set to values that are approximately proportional to the reciprocal of the absolute value of the total load impedance, so that an output with a constant amplitude can be obtained irrespective of resistance value variations. In addition, when the minimum output amplitude is determined, it is not necessary to consider the variation, so that the power can be reduced.
[0054]
FIG. 6 is a circuit diagram illustrating a configuration example of a reception front-end unit as a communication device of a wireless system to which the drive circuit according to the present invention is applied.
[0055]
As shown in FIG. 6, the reception system front end unit 100 includes an antenna 101, a SAW filter 102, a matching circuit (MTC) 103, a low noise amplifier (LNA) 104, a first VCO 105 as a first local oscillator, A first PLL 106, a first loop filter 107, a second VCO 108 as a second local oscillator, a second PLL 109, a second loop filter 110, mixers 111 to 114, band-pass filters (BPF) 115 to 117 , A synthesizer 118, and a comparator 119.
[0056]
The reception system front end unit 100 includes a low noise amplifier (LNA) 104, a first VCO 105, a first PLL 106, a second VCO 108, a second PLL 109, mixers 111 to 114, and bandpass filters (BPF) 115 to 117. , A synthesizer 118 and a comparator 119 are integrated on one chip.
Then, it has a configuration in which the RF section on the high frequency side in all stages and the intermediate frequency (IF) section in the subsequent stage are cascaded.
The RF unit includes a low noise amplifier 104, a first VCO 105, a first PLL 106, a first loop filter 107, mixers 111 and 112, and bandpass filters 115 and 116.
The IF unit includes a second VCO 108, a second PLL 109, a second loop filter 110, mixers 113 and 114, a combiner 118, a bandpass filter 11117, and a comparator 119.
[0057]
The first VCO 105 outputs the first oscillation signal having a frequency of 1573 MHz to the mixers 111 and 112 according to the output signal of the first loop filter 107 in accordance with the output signal of the first PLL 106 synchronized in phase with the reference clock CLK by the crystal oscillator. Supply.
The drive circuit 10 according to the above-described embodiment for obtaining a constant amplitude output is applied to the first VCO 105 related to the high frequency.
In practice, differential outputs VOP and VON are supplied to mixers 111 and 112, respectively. That is, two drive circuits 10 are mounted on the first VCO 105.
[0058]
The second VCO 108 outputs the output of the second PLL 109 phase-locked to the reference clock CLK from the crystal oscillator to the mixers 113 and 114 in accordance with the output signal of the second loop filter 110 and the second oscillation signal of 3 MHz in frequency. Supply.
Since the second VCO 108 is used in a lower frequency band than the first VCO 105, the drive circuit 10 according to the present embodiment does not need to be applied.
However, it is possible to apply the above-described drive circuit 10 according to the present embodiment for obtaining a constant amplitude output to the second VCO 108.
Also in this case, differential outputs VOP and VON are supplied to mixers 113 and 114, respectively. That is, two drive circuits 10 are mounted on the second VCO 108.
[0059]
In the receiving system front-end unit 100, for example, a radio signal RF having a frequency of 1575 MHz is received by the antenna 101 and input to the mixers 111 and 112 via the SAW filter 102, the matching circuit 103, and the low-noise amplifier 104.
Then, in the mixers 111 and 112, the first VCO 105 mixes the first oscillation signal with the first oscillation signal. The first intermediate frequency of 2 MHz is extracted through the band-pass filters 115 and 116 and input to the mixers 113 and 114.
After being mixed with the second oscillating signal by the second VCO 108 in the mixers 113 and 114, they are combined in the combiner 118, and a second intermediate frequency of 1 MHz is obtained through the band-pass filter 117.
Then, the data of the comparator 119 is output to a baseband processing unit (not shown) based on the output of the bandpass filter 117.
[0060]
As described above, the reception system front-end unit 100 employs the driving circuit that obtains a constant-amplitude output regardless of the resistance value variation or the like in the first VCO 105. is there.
[0061]
【The invention's effect】
As described above, according to the present invention, an output having a constant amplitude can be obtained irrespective of resistance value variation.
In addition, when the minimum output amplitude is determined, there is no need to consider variations, so that there is an advantage that power consumption can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing one embodiment of a drive circuit according to the present invention.
FIG. 2 is a circuit diagram illustrating a configuration example of a current source according to the embodiment.
FIG. 3 is a circuit diagram showing a configuration example of a current source of IR in FIG. 2;
FIG. 4 is a circuit diagram showing a configuration example of a current source of IC1 in FIG. 2;
FIG. 5 is a circuit diagram showing another configuration example of the current source of IC1 in FIG. 2;
FIG. 6 is a circuit diagram showing a configuration example of a reception system front end unit of a wireless system to which a drive circuit according to the present invention is applied.
FIG. 7 is a circuit diagram illustrating a configuration example of a conventional drive circuit.
[Explanation of symbols]
Reference numeral 10: drive circuit, MN11: first MOS transistor (first switching means), MN12: second MOS transistor (second switching means), I11: current source, R11: first load resistance, R12 ... Second load resistance, C11: first capacitance element, C12: second capacitance element, MN21 to MN26: MOS transistor, IS21, IS22: current source, 100: reception front end unit, 101: antenna, 102 ... SAW filter, 103 matching circuit (MTC), 104 low-noise amplifier (LNA), 105 first VCO, 106 first PLL, 107 first loop filter, 108 second VCO, 109 ... second PLL, 110 ... second loop filter, 111-114 ... mixer, 115-117 ... band-pass filter (BP ), 118 ... combiner, 119 ... comparator.

Claims (20)

A switching element for adjusting an amount of current flowing between the first terminal and the second terminal according to a signal level supplied to the control terminal;
A current source connected to a first terminal of the switching element;
A load resistor connected between the second terminal of the switching element and a power supply voltage source;
A capacitive element added to a second terminal of the switching element;
Has,
A drive circuit in which a current value of the current source is set to a value substantially proportional to a reciprocal of an absolute value of a total load impedance by the load resistance and the capacitive element. When the resistance value of the load resistor is R and the reactance of the capacitive element is Xc, the current source generates a first current approximately proportional to 1 / R and a second current proportional to 1 / Xc. The driving circuit according to claim 1, wherein: When the resistance value of the load resistor is R, the current source generates the current by adding a first current approximately proportional to 1 / R and a second current that is approximately fixed at an appropriate ratio. The drive circuit according to claim 1, wherein 3. The drive circuit according to claim 2, wherein a ratio between the first current and the second current is set to approximately 1 / R: 1 / Xc. The drive circuit according to claim 4, wherein the current source includes at least a reference voltage source and a resistor, and generates the first current as a current obtained by dividing a reference voltage by a resistance value of the resistor. 5. The current source includes a switched capacitor unit that switches a reference voltage with a signal of a predetermined frequency, and generates the second current by buffering a current proportional to a capacitance in the switched capacitor unit. The driving circuit as described. The current source includes at least a reference voltage source and a resistor, and a switched capacitor unit that switches the reference voltage with a signal having a predetermined frequency.
Generating the first current as a current obtained by dividing a reference voltage by a resistance value of the resistor;
5. The drive circuit according to claim 4, wherein the second current is generated by buffering a current proportional to a capacitance in the switched capacitor unit. 4. The drive circuit according to claim 3, wherein the current source includes at least a reference voltage source and a resistor having a small resistance value variation, and generates the second current as a current obtained by dividing a reference voltage by a resistance value of the resistor. 9. The drive circuit according to claim 8, wherein the current source generates the first current as a current obtained by dividing a reference voltage by a resistance value of a predetermined resistor. A first switching element for adjusting an amount of current flowing between the first terminal and the second terminal according to a signal level supplied to the control terminal;
A second switching element for adjusting an amount of current flowing between the first terminal and the second terminal according to a signal level supplied to the control terminal;
A current source connected to first terminals of the first and second switching elements;
A first load resistance connected between a second terminal of the first switching element and a power supply voltage source;
A second load resistor connected between a second terminal of the second switching element and a power supply voltage source;
A capacitance element added to at least one of the second terminals of the first and second switching elements,
A differential signal is supplied to a control terminal of the first switching element and a control terminal of the second switching element,
A drive circuit wherein a current value of the current source is set to a value substantially proportional to an inverse of an absolute value of a total load impedance by the first and second load resistors and the capacitive element. When the resistance value of the load resistor is R and the reactance of the capacitive element is Xc, the current source generates a first current approximately proportional to 1 / R and a second current proportional to 1 / Xc. 11. The driving circuit according to claim 10, wherein: When the resistance value of the load resistor is R, the current source generates the current by adding a first current approximately proportional to 1 / R and a second current that is approximately fixed at an appropriate ratio. The drive circuit according to claim 10, wherein: The drive circuit according to claim 11, wherein a ratio between the first current and the second current is set to approximately 1 / R: 1 / Xc. 14. The drive circuit according to claim 13, wherein the current source includes at least a reference voltage source and a resistor, and generates the first current as a current obtained by dividing a reference voltage by a resistance value of the resistor. 14. The current source includes a switched capacitor unit that switches a reference voltage with a signal of a predetermined frequency, and generates the second current by buffering a current proportional to a capacitance in the switched capacitor unit. The driving circuit as described. The current source includes at least a reference voltage source and a resistor, and a switched capacitor unit that switches the reference voltage with a signal having a predetermined frequency.
Generating the first current as a current obtained by dividing a reference voltage by a resistance value of the resistor;
14. The drive circuit according to claim 13, wherein the second current is generated by buffering a current proportional to a capacity in the switched capacitor unit. 13. The drive circuit according to claim 12, wherein the current source includes at least a reference voltage source and a resistor having small resistance value variation, and generates the second current as a current obtained by dividing a reference voltage by a resistance value of the resistor. 18. The drive circuit according to claim 17, wherein the current source generates the first current as a current obtained by dividing a reference voltage by a resistance value of a predetermined resistor. A communication device having a local oscillator and a mixer, wherein the mixer is driven by a drive signal from the local oscillator,
The local oscillator includes a drive circuit that generates the drive signal,
The drive circuit is
A switching element for adjusting an amount of current flowing between the first terminal and the second terminal according to a signal level supplied to the control terminal;
A current source connected to a first terminal of the switching element;
A load resistor connected between the second terminal of the switching element and a power supply voltage source;
A capacitive element added to a second terminal of the switching element;
Has,
A communication device, wherein the current value of the current source is set to a value that is approximately proportional to the reciprocal of the absolute value of the total load impedance of the load resistance and the capacitive element. A communication device having a local oscillator and a mixer, wherein the mixer is driven by a drive signal from the local oscillator,
The local oscillator includes a drive circuit that generates the drive signal,
The drive circuit is
A first switching element for adjusting an amount of current flowing between the first terminal and the second terminal according to a signal level supplied to the control terminal;
A second switching element for adjusting an amount of current flowing between the first terminal and the second terminal according to a signal level supplied to the control terminal;
A current source connected to first terminals of the first and second switching elements;
A first load resistance connected between a second terminal of the first switching element and a power supply voltage source;
A second load resistor connected between a second terminal of the second switching element and a power supply voltage source;
A capacitance element added to at least one of the second terminals of the first and second switching elements,
A differential signal is supplied to a control terminal of the first switching element and a control terminal of the second switching element,
A communication device in which a current value of the current source is set to a value substantially proportional to a reciprocal of an absolute value of a total load impedance by the first and second load resistors and the capacitive element.

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