SU1679638A1 - Synchronizer - Google Patents

Description

The invention relates to radio engineering.

The purpose of the invention is to improve the noise immunity. The synchronization device contains a generator of 1 reference pulses, a phase shifter 2, a divider 3 frequencies, an OR 4 element, a receiver'5, a search and tracking unit 6 and an input signal analyzer 7 consisting of an input signal capture detection unit 8, a subtracting counter 9, accumulating adder 10 and a frequency divider 11. At the initial moment after switching on the generator 1, it gives out the frequency ί _Γ and has a large detuning frequency; tty ATg = Tr ^ go. relative to the nominal T _ha . To ensure reliable acquisition of phase shifter 2 through the element OR 4, an additional periodic pulse sequence with a frequency P is applied, which is generated in the analyzer 7. If the value of E is such that / MGO = P / <10 Hz, then the condition of reliable synchronization is satisfied. 1 il.

SL

with

1679638 A1

3

1679638

four

The invention relates to radio engineering. in particular, to radionavigation, and can be used for automatic synchronization of the receiver-indicator of the radionavigation system.

The aim of the invention is to improve the noise immunity.

The drawing shows a block diagram of a synchronization device.

The synchronization device contains a generator of 1 reference pulses, a phase shifter 2, a divider 3 frequencies, an element of OR 4, a receiver 5, a search and tracking unit 6, an input signal analyzer 7, which includes an input signal capture detection unit 8, a subtracting counter 9, accumulating adder 10 and an additional frequency divider 11.

The synchronization device works as follows.

The generator 1 of the reference pulses generates a sequence of reference pulses, which through the phase shifter 2 is fed to the input of the frequency divider 3, in which pulses are formed from the specified sequence, the sequence of which is a multiple of the period of the received radio pulses, and rectangular pulses equal in duration to the received radio pulses.

Received and amplified by the receiver 5 - radio pulses arrive at block 6 of search and tracking, in which a sequence of rectangular pulses is formed from the radio pulses, then a rectangular pulse is formed, the duration of which is determined by the time delay between the pulses of the generated sequence and the pulses generated at the second output of the divider 3

frequencies.

Then the formed rectangular pulse is gated with a sequence of pulses coming from the first output of divider 3, the repetition period of which is two times less than the duration of the rectangular pulses formed at its second output.

The pulse sequence from the output of block 6 search and tracking enters the phase shifter 2 at the time when a square pulse is formed, and the number of pulses entering the phase shifter 2 is determined by the time delay between the pulses generated by the search and tracking unit 6 and the pulses generated on the second output of the divider 3.

At the initial moment after switching on the generator 1, the reference pulses produce a frequency _Γ and have a large frequency detuning Δί _Γ = relative to the nominal _Γ ο.

To ensure reliable entry into synchronism, it is necessary to apply an additional periodic pulse sequence with frequency G to the phase shifter 2 through the element OR 4. In this case, the average value of the pulse frequency at the output of the phase shifter 2 is (Tg ~ T) · If the value of T is such that / Tg - Ίγο - П! <10 Hz, then the condition of reliable synchronization is fulfilled.

The control pulse sequence with frequency G to the input of the element OR 4 is fed from the output of accumulating adder 10, which is a synchronous η-bit drive, to one input of which from an additional 11 frequency divider clock pulses are received with a frequency Ει, and from the output of deducting counter 9 The η-bit number M. In this case, the overflow pulses from the output of accumulating adder 10 have

_{with with} M M

the average frequency is E = Ρι- - - = Ει -, i.e.

These blocks perform the functions of a frequency divider with a fractionally rational coefficient. The frequency tuning disc is equal to Ει / а, and the maximum value of the output frequency is Ρι.

Selection of the required frequency for a given time moment G is provided by the block 8 of the detection of the capture of the input signal, which is a drive-detector signal.

Immediately after switching on, the subtractive counter 9 is set to the state corresponding to the highest value M, i.e. the frequency at the output of the accumulating adder 10 of the analyzer 7 is set to P = Gmax. Then, during the accumulation time, a search and detection procedure involving the search and tracking unit 6 and the capture detection unit 8 occur. If a seizure occurs, then the output frequency G remains at the output of accumulating adder 10. If no seizure occurs, a pulse appears at the output of the capture detection unit 8, which reduces the frequencies E by 2 ΔΕπορ., And the procedure is repeated. This process occurs until the value of 6- - HGO - P is within ± Δ Epor ·

After that, from the output of block 8 of detection of capture, the flow of pulses is stopped and the last value is fixed

frequency E at the output of the accumulating sum 1679638

10. A slow change in frequency with time at some point violates the conditions of reliable capture, then a single impulse will appear at the output of the capture detection unit 8, the frequency of the impulses at its output 5 will decrease by 2 Δ P _P or. and the system is again in equilibrium.

Claims (1)

A synchronization device containing serially connected reference pulse generator, phase shifter and frequency divider, whose outputs are connected to the corresponding inputs of the search and tracking unit, to the signal input of which the receiver output is connected and the first input of the input analyzer, to the second input of which is connected output of the reference pulse generator 20, characterized in that, with In order to improve noise immunity, the input signal analyzer is designed as a serially connected input capture detection unit, a subtractive counter and an accumulating adder, the output of an additional frequency divider is connected to another input, the first input of the block and the second input detecting the input 10 signal and the additional divider input the frequencies are respectively the first, additional and second inputs of the input analyzer, the output of which is the output accumulating adder and entered the OR gate, which outputs the input signal analyzer, and search and tracking unit through an OR gate coupled to a control input of the phase shifter and to a further input of the input signal analyzer connected to the corresponding output of the frequency divider.