SU1215109A2 - Subtracting device - Google Patents

Abstract

The invention relates to the field of computing and can be used in the processing of digital information. The aim of the invention is to simplify the device and expand the field of application by implementing a controlled zeroing of the device output. The device for subtraction contains a n-bit adder, a group of n PABTi elements (DI-lf (P

Description

121

SIGNIFICANCE, a group of p elements AND, a group of n elements OR-NOT, B-trigger delay block, three elements OR, three elements AND, HEP ALBUM TORCH, three elements OR-NOT and NOT element, Delay unit contains two One-way-one RATOR. At the input of the resolution of subtraction 1 and the input of the delay unit is 1JY-; pulse tracking of operands. Upon the decay of this goshulse, a pulse appears at the first output of the delay unit.

The invention relates to computing and can be used in the processing of digital information.

The aim of the invention is to simplify the device and expand the scope of use by implementing controlled zero output of the device.

FIG. 1 is a functional block diagram of the subtractor; in fig. 2 - diagram of the delay unit; in fig. 3 - timing charts of the device.

The device for subtraction contains n-razdny adder 1, group 2 of h elements UNIFORMITY, group 3 of h elements AND, group 4 of h elements SH-NOT D-trigger 5j block 6 delay, elements OR 7-9, elements AND 10-12, the UNEQUALITY element 13, the elements OR NOT 14-16, the element NOT 17, the inputs 18 of the first operand, the inputs 19 of the second operand, the input 20 of the subtraction resolution, the input 21 zeroes the input 22 specifying the operation mode, the input 23 allowing the output of the result in reverse code, output 24 of the device, output 25 digits of the difference and output

26 operands.

Block 6 delay contains the first

27 and second 28 one-shot ones. The device works as follows.

in a way.

At time t, there is a change of information at the inputs 18 and 19 of the first and second operands. Input 20 permits the subtraction to the input of block 6 of the delay arrives

109

the duration of which is longer than the duration of the transient process at the transfer output of the adder. In the delay unit i by the decay of this pulse, at its second output a pulse is formed, the duration of which is also chosen longer than the duration of the transient process at the output of the ipeHOca adder. Invention - additional to auth. St. 1133592, 3 Il.

impulse tracking operands. By the decline of this pulse on the first you-. During the delay block 6, a pulse appears, the duration of which 5 is longer than the duration of the transient process at the output of the transfer of sum- mat 1. In block 6, the decay time jToro of the pulse at its second output creates a pulse whose duration is also chosen longer than the transient transfer output of the adder 1.

If the input 21 zeroes

5, the signal O is present, then the signal O appears at the output of the element And 10, and the output of the element HE 17 is 1. 1. Signal 1 from the output of the element He 17 permits the passage of the signal 0 through the T) trigger 5 and the element 12, and the signal About from the output of the element And 10 allows the passage of signals through the element OR 8 and the element SH- NOT 14.

5 From the first output of block 6 of the delay in the time interval from te to t, signal 1 through the serially connected elements OR 9 and I 12 enters the transfer input of sum0 torus 1.

In the time interval from t ,, to t at the first input of the element 11, there is a signal O, which blocks the signal path

- from the transfer output of the adder 1 to the transfer input. In this time interval, at the transfer input of adder 1, signal O is present.

In the time interval from t to t, the element 11 is unlocked on

the transfer input of the adder 1 through the series-connected elements AND 11, OR 9 and And 12 receives a signal from the transfer output of the same adder.

If signal 1 is present at input 22 of the operation mode setting, then signals OR will NOT appear at outputs 15 and 16. At the output of the element OR 8, the signal O appears, and at the output of the element OR NOT 14 is 1. These signals unblock, respectively, a group of 4 elements SH-NOT and a group of 3 elements I. Consequently, the first group of inputs of the adder 1 receives the direct code the first operand from input 18, and to the second group of inputs - the inverse code of the second operand from input 19. In adder 1, the code of the second operand is subtracted from the code of the first operand.

If the second operand is smaller than the first operand, then the output of the transfer of adder 1 at time t will be signal 1. This signal will be recorded at the first output of delay block 6 at T) -trigger 5. At times t and tj at the output of the transfer of adder 1, signal 1 will also be present. Thus, at the first and second inputs of the element EQUALITY 13, by the time the result of the subtraction is fixed, there will be signals O, iFactly, the output of the element UNEQUALITY 13

will be a signal O.

Thus, at the output 25 of the sign of the difference and at the output 26 of equality of the operands, the result of the comparison, respectively, with signals 1 and O is recorded. At output 24 there will be a difference of operands in the forward code.

If the second operand is larger than the first operand, then at the output of the transfer of adder 1 at time ty the signal O will be present. This signal on the pulse decay at the first output of the delay block 6 will be recorded in the D-trigger 5. In the time interval from tg to tf the output of the transfer of the adder 1 will be a signal O. Thus, at the first and second inputs of the element UNEQUALITY

13 by the time the result of the subtraction is fixed, signal2151094 will be present

 ly O. Therefore, the output of this element will be the signal O.

Thus, at the output 25 of the sign of the difference and at the output 26 of the equality c, the result of the comparison is recorded by the signal O, and at the output 24 there will be the difference of the operands in the forward code.

If the code of the second operand is equal to the code of the first operand, then at the output of the transfer of adder 1 at time tg signal 1 will be present. This signal will be recorded at the first input of delay unit 6 at J5 f-trigger 5. In the time interval from t, o at the output of the transfer of adder 1 there will be a signal O. Thus, at the first input of the UNEMATE DETAILER element 13 there is a signal O, and at the second input there is a signal 1 ... Therefore, at you. during element, UNEQUALITY .13 will be signal 1.

Thus, at the output 25 of the sign 25 of the difference and at the output 26 of the equality, the result of comparison, respectively, by signals O and 1, is fixed. At the outputs of adder 1, the difference of operands in the inverse code is obtained at the moment of recording the result of the subtraction, since Oh and the first operand is equal to the second. Since at the inputs of the element OR 7 there are signals O, then 35 and at the first inputs of the elements EQUALITY of group 2 will be the signal O. Therefore, at the output 24 there will be zero difference of the operands.

If the signal O is present at the input 22 of the job mode 0 operation, the device operates in the transfer mode to the output of either the per-fBoro operand or the second one, depending on the signal at the input 23. 45

If the signal O is applied to the input 23, then the first operand is transmitted to the output 24 of the device. In this case, the outputs of the element OR-NOT 15, the element OR 7, the element OR 8 and the element ШШ-НЕ 14 appear signals 1. At that, the group of 3 elements AND is unlocked, and the group of 4 elements OR is NOT blocked, t. e. on

55 the first group of inputs of the adder 1 receives the first operand, and the second group of inputs of the adder 1 receives the zero code. ..

Thus, at the outputs of adder 1, the direct code of the first operand is obtained. Signal 1 is sent to the first inputs of EQUIPMENT of group 2 from the output of element OR 7. Consequently, the direct code of the first operand is sent to the output 24 of the device.

If signal 1 is applied to input 23, a second operand is transmitted to the device output.

If at the input 21 of the zeroing and at the input 22 of the setting of the operation mode, signals 1 are simultaneously present, then the subtractor operates in the zero setting mode. In this case, the output of the element And 10 receives a signal 1, and the output of the element NOT 17 - O. At the same time, the outputs b. -trigger 5 and elements I 12 and ILY-NOT 14 will have signals O, and the output of element OR 8 will be 1. Thus, the first and second groups of inputs of adder 1, the transfer input of adder t receive signals equal to zero. Consequently, at the outputs of the adder 1, a zero result is obtained, and since the first inputs of the elements EQUALITY of groups 2 receive a signal 1 from the output of the element OR 7, then the output 24 of the device will have a zero result. Since the D-trigger 5 is in the zero state, and the output of the transfer of the adder 1 is the signal O, then the output 26 will be the signal O.

Claims (1)

Invention Formula A subtraction device containing an h -discharge adder, where h is the width of the operands, a group of h elements, EQUITY, a group of AND elements, a group of h OR elements, three IZH-elements, the first AND element, and two elements OR, the first inputs of the elements AND of the group are connected to the inputs of the corresponding bits of the first operand of the device, and the first inputs of the elements of the OR-NO group are connected to the inputs of the corresponding bits of the second operand of the device, the outputs of the elements of the AND group and the outputs of the elements of the OR-NO group are connected with the corresponding Leica Geosystems inputs of the first and second groups of the adder inputs, you Yu 15 20 5 o 0 five 0 the moves of the bits of which are connected to the first inputs of the corresponding elements EQUALITY of the group, the outputs of which are connected to the outputs of the bits of the device, the second inputs of the elements AND group and the elements OR NOT groups are connected respectively to the outputs of the first element SH-NI of the first element OR, the second inputs of the elements EQUALITY the groups are connected to the output of the second element OR, the first input of which is connected to the transfer output of the adder, the second input is connected to the first inputs of the first element OR and the first element OR NOT, and that the same with the output of the first element AND, and the third input of the second element OR is connected to the second input of the first element OR, the first input of the second element OR NOT and the output of the third element OR NOT, the first input of which is connected to the first input of the first element AND, with the second input the second element OR NOT and with the input of the device operation mode setting, the second input of the third element OR is NOT connected to the enable input of outputting the result in the reverse device code, the second input of the first element OR is NOT connected to the output of the second element OR NOT, the output is The adder transfer is connected to the output of the sign of the device difference, characterized in that, in order to simplify and expand the scope of application by implementing controlled zeroing of the output of the device, it additionally contains a b-trigger, a third OR element, a second and a third AND elements, a NOT element, the UNCHARACTER element and the delay unit 15, the input of the delay unit connected to the device subtraction resolution input, the first output connected to the clock input D of the trigger and the first input of the third element OR, the second output of the delayed connector inn with the first input of the second element AND, the output of which is connected to the second input of the third element OR, the output of which is connected to the first input of the third element AND, the second input of which is connected to the input of zeroing of the P-trigger AND and the output of the element NOT whose input is connected to the output of the first And, the second input of which is connected to the zeroing input of the device, the output of the third element And is connected to the transfer input of the adder, the transfer output of which is connected to the D input of the D. flip-flop, the second input of the second And element and the first the INPUT element is input, the second input of which is connected to the output of the D-trigger, and the output is connected to the equality output of the device operands.