SU1631509A1 - Multicycle recirculating time-to-number converter - Google Patents

Abstract

The invention relates to a pulse technique. The purpose of the invention is to increase the reliability of the multi-cycle time-to-recirculation converter — code-achieved by introducing a selector-multiplexer 5 into it. D-flip-flop 9, delay element 10, AND 11 element, OR element 12, delay element 13. In addition, the converter contains an OR 1 element, an input bus 2. a delay element 3, a delay element 4, a delay element 6, a decoder 7, an AND element 8, an AND block 14, an RS-trigger block 15, an installation bus 16. 1 silt

Description

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The invention relates to a pulse technique and can be used to measure the duration of single nanosecond pulses.

The purpose of the invention is to increase reliability by reducing hardware costs.

The drawing shows a functional diagram of a multi-cycle recirculation time-code converter.

The multi-cycle recirculation time converter - the code contains the element OR 1, the input bus 2, the delay element 3, the delay multiple element 4, the selector-multiplexer 5, the counter 6, the decoder 7, the AND element 8, the D-flip-flop 9, the delay element 10, the element AND 11, the element OR 12, the delay element 13, the block 14 of the elements AND, the block 15 of the flip-flops and the installation bus 16. The input bus 2 is connected to the first input of the element OR 1, the second input of which is connected through the element 3 to the output of the element OR 12 and counting the input of the counter 6, the reset input of which is connected to the device The bus 16, the reset input of the 15 trigger block and the R-input of the D-flip-flop 9, the C-input of which is connected to the output of the selector multiplexer 5, the first input of the And 8 element and through the delay element 10 - the first input of the And 11 element, the second input of which connected to the inverse output of the D-flip-flop 9, the D- input of which is connected to the output of the element OR 1, the input of the multi-drop delay line 4 and through the delay element 13 to the second input of the element 8 and the output of which is connected to the first inputs of the block 14 and the first input of the element OR 12, the second input of which is connected to the output And 11, the outputs of the delayed element 4, are connected to the corresponding signal inputs of the selector-multiplexer 5, the control inputs of which are connected to the corresponding discharge outputs of the counter b and the inputs of the decoder 7, the outputs of which are connected to the corresponding second inputs of the block 14 elements And, the outputs of which connected to the corresponding inputs of the block 15 triggers.

The multi-cycle recirculation time converter — the code works as follows.

The multi-tap element 4 delay is made with p-1 taps, with a delay time of each of the taps, respectively: the first - TI, the second - 2 TI; the third - 22 t, the fourth - 23 ri; (p-1) -ro is the item where p is the required number of bits of the output code of the converter.

The OR 1 element, the delay element 3, the multi-tap delay element 4, the selector-multiplexer 5. AND element 8 and OR element 12 form a temporary recirculator, the output of which is the output of the OR element 12.

The delay element 10 is intended for

10 compensate for the delay time of the D-flip-flop 9, and the delay element 13 to compensate for the delay time of the selector-multiplexer 5.

Before starting the conversion, the signal 15, the scrap unit, is installed on the bus 16, the D-trigger 9, the RS-flip-flops in block 15 are set to the zero state, and the unit 6 is written to the counter 6, by means of which the selector-multiplex 20 sor connects the last ( p-1) -th tap of the multi-drop element 4 delay, the delay time of which is 2p-1 ton.

The entire operation of the converter is divided into p − 1 cycles, each of which defines one of the bits of the output code, starting with the highest one. The capacity of the counter 6 is chosen to be equal to the number of conversion cycles.

The 30 Rpntx TI at the output of the time recirculator produces a pulse of duration D txi tx - 2P n, which is fixed in the counter 6, as a result, there appears in it a fixed number equal to two.

While the pulse Atxi is delayed on the element 3 of the delay at the time ts xxmax (where 1x max is the largest value of the duration of the input signal) selector-multiplexer

40 5 in accordance with the incoming from the output of the counter 6 to its control inputs the code connects the next (p-2) -th tap of the multi-tap delay element 4 to its output, the delay time of which is 2Р TI.

45 Simultaneously, at the second output of the decoder 7, a pulse signal is produced, which, through the corresponding output of the element And block 14, is fed to the S input corresponding to this output

50 RS-flip-flops in block 15, i.e. the result of the conversion is fixed in the first cycle, i.e. the highest bit of the converter, while the second input of the corresponding element And block 14 contains the enabling pulse signal Atxi.

In the second conversion cycle, a pulse is generated at the output of the time recirculator when Atxi .2P TI

Atx2 Atxi - n tx - (+) n, which is processed similarly to the first cycle, and the third output of the decoder 7 produces a pulse signal which, through the corresponding output element of the block 14 (whose second input contains the enabling pulse signal D txa) supplied to the S input of the corresponding RS flip-flop of block 15, i.e. The result of the conversion of the second clock cycle is recorded in the next highest order in the direction of the lower bits.

This process takes place in all subsequent conversion cycles.

When received in the i-th cycle A txi 2 t

(where i 1,2 (p-1) is the sequence number of the measure

conversion), this pulse is introduced into the time recirculator and is fed to the input of counter 6 through element 11 and the second input of element OR 12. This pulse is detected by counter 6, which controls the operation of the selector-multiplexer 5, but does not take place in the unit state of the RS-flip-flop conversion corresponding to this cycle in block 15, since the pulse signal produced at the corresponding output of the decoder 7 does not pass through the matching element of the block 14 corresponding to this output, since its second input There is no enable signal.

Thus, at the end of all p-1 conversion cycles in the RS-triggers of block 15, a positional binary code representing the digital conversion result is fixed.

At the same time, the conversion time T (1 + 21 + 22 + 23 + ...) TI + (p-1) tz0

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Claims (1)

Claims of the invention Multi-cycle recirculating time converter - code. containing the input bus, the first element OR, the first delay element, the multi-tap delay element, the AND element, the counter, the decoder, the AND element block, the trigger block whose inputs are connected to the corresponding outputs of the AND element block, the input bus is connected to the first input of the first OR element, the second input of which is connected to the counter input via the first delay element, the output of the first OR element is connected to the input of the multi-tap delay element, characterized in that, in order to increase reliability, a selector-multi is introduced into it typelexer, D-flip-flop, two delay elements, second AND element, second OR element, whose output is connected to the counter input, the bit outputs of which are connected to the corresponding inputs of the decoder and control inputs of the selector-multiplexer, whose inputs are connected to the corresponding outputs of the multi-tap delay element whose input is connected to the input of the second delay element and the D input of the D flip-flop, the C input of which is connected to the first input of the first element I, the output of the selector-multiplexer, and through the third element the output ki - with the first input of the second element And, the output of which is connected to the first input of the second element OR, the second input of which is connected to the corresponding input of the block of elements And and the output of the first element And, the second input of which is connected to the output of the second delay element, the second input of the second element And connected to the inverse output of the D-flip-flop, the R-input of which is connected to the installation bus, the installation input of the trigger block and the counter, the outputs of the decoder are connected to the corresponding inputs of the block of elements I.