SU1548787A1 - Device for checking counters - Google Patents

Abstract

The invention relates to computing and can be used to periodically monitor pulse counters that operate at different times. The aim of the invention is to increase the reliability of the control. The goal is achieved by switching the device from dual-channel operation to single-channel, sequential polling of the paraphase outputs of the first and second counters and monitoring the information recorded in them with the help of a paraphase modulo two. The reliability of the operation of the paraphase modulo-two adder is controlled in a two-channel device operation mode by supplying a control action to the switching element, i.e. the generation of the paraphase code * 9811 * 98 from the output of the first multiplexer is simulated. The control device contains a counter 3 digit numbers, multiplexers 4, 5, switching element 6, paraphase adder 7 modulo two, comparison circuit 8, elements OR 9, 12, 14, 18, trigger 10, elements 11, 13, 17, the delay element 15, the generator 16 clock pulses. The device operates in three modes. The first is the two-channel operation mode, i.e. when counter 1 is connected to input 20, and redundant controlled counter 2 to input 21. The second is single-channel mode, i.e. monitored counters 1, 2 are connected to the input. The third is the control mode of the paraphase adder 7 modulo two. 3 il.

Description

one

(21) 4461403 / 24-24

(22) 06.06.88

(46) 07.03.90. Bul Number 9

(72) N.N. Novikov, A.R. Kaplan

and H.M. Ruha

(53) 681.325 (088.8)

(56) Sellers F. Detection Methods

errors in the work of the digital computer - M .: Mir, 1972,

with. 224, FIG. 12.2.a.

Kuzmin, Burnazan R.G., Kovegin A.A. Hardware control of electronic computer - M .: Energie, 1974, p. 14, fig. one.

USSR Author's Certificate No. 1015385, cl. G 06 F 11/00, 1981.

(54) DEVICE FOR CONTROLLING COUNTERS

(57) The invention relates to computing and can be used to periodically monitor pulse counters that operate at different times. The aim of the invention is to increase the reliability of the control. The goal is achieved by switching the device from dual-channel operation to single-channel, sequential interrogation of the paraphase outputs of the first and second counters and monitoring recorded in them

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information by using a paraphonic adder modulo two. Accuracy The functioning of the paraphase modulo-two adder is controlled in a two-channel device operation mode by supplying a control action to the switching element, i.e. simulating the output of the paraphase code 1 from the output of the first multiplexer, 1 The control device contains a counter 3 bit numbers, multiplexers 4 and 5, switching element 6, an interphase modulo 7 modulo two, circuit 8 compare. Consider a computing technique and periodic monitoring of pulse counters.

The purpose of the invention is to increase the reliability of the control.

FIG. 1 shows a block diagram of a meter control device; in fig. 2 - structural scheme of the multiplexer; Fig. 3 is an electrical circuit of a switching element.

The device contains the main 1 and duplicate 2 counter-controlled counter 3 discharge number, the first 4 and second 5 multiplexers, switching element 6, paraphase summer 7 modulo dvl, comparison circuit 8, element OR 93 control trigger 10, elements AND 1 1, OR 12, AND 1 3 s OR 14, delay element 15, generator of 16 clock pulses, elements AND 7, OR 18, output 9 of the discharge number, first 20 and second 21 information inputs of the device, 22 input reset devices, device control start-up input 23, device self-control device input 24, the first 25 and the second 26 groups s information device outputs, control output 27 of the device.

Multiplexers 4 and 5 (Fig. 2) contain direct 28 and inverse 29 outputs, decoder 30, AND 31-36 elements OR 37 and 38 HE 39 and AND 40. The switching element (Fig. 3) contains relay AND 4 and contact 42 relays.

The device works as follows.

The Reset signal from input 22 enters the counters 3 and the trigger 10, which

nor, elements OR 9, 12, 14, and 18, trigger 10, elements AND 11, 13, and 17, delay element 15, generator of 16 tat pulses. The device operates in three modes. The first is the two-channel operation mode, i.e. when counter 1 is connected to input 20, and redundant controlled counter 2 is connected to input 21. The second is single-channel mode, that is, monitored counters 1, 2 are connected at the input. The third is the control mode of the paraphase adder 7 modulo two. 3 il.

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The latter are returned to their original (zero) state.

The device can operate in three modes: the first is the two-channel operation mode, i.e. when counter 1 is connected to the first information input 20 of the device, and counter 2 to the second information input 21 of the device, the control action on input 24 is zero; the second mode is single channel, i.e. when counter 2 is disconnected from input 21 and connected to input 20 and the operation of counters 1 and 2 is monitored, the third is a two-channel mode, with a control action at input 24, equivalent to logical 1, i.e. control mode paraphase adder modulo two.

When the first mode is implemented, the trigger 10 is in the zero state, this provides the connection of the counting output of counter 1 to the input 20, and the counter 2 to the input 21, which carry out the counting of the pulses arriving at the inputs 20 and 21.

When implementing the second mode, a control signal is applied to the input 23, which ensures the transfer of the trigger 1 0 to one state. In this case, elements 11 and 17 are prepared for opening, and element 13 is closed. The counting input of the counter 2 is connected to the input 20. The counting input of the third counter 3 is connected to the generator 16. The frequency of the pulses generated from the generator 16 is chosen so that for the duration of the presence of the pulse at the input 20, the counter 3 from the generator 16 is recorded

the number of pulses required to interrogate all the outputs of counters 1 and 2 (counters 1 and 2 are the same in capacity of the memory).

In accordance with the received code from counter 3 to the decoder 30 of multiplexer 4 and 5 (by construction they are identical), the same-name paraphase outputs of counters 1 and 2 are connected to the inputs of the paraphase adder 7 modulo two, which performs the following function:

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At the output of the paraphase adder 7 modulo two, when the counters are operating correctly, a code is formed at the outputs c /, and,. In the event of a malfunction in the first 1 or second 2 pulse counter at the output of the paraphase adder, modulo two, a code 1.0 is formed, i.e. output 2 will be given a signal through the element

OR 9 on the presence of a fault. The operation of the paraphase adder 7 modulo two is controlled by the comparison circuit 8. If at the output of block 7 a code of 0.0 or 1.1 is generated, circuit 8 will signal a fault at output 27 (i.e., codes 00, 10, 11 - failure codes).

When the nth output is excited in the counter 1, after the delay time determined by the delay element 15, the trigger 1 is set to the zero state. When the m + 1-ro output is excited in the counter 3, it is reset to the initial state.

When implementing the third mode of operation of the device, the trigger 10 is in the zero state, i.e. the device operates, in two-channel mode, the output of multiplexers 4 and 5 is 0.1, that is, at output 28, the signal is equivalent to logical O, and output 29 is logical 1. When the control input is applied to input 24, the switching element issues a signal equivalent to logical 1, to input b, paraphase adder 7 modulo two, which must be at outputs o (o, o (4 give the code 1.1. This code is fixed by comparison circuit 8 and output to the output 27 of the device, if this does not happen, means that the elements involved have a fault.

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A device for controlling counters, containing the first and second multiplexers, the comparison circuit, the first element OR, the first - the third element AND, and the control trigger, the unit input of which is connected to the control start input of the device, and the direct output to the first input of the first element AND, the second the input of which is connected to the first information input of the device, characterized in that, in order to increase the reliability of the control, a bit number counter is entered into it, the second - the fourth OR element, a delay element, a clock pulse generator owls, and switching element paraphase adder modulo two, first information input device serves for connecting the main controlled counter input of the counter, the first 5 ravl yn yuschy input device serves to

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connect the high-order output of the main controlled counter and is connected to the input of the delay element, the inverse output of the control trigger is connected to the first input of the second element AND, the second input of which is connected to the second information input of the device, and the output to the first input of the first element OR, the second input of which connected to the first input of the third element AND and the second input of the first element OR, the output of which is the output of the device, which serves to connect to the counting input of the redundant controlled account the second input of the third element AND is connected to the output of the clock pulse generator, and the output to the counting input of the discharge number counter, whose information outputs are connected to the address inputs of the first and second multiplexers, and the overflow output - with the first input of the second element OR, the second input which is connected to the reset input of the device and the first input of the third element OR, and the output is connected to the installation of the discharge number in O, the second input of the third OR is connected to the output of the delay element, and the output with zero in control trigger, first and second groups of information inputs of the device are used to connect the outputs of the main and backup

controlled counters to groups of information inputs of the first and second multiplexers, respectively; the direct and inverse outputs of the first multiplexer are connected respectively to the first and second inputs of the first modular paraphase two adder, the first input of the second component is connected to the output of the switching element, the control input which is connected to the device self-control input, and the information

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the input is with the direct output of the second multiplexer, the output of which is connected to the second input of the second addend paraphase modulo two, connected by the direct output to the first inputs of the comparison circuit and the fourth OR element, the output of which is connected to the control output of the device, and the second input is with the output of the comparison circuit, the second input of which is connected to the inverse output of the para-phase adder and module two.

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Claims (1)

The formula of the invention. shenia A device for monitoring counters, containing the first and second mul · 5 typlexers, a comparison circuit, the first OR element, the first - the third AND elements, and a control trigger, a single input of which is connected to the IQ input of the device control start, and a direct output to the first input of the first element .nta AND, the second input of which is connected to the first information input of the device, characterized 15 in that, in order to increase the reliability of control, a discharge number counter is introduced into it, the second to the fourth OR element, a delay element, a clock pulse generator, 20 switching element and a two-phase adder modulo two, the first information input of the device is used to connect the counting input of the main controlled counter, the first up25 equalizing input of the device is used to connect the high-order output of the main controlled counter and is connected to the input of the delay element, the inverse output of the 3Q control trigger is connected with the first input of the second AND element, the second input of which is connected to the second information input of the device, and the output to the first input of the first OR element, second the first input of which is connected to the first input of the third AND element and the second input of the first OR element, the output of which is the output of the device serving / for connecting to the counter input of the duplicate monitored counter, the second input of the third AND element is connected to the output of the clock generator, and the output to the counting input of the number · discharge counter, the information outputs of which are connected to the address inputs of the first and second multiplexers, and the overflow output is connected to the first input of the second OR element, the second input of which is sub is connected to the device reset input and the first input of the third OR element, and the output is to the setting input of the discharge number counter at 0, the second input of the third OR element is connected to the output of the delay element, and the output with the control trigger zero input, the first and second groups of device information inputs serve to connect the outputs of the main and backup monitored counters to groups of information inputs of the first and second multiplexers, respectively, the direct and inverse outputs of the first multiplexer are connected respectively o with the first and second inputs of the first term of the paraphase adder modulo two, the first input of the second term of which is connected to the output of the switching element, the control input of which is connected to the input of the device’s self-control, and the information input with the direct output of the second multiplexer, the inverse output of which is connected to the second input the second term of the paraphase adder modulo two, connected by a direct output to the first inputs of the comparison circuit and the fourth OR element, the output of which is connected to the control output devices, and the second input - with the output of the comparison circuit, the second input of which is connected to the inverse output of the paraphase adder and module two.