SU1381513A1 - Device for checking terminals of lsi - Google Patents

Abstract

The invention relates to digital computing and can be used in the design of self-controlled large integrated circuits (LSI) for digital computers and systems. The purpose of the invention is to increase the efficiency of monitoring by ensuring verification of the findings in one cycle and expanding the field of application of the device by providing the possibility of combining the monitoring of the conclusions of the LSI with the control of the correctness of its operation. The device for monitoring the LSI outputs contains element 2I-OR 1, switch 2, decoder 3, clock generator 4, trigger triggers 5 and control 6, group 9 elements And, first 10, second II and third 12 elements And, demultiplexer of conclusions 7, multiplexer 8. 3 Il. (L

Description

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The invention relates to digital computing and can be used in the design of self-controlled large integrated circuits (VIS) for digital computers and systems.

The purpose of the invention is to increase the control efficiency by ensuring verification of the findings in one cycle, as well as expanding the field of application by providing the possibility of combining the control of the LSI conclusions with the control of the correctness of the operation.

Figure 1 shows the functional diagram of the device; 2 is a diagram for connecting the second output of the demultiplexer to the first input of the multiplexer; FIG. 3 is a time diagram of the operation of the device.

The device for monitoring the LSI outputs (Fig. 1) contains element 2I-OR 1, switch 2, decoder 3, 4 clock pulse generator, start trigger 5 and control 6, demultiplexer 7, multiplexer 8, group 9 of elements I, the first 10, the second 11 and the third 12 elements And, information input 13 of the multiplexer, information input 14 and output 15 of the device, output 16 of switch 2, output 17 of the trigger 5 start, failure output 18, test input 19 and output 20 of the response of the controlled LSI to test effects of the device, output 21 of the multiplexer 8, the first 22 and second 23 outputs of the gene erator 4.

Element 2И-Ш1И 1 is intended to form a generalized signal of failure in accordance with the logic function

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Z x L y, + X, L y,

where X "(O, 1) is the control value

signal;

у.е (0,1) - signal value i-r of the information input bit;

, n is the bit number of the information input. With a zero (single) value of the control signal, if a code containing at least one unit (one zero) arrives at its information input, then a zero signal is formed at its output.

Switch 2 is designed to switch operating information from device 14 (control code

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from the trigger output 6) to the module outputs in the (zero, one) state of the 5 start trigger. The decoder 3 krda start control is designed to generate a control signal trigger trigger 5. The clock pulse generator 4 is designed to form a sequence of clock pulses that synchronize the operation of the device. The trigger 5 is designed to generate a control signal for the start of the 4 clock pulse generator. A control trigger 6 is designed to generate a control code and control the operation of the device.

The demultiplexer 7 serves to switch the output signals of the device. With a single signal at its control input, the signals arriving at its information input are switched to its first output, which is device output 20, and with a zero control signal, the signals arriving at its information input are switched to its second output. The multiplexer 8 is designed to connect the inputs of the module i LSI with the output of the demultiplexer with a zero control signal, with the test input 19 of the device with a single control signal. A group of 9 elements And is designed to disconnect the module from the pins while monitoring them.

Element And 10 serves to control the recording of information in control trigger 6. Element And 11 serves to generate a failure signal. Element And 12 is designed /. The formation of the signal off trigger trigger 5.

The device works as follows.

In the initial state, the start 5 and control 6 triggers are reset, output 17 contains a single signal (the initial state setting circuits, common for the LSI module circuit and for the proposed device, are not shown conventionally). In this case, the demultiplexer 7 switches the output 16 of the switch 2 to the output 20 of the device, and the multiplexer 8 connects the input 19 of the device to the information input of the group, 9 elements I.

To organize the outputs of the LSI module at the input 19 of the device go: give the control start code, which through multiplexer 8 and a group of 9 elements comes to the input of the decoder 3 of the control start code, which generates a single signal at its output. By this signal, the start trigger 5 is set to one. The single signal from its direct output goes to the input of generator 4, and the zero signal from the inverse output goes to the control inputs of switch 2, group 9 of elements I, multiplexer 8, and demultiplexer 7.

The demultiplexer 7 recommutes the output 16 of the switch 2 to the first information input of the multiplexer, and the multiplexer 8 connects the information input of a group of 9 elements AND to the second output of the demultiplexer. Thus, the derivation; the module corresponding to its outputs are connected to its terminals corresponding to its inputs.

The zero control code formed by control trigger 6, through switch 2, demultiplexer 7 and multiplexer 8, passes through the module outputs to the information input of element 2I-OR I. If the code arriving at information input of element 2I-OR 1 is at least one unit (which corresponds to the presence of at least one fault of type constant 1 or break), then at its output there is a zero and a sequence of clock pulses generated by generator 4 at the second output 23, through the element AND And arrives at the output 18 of the refusal a. If the fault constant 1 is absent, then at the output of element 2I-OR 1, the unit also appears on the trailing edge of the first clock pulse generated by at the trailing time determined by the circuit of the control code and the operation of element 2I-OR 1 (j). the first output 22 of the generator 4, the trigger 6 goes into one state. A single code arrives at the information input of element 2I-OR (all bits are single) A unit is formed at the output of element 2I-OR 1 after a delay time, which corresponds to the absence of faults of the constant type O or short circuit. The first pulse generated at the output 23 of the generator 4 passes through the element 12 and trigger start 5 goes to the zero state. A single signal with

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its zero output brings the module into working state (opens a group of 9 elements AND and switches switch 2), and also, arriving at the control inputs of the demultiplexer 7 and multiplexer 8, performs a re-switching, due to which the output of the module is connected to the test input 19 and output 20 of the reaction device.

Next, you can begin to check the correctness of the function of the LSI module, for example, by testing, applying control tests to the device input 19, and removing the response of the LSI module circuit to these tests from the device output 20. The code for starting the monitoring of the outputs of the LSI module can be placed as the first test in the test sequence used to monitor the correctness of the operation of the LSI module, and the monitoring of the outputs of the module can be used as a subcontrol of the more general monitoring of the correctness of functioning. Such an organization of monitoring the outputs of the LSI module eliminates the time costs of monitoring the correct functioning of the module with faulty outputs, as well as connecting the LSI module to various control devices. If at least one fault of the constant type O is present, then the information input of the element 2И-OR 1 receives a code containing at least one zero. At the output of element 2I-OR I — after a time delay i, a zero signal is generated, and the sequence of pulses generated at the second output 23 of the generator 4 enters through the element. And 11 to exit 18 device failure.

In this way, the conclusions of the module are monitored before starting to check its correct functioning.

Claims (1)

Invention Formula A device for monitoring the outputs of large integrated circuits containing a switch, a decoder, a clock generator, start and control triggers, a group of elements AND, the first and second elements AND, and the outputs of elements AND of a group are connected to a group of information inputs of the decoder and form the output of the device for connection to control input -, 5138 a large integrated circuit, the output of the decoder is connected to the S-input of the start trigger, the zero output of which is connected to the first inputs of the AND elements of the group and the control input of the switch, the single output of the trigger trigger is connected to the start input of the clock generator which is connected to the first and second outputs respectively, with the direct input of the first and the direct input of the second elements AND, the first information input of the switch is the device input for connecting to the output of the monitored large integrated circuit, exc It was found out that, in order to increase the control efficiency by providing verification of the findings in one cycle and expanding the scope of application by providing the possibility of combining the control of the outputs of a large integrated circuit with the control of its correct operation, the device contains an element 2 AND-OR, a duplexer and a third element And, moreover, the group of outputs of the multiplexer is connected to the second inputs of the elements AND of the group, with the group of information inputs of the element 2И-ИПИ, the outputs of the element 2И-OR are connected to the D-INPUT of the control trigger laziness, inverted input of the second AND gate and the first input of the third AND gate, five 0 five 0 36 the output of which is connected to the R-input of the start trigger, the output of the control trigger is connected to the second information input of the switch, to the control input of element 2I-OR, to the inverse input of the first element AND, and to the second input of the third element AND ,. the third input is connected to the second clock pulse output, the zero trigger start output is connected to the control inputs of the demultiplexer and multiplexer. The switch output is connected to the information input of the demultiplexer, the first output of which is controlled by the test effects of the device. , the i-th bit of the second output of the demultiplexer is connected to the (j n 1) th bits of the first information input of the multiplexer, (where n is the output size controlled by where K is the number of groups of bits of the input of the controlled circuit, the number of bits in the groups from the 0th to (K-1) -th is n), the second information input of which is the input of the device tests, the output of the second element And is the output of the device failure, the output of the first element AND is connected to the synchronization input of the control trigger. Y / 7 / /. . . / 7 corner L ..J (rig 2 7