RU1805471C - Device for control of logical units - Google Patents

Abstract

The invention relates to computer technology and can be used in test diagnostic systems for digital objects. The purpose of the invention is to increase the reliability of control. The goal is achieved due to the fact that the use of the signature analyzer in the invention not only for analyzing the output sequences of the object of control (K), but also for generating input sequences for it, allows us to abandon the special means of generating test sequences. In addition, with a fixed number of OK inputs, a positive test result, regardless of the type of OK, always corresponds to only one signature value, which increases the universality of the device and facilitates the analysis of test results. The device comprises a signature analyzer 2, a decoder 4, a comparison unit 5, a reference sequence generator 3, a clock generator 6 and a delay element 1. 1 or

Description

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The invention relates to the field of computer engineering and can be used in test diagnostic systems for digital objects.

The purpose of the invention is to increase the reliability of control.

The drawing shows a functional diagram of a device that contains a delay element 1, a signature analyzer 2, a reference sequence generator 3, a decoder 4, a comparison unit 5, a clock pulse generator .6, a start input 7.

The drawing also shows a controlled logic unit 8.

The device operates as follows,

The Start signal includes a clock 6, which at the first output generates a reset pulse of the signature analyzer 2 of the initial installation of the monitored logic unit 8 and generator 3. Generator 3 is, for example, a typical circuit on the address counter and ROM. Then, the clock generator 6 at the second output generates a series of pulses clocking blocks 2, 3, and 8. The number of clock pulses in a cycle of exhaustive search of input actions is determined by the number of inputs n and is equal to 2P.

The incompatible inputs k of block 8 are stimulated through a decoder 4, which excludes the simultaneous supply of the same stimuli to them. For a healthy block 8, the value of the information bit of test sequence A is always 1 in each control cycle.

Delay element 1 takes into account the transient response times of blocks 8, 3, and 5.

According to the first clock pulse from the output of the generator 6, block 8 is stimulated with the first input set. At the same time, the first m-bit word is called up from the memory of the generator 3, in this case for the healthy block 8, the relations Vc O) will always be executed, where is the number of the control beat, and m is the number of the compared bit.

The result of the comparison from the output of block 5 is fed to the information input D of the signature analyzer 2. Information is recorded in the first bit of the register of block 2 at the input D with the arrival of the clock signal at the input, taking into account its delay in block 8. At the same time, the outputs of block 2 will be generated 2 input set. For each subsequent clock pulse, the described cycle is repeated.

After the end of the control cycle, as after all the 2P clock pulses passed, the final signature will be recorded in the signal analyzer 2, based on the comparison of which with the reference one we can conclude about the technical state of block 8,

Claims (1)

SUMMARY OF THE INVENTION A logic block monitoring apparatus comprising a signature analyzer, a clock, a delay element, and a decoder, wherein the start input of the device is connected to the start input of the clock, the first output of which is connected to the reset input of the signature analyzer and is the first output of the device for connecting to the input of the initial installation of the controlled logic unit, the group of outputs of the decoder form the first group of information outputs of the device for connecting the first group of inputs of the monitored logic unit, the second output of the clock generator is connected through the delay element to the clock input of the signature analyzer and is the second output of the device for connecting to the clock input of the monitored logic unit, characterized in that, in order to increase the reliability of the control, it further comprises a reference sequence generator and a comparison unit, the output of which is connected to the information input of the signature analyzer, the first group of information the output of which is connected to the group of inputs of the decoder, and the second group of information outputs forms the second group of information outputs of the device for connecting to the second group of information inputs of the controlled logic unit, the group of outputs of the generator, the reference sequence is connected to the first group of inputs of the comparison unit, the second group of inputs of which are is a group of information inputs of the device for connecting to the group of outputs of a controlled logical unit, the input of the initial installation, and so on Marketing input reference sequence generator connected to first and second outputs of the clock.