SU1264181A1 - Device for checking large-scale integrated circuits - Google Patents

Abstract

It is related to digital computing and can be used in the design of self-controlled large and super-large integrated circuits for digital computers and systems. The purpose of the invention is to increase the control and increase testability / simplify the control process /. . A device for controlling an LSI contains a decoder of pin numbers, a synchronization unit, two groups of units of elements I, a switch of control codes, a unit for analyzing the result, a block of switches for pairs of outputs, a group of input switches. This technical solution provides higher completeness and reliability of control of LSI outputs and eliminates the omission of constant faults. In addition, the process of control is simplified due to the adaptability of the circuit to the pro (LIs of the LSI circuits by switching its inputs and outputs. 1 Cp f-crystals, 3 Il.

Description

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and the invention relates to u-digital computing and can be used in the design of self-controlled large and extra-large integrated circuits for digital computers and systems. The purpose of the invention is to increase the completeness of control and increase testability (simplification of the control process). Figure 1 presents the scheme of the device; figure 2 - block diagram of the analysis of the result; on fig.Z - diagram of the synchronization unit. The device contains a result analysis block 1, a synchronization block 2, blocks 3.1 - 3, M-and 4.1-4.N elements of the first and second groups, input 5 of the initial installation, input 6 of the start information inputs 7 and outputs 8 of the device, output 9 of the result , counter 10, decoder P pin numbers, input switches 12.1 -12.N groups, switch 13 control codes, block 14 specifying control codes, block 15 of switch pairs of pins. The result analysis unit 1 (FIG. 2) contains an error switch 16, error trigger 17, a comparison circuit 18, a group of elements OR 19 second 20 first 21 groups of information inputs, a synchronous input 22.1 and an input 22.2 of the decision to output an error signal, control end input 23 , exit 24 no error. The synchronization unit 2 (FIG. 3) contains the first 25, third 26, second 27, fourth 28 outputs second reset input 29, pulse generator 30, triggers 31-33, decoder 34, OR element 35, And elements 36 and 37 The monitoring of the integrity of the outputs of the BIS device module is carried out as follows. The cycle of checking the pair of outputs of the LSI module consists of two cycles. At the first time, from the direct output of block 14, through the switch 13 and the corresponding switch 12 of the direct control code group from the device output goes to the corresponding input of block 15. In addition, this code is interpreted from the output of the switch 13 to the input of block 1. The control code, having passed through block 15, is fed to the input of the corresponding blocks 3.1 and 4.1 of the elements 12 and then to the input of block 1. In block I, the codes received are compared his inputs. In the first cycle of the first cycle, by comparing the value of the direct code derived from the LSI output and obtained at its input, the corresponding pair of pins is checked for the absence (presence) of faults in them or the constant O. constant type 1 code i-rc bit is equal to O, then as a result of checking the break of one output of the controlled output will be detected, since in this case the value of i-ro bit in the code received on the LSI input is equal to 1. In the case the first cycle of a cycle of integrity violations you No water, the device moves to the second cycle of operation. In the second cycle, the reverse control code is output from the inverse output of the control code setting unit 14. Thus, faults that were not detected in the first cycle (for example, a short circuit of the i-ro output of the controlled output) will be detected. In the event that there are no deviations from the norm in the corresponding pair of controlled conclusions, the transition to the control of the next pair of conclusions takes place automatically. This transition is carried out by increasing the contents of the counter 10 in the second cycle of the cycle. Consequently, with such an organization, the control of the forward and reverse code of the LSI pairs of terminals provides detection of: all constant fault faults. In the initial state, all the memory elements are in the zero state. In block 15, the switches are in the On position. Operation code Control is fed to input 6 of the device. The operation code is fed to the input of the decoder 34. A single signal from its output is fed to the S input of the trigger 31, which is set to one state. A single signal from the direct output of the trigger 31 triggers the generator 30 and a clock pulse appears at its output nerve. This signal is fed to the second input element And 36, the first input of which receives a single

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the signal from the zero output of the trigger 17 of block 1. The first pulse from the first output of the generator 30, having passed through the element 36, arrives at the counting input of the trigger 32 and switches it to the unit state. From the first output of the block 14, the direct control code goes through the switch 13 to the first information inputs of the switches 12.1 to 12.N and the second information input, block 1.

The single signal, which appeared at the zero output of the decoder 11 as a result of the arrival of a single signal at its input, opens the switch 12.1, and the control code from the LSI output goes to the corresponding input of block 15. The control code passes through the closed toggle switches of block 15 and goes to the same open a single signal from the zero output of the decoder J1 block of elements AND 4.1 and further to the first information input of block 1. The clock pulse from the second output of the generator 30 through the open element And 37 enters the synchronous input of the trigger 17. In that case In addition, if the codes received at the inputs of block 1 match, there is no single signal at its output and trigger 17 remains in the initial state. Otherwise, on the falling edge of this sync pulse, trigger 17 switches to the single state and at the output of switch 16 appears a sequence of clock pulses, signaling a malfunction of the BIS outputs.

Simultaneously, on the falling edge of the same clock pulse, the trigger 33 is switched to one state. In the event that no fault is detected, on the falling edge of the sync pulse received from the first output of the generator 30, the trigger 32 switches to the initial state. From the second output of the block 14, the inverse control code arrives at the output of the switch 13. This code simultaneously arrives at the second information input of block 1. From the output of the switch 12.1 through block 15, the inverse control code is fed to the input of block 4.1 of the elements I and to the first information input of block 1.

The next clock pulse from the second output of the generator 30 is fed to the synchronous inputs of the trigger 17 and 33.

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The leading edge of this pulse is the recording of the result of checking the integrity of the outputs in the trigger 17. The trigger 33 returns to the initial state. In this case, the counter 10 recorded unit. At the first output of the decoder 11 a high potential is formed. On the trailing edge of the next clock pulse from the first output of the generator 30, the trigger 32 switches to one state. For the next couple of conclusions, the LSI is supplied with a direct control code. The test cycle repeats. After checking the last pair of LSI outputs, a single signal is generated at the nth output of the counter 10, which is fed through the OR element 35 to the R input of the trigger 31. As a result, the clock pulse from the output of the generator 30 stops.

The output 9 of the device through the switch 16 receives a single signal, indicating the end of the control and the health of the LSI terminals.

Claims (2)

Invention Formula 1. A device for controlling an LSI that contains an encoder of code numbers, two groups of AND blocks, a switch of control codes, a block of setting control codes, a counter, a synchronization block, a block of performance analysis, a group of input switches, and the outputs of the block of setting control codes are connected to information inputs of the switch of control codes, the direct and inverse control inputs of which are connected to the first output of the synchronization unit; the first groups of information inputs of the input switches of the group are connected to the output Dami controlled LSI, the inputs of which are connected to the outputs of the element blocks of the first group, the start input of the device is connected to the start input of the synchronization unit, the first control inputs of the input switches of the group and the control inputs of the element blocks of the first group are connected to the second output of the synchronization unit, the decoder outputs pin numbers are connected to the second control inputs of the input switches of the group, the input of the initial installation of the device is connected to the reset inputs of the counter, the result analysis unit 512 This and the first reset input of the synchronization unit, the first group of information inputs of which are connected to the outputs of the element blocks of the second group, the control inputs of which are connected to the outputs of the pin number decoder, the third and fourth outputs of the synchronization block are connected respectively to the counter count input and the pin number decoder sync input , that is, that, in order to increase the completeness of control, it contains a block of switches of pairs of terminals, and the inputs of the block of switches of pairs of terminals are connected to the outputs of the input switches of the group, and the i-th output of the group of outputs to the information inputs of the ix blocks of the elements of the first and second groups, the output group of the switch of control codes is connected to the second groups of information inputs, the input switches of the group and the analyzer block. the control of which is connected to the overflow output of the counter connected to the second reset input of the synchronization block, the group of the output of the counter is connected to the input group of the pin number decoder, the output from the absence of an error of the analysis block p Ezul; Tata is connected to the sync pulse sync pulse enable input. The fifth and sixth outputs of which are connected respectively to the synchronous input and the enable input, outputting the error signal of the result analysis block, the output of which is the output of the device. 2. The device in accordance with claim 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 2), the result analysis block contains a group of elements ISH1, a comparison circuit, an error trigger and an error switch, and the inputs of the elements of OR group are the first group of information inputs of the block, the first and second groups information inputs of the comparison circuit are connected, respectively, with the outputs of the OR elements of the group and the second group of information inputs of the block; the output of the comparison circuit is connected to the information input of the error trigger, the synchronous input and. the reset input of which are the same inputs of the block, the single and zero outputs of the error trigger are connected to the information inputs of the switch. The errors, the first and second control inputs of which are respectively the input of the control end and the enable input of the error signal of the block, the zero output of the error trigger and the output switch errors are respectively the output of no error and the output of the block result. one 5.N 22.2 22. 5 /9 / .2 f6 With f 0 2f (25