SU1741136A1 - Device for checking multiplexer - Google Patents

Abstract

The invention can be used in automation and computing devices for monitoring the health and troubleshooting of a multiplexer with a large number of channels, consisting of a multitude of elementary multiplexers connected in a multi-step scheme. The purpose of the invention is to expand the scope by defining a faulty element in multi-stage multiplexers. The goal is achieved by the introduction of a shift register, two switches, a comparator unit, a display unit, a trigger, a pulse shaper, three AND elements, and OR and NOT elements, ensuring the operation of the device alternately in control mode and in fault finding mode. If a fault is detected in the monitor mode, the fault search is carried out alternately on all channels, starting with the penultimate stage. The faulty element is determined by the channel number and the stage number, 3 Il. sl C

Description

The invention relates to automation and computing and can be used to monitor operability and troubleshoot multiplexers.

A device for monitoring the switching of information channels is known, containing (1 + 1) multiplexers for n bits each, n code comparison blocks, pulse distributor, two decoders, a frequency divider counter, n And elements, trigger, pulse shaper, and two OR elements monitors I information channels for n bits each and detects faults Open, Short, Switching Error.

A disadvantage of the known device is great complexity.

Closest to the present invention is a multiplexer control device comprising a clock pulse generator, four counters, a pulse distributor, a decoder, two display units, three AND elements, an OR element and a NOT element, the pulse distributor outputs are information outputs of the device for connection to information the inputs of the monitored multiplexer; the outputs of the first counter are the address outputs of the device for connection to the control inputs of the monitored multiplexer.

The device is designed to control multiplexers with a small number of FNJ channels. As the number N increases, the number of outputs increases.

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pulse bodies and, accordingly, the number of connections between the controlled multiplexer (MSC) and the device. Therefore, it is most commonly used to control multiplexers with a small number of N channels, i.e. IC type 155 KP1, 155KP5, 555KP12, etc. These ICs are also used to implement a MFC with a number of channels based on a multi-stage (pyramidal) scheme consisting of m elementary multiplexers (EMI). The device makes it possible to determine the suitability of a current MFC, although this requires an increase in the amount of equipment.

The disadvantage is that the device does not allow to determine the place of failure - in which stage and which EMF failed.

The aim of the invention is to expand the scope of use due to the possibility of determining the defective element in multistage multiplexers.

This goal is achieved in that the device for controlling the multiplexer, which contains a clock generator, four counters, a pulse distributor, two display units, three AND elements, the first OR element and the NOT element, the information input of the first counter being output by the device connected to the address input of the controlled multiplexer, the output of the clock pulse generator is connected to the first input of the second element AND, the start input of the pulse distributor and the counting input of the second counter, the output of The completions of which are connected to the reset input of the second and third counters, the counting input of the first counter and the first input of the third element, the overflow output of the first counter connected to the reset input of the first counter, the output of the third element I connected to the counting input of the fourth counter, the overflow output of which is connected to its input reset and the input of the first display unit, the output of the first element OR through the first element is NOT connected to the second input of the first element AND, the output of the second element AND is connected to the counting input tr the second counter, two switches are entered, a shift register, a comparison unit, a third indication unit, a trigger, a pulse shaper, fourth to sixth AND elements, a second OR element, and an NOT element, with the output of the first switch being the output of the device to be connected to the information input multiplexer, information and control inputs of the first switch are connected respectively to the output of the pulse distributor and information output of the second counter, the overflow output of which is connected to the first the input of the fourth element And, the output More Comparison Unit is connected to

the second input of the fourth element AND and the first input of the fifth element AND, the output of which is connected to the first input of the first element OR, the output of the fourth element AND and the first input of the fifth element AND,

the output of which is connected to the first input of the first element OR, the output of the fourth element AND is connected to the first input of the second element OR, the second input of which and the first input of the sixth element AND are connected

with the overflow output of the first counter, the output of the second element OR is connected to the synchronous input of the shift register, the group of outputs of which is connected to the group of inputs of the second display unit and the control

the inputs of the corresponding channels of the second switch, the information inputs of the channels of which are a group of inputs of the device for connection to the outputs of the respective stages of the monitored multiplexer, the output of the second switch is connected to the second input of the second element I, the information output of the third counter is connected to the first input of the comparator, the second input of which

connected to the code input of the device, the Equality output of the comparator unit is connected to the second input of the third element I, the information output of the first counter is connected to the input of the third display unit,

the output of the last bit of the group of outputs of the shift register is connected to the second output of the sixth And element and through the second element NOT to the second input of the fifth And element, the overflow output of the fourth counter

connected to the third input of the sixth element I, the output of which is connected to the synchronous input of the trigger, the installation input to 1 of which through the pulse shaper is connected to the output of the first bit of the output group

the shift register, the trigger output is connected to the second input of the first element OR.

FIG. 1 shows a block diagram of the device; in fig. 2 - functional diagram of the switch 12; in fig. 3-functional switch layout 13.

The device contains a clock pulse generator 1, elements 2 and 3, a pulse distributor 4, counter 5, elements 6 and 7, counters 8 and 9, a monitored multiplexer 10, an indication block 11, switches 12 and 13, a comparison block 14, an And element 15, the element IL AND 16, the shift register 17, the display unit 18, the counter 19, the display unit 20, the AND element 21, the trigger 22, the OR element

23, elements 24 and 25, code input 26, driver 27 pulses.

The invention can be implemented on the basis of IC series 155. All counters of the device are switched on the leading edges of the pulses on the counting inputs. The reset of the counter 8 occurs on the falling edge of the pulse at the reset input. The shift in register 17 is made on the falling edge of the input pulse. The initial state of register 17 is O in all bits except the last, into which 1 is written. The initial state of all counters and triggers is zero. The installation of the initial state is carried out; before the start of the control of the established MSC, the circuit of the installation is conventionally not shown,

The device operates in two modes: in the control mode, and in the fault finding mode.

Consider the operation of the device in control mode. At the output of the element OR 23, the level O is set, at the output of the inverter 24 is 1. At the same time, the element AND 2 transmits clock pulses of duration t ™ at a frequency of fo from the output of the generator 10

torus 1 to the input of the counter 5. The duration t ™ is chosen longer than the total delay time of the pulses introduced by the elements 4,9,12,10 and 13, which is necessary to ensure the formation of the output element And 3 of the pulse with a duration sufficient for reliable counter 8 is triggered. Counter 5 divides the frequency fo by a factor N, Hz N is the number of channels in the MMP. Distributor 4 pulses are triggered by clock pulses of frequency f and generates at their outputs K pulse sequences with frequency fq / K shifted by each relative to each other to the interval to. These K sequences for N cycles, the switch 12 alternately connects to the K-inputs of each of the main systems of the elementary multiplexers of the first stage of the ILC in accordance with the address codes generated by the counter 5. In the meantime, only one of the N-inputs will arrive pulse that does not coincide with pulses on other inputs.

Counter 9 is started with clock pulses at a frequency of fo / N and generates an address code with a number of bits. The counter module Ng is 2P and is selected from the condition NgЈN. At the outputs of counter 9, a permanent address code is selected at the N-to time, by which one of the N MCC channels is selected. The address code is divided into I groups of bits in accordance with the number of stages in the MMP,

The first group of m low-order bits is connected to the address inputs of the first-stage main electromagnetic field (mi $ 2n1), the second group of bits n2, starting with (n + 1) is connected to the address inputs of the second stage EMF, etc. The last group of bits is connected to the address inputs of a single EMI of the last stage.

The first group of bits of the address code ni determines the corresponding EMI from the mainstream and its channel that should pass the input pulse. Correspondingly, groups of bits-P2ni determine the EMI in subsequent stages, as a result of which the channel is formed by a serial connection I of the EMI, through which the input pulse arrives at the output of the last stage. Checking one selected channel takes N ticks, during which this channel is checked for skip the input pulse, and the remaining channels to ban the pulse. As a result, for N clocks, a single pulse must arrive at the output of the MMP, which passes through the switch 13 and the I 3 element at the input of the counter 8. With a good MFC, the state of the counter is 00 ... 01. The same code is set from the code input of the device 27 to the input of the comparator block 14, which generates level 1 at the Equality output, which indicates the equality of the codes. At the same time, the overflow pulse of the counter 5 passes through the AND 6 element to the input of the counter 19. In N cycles, all the N MCC channels are checked and the counter 19 overflows simultaneously with the overflow of the counters 5 and 9, which ensures the passage of the pulse through the AND element 21 and switching the trigger 22 at 1. At this time, the And 2 element is closed and the arrival of the clock pulses is stopped. The display unit 20 signals the operator about the health of the ILC.

If the MFC is faulty, the number of pulses a counted by the counter 8 per N clock cycles is greater than 1. For the number of pulses, a fault is considered as a connection error, and if a fault is considered as a break. Thus, in case of malfunction in the MFC at the output More than the code comparison block 14, the level 1 is set to the moment of the end of the Nth cycle of the monitoring mode, therefore the overflow pulse of the counter 5 passes through the element 7 and the element IL 16 to the input of the shift register 17. At the same time, 1 of the higher bit I shifts to the left in (1-1) - th bit d 00 ... 10. The monitoring mode ends and a fault finding mode starts.

Consider the operation of the device in the fault finding mode. In the control mode, the switch 13 was connected to the input

counter output of the ILC (output of the last 1st stage of the ILC). In the search mode, the switch connects to the input of the counter 8 outputs tm EMF (S) -th stage. This connection is provided by feeding 1 output (1-1) -th bit of register 17 to control input (1-1) -th group of inputs of switch 13. In this mode, counters 5 and 9 form address codes, and distributor 4 pulses and a bus switch 12 - N sequences of input pulses as well as in control mode. When a fault is detected, the level 1 from the output of the Comparison unit 14 passes through the AND 15 element, the OR 23 element at the input of the HE element 24, and the AND 2 element stops passing the clock pulses. In this case, the display unit 11 indicates the code of the number of the faulty channel, and the display unit 20 indicates the number of the ILC stage in which the fault is detected. From these data, a faulty CMP is established. If during N cycles the malfunction in (1-1) -th stage is not detected, the overflow pulse of counter 9 will pass through the element OR 16 and shift 1 from (1-1) -th bit to (-2) -th discharge. A fault finding will start at the (-2) th stage of the ILC,

Thus, consistently, starting with the penultimate (1-1) -th stage and up to the first, a fault search is conducted. If in 1- (1-1) step failure was not detected, but in the control mode the fault was fixed, it means a fault in the last step. After troubleshooting in stage I, the overflow pulse of counter 9 shifts 1 from the first register register 17 to the last. Block 18 indicates a fault in the last stage of the ILC. By the difference from 1 to O of the first register bit 17, the pulse shaper 27 generates a pulse, which sets the trigger 22 to 1. The counters 5 and 9 stop counting the pulses, and the block 11 indicates the zero state of the counter 9.

A device for controlling a multiplexer as compared with a prototype device has a wider range of application due to the possibility to determine faulty elements in multi-stage multiplexers with a large number of channels.

Claims (1)

Claims An apparatus for controlling a multiplexer, comprising a clock pulse generator, four counters, a pulse distributor, two indication units, three AND elements, the first OR element and the first NO element, the information output of the first counter being the device output for connecting to the address input controlled multiplexer, the output of the clock pulse generator is connected to the first input of the first element And, the output of which is connected to the first input of the second element And, the start input of the impulse distributor Both the counter and the counting input of the second counter, the overflow output of which is connected to the reset inputs of the second and third counters, the counting input of the first counter and the first input of the third element I, the overflow output of the first counter connected to its reset input, the output of the third element I connected to the counting input of the fourth counter whose overflow output is connected to its reset input and the input of the first display unit, the output of the first element OR is NOT connected to the second input of the first element AND through the first element, the output is the second An element I is connected to a counting input of a third counter, characterized in that, in order to expand the field of application due to the possibility of determining a faulty element in multi-stage multiplexers, it contains two switches, a shift register, a comparison unit, a third indication unit, a trigger, a pulse shaper, the three AND elements, the second OR element, and the NOT element, the output of the first switch being the output of the device for connecting to the information input of the monitored multiplexer, information and control The first inputs of the first switch are connected respectively to the output of the pulse distributor and the information output of the second counter, the overflow output of which is connected to the first input of the fourth And element, the output of the More And comparison block is connected to the second input of the fourth And element and to the first input of the fifth And element, the output of which is connected with the first input of the first element OR, the output of the fourth element AND is connected to the first input of the second element OR, the second input of which and the first input of the sixth element AND are connected to the output of The outputs of the second counter, the output of the second element OR are connected to the synchronous input of the shift register, the output group of which is connected to the input group of the second display unit and the control inputs of the corresponding channels of the second switch, the information inputs of the channels are a group of device inputs for connecting to the outputs of the corresponding steps of the monitored multiplexer , the output of the second switch is connected to the second input of the second element, And the information output of the third counter is connected to the first input of the block The comparison, the second input of which is connected to the code input of the device, the output Equality of the comparison block is connected to the second input of the third element I, the information output of the first counter is connected to the input of the third display unit, the output of the last digit of the shift register is connected to the second input of the sixth element And, and through 0 the second element is NOT with the second input of the fifth element I, the overflow output of the fourth counter is connected to the third input of the sixth element I, the output of which is connected to the trigger synchronous input, the input of which is connected to the output of the first bit of the shift register, the output of the trigger 1 connected to the second input of the first element OR. C $ 7 ml u & CSI + / 77 / ss I S j FIG. 2 R Output -